Ayca Akkaya

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Yusuf Leblebici

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Publications

2021
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Firat Celik, Ayca Akkaya, Yusuf Leblebici:
A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI. Microelectron. J. 108: 104967 (2021)
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Ayca Akkaya, Firat Celik, Yusuf Leblebici:
An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2766-2774 (2021)
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Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1132-1140 (2021)
2020
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  - conf/iscas/AkkayaCL20
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Ayca Akkaya, Firat Celik, Yusuf Leblebici:
A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS. ISCAS 2020: 1-5
2019
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Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. NEWCAS 2019: 1-4
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Ayca Akkaya, Firat Celik, Yusuf Leblebici:
Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCs. NORCAS 2019: 1-7
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Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici:
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME 2019: 101-104
2018
[c1]
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Ayca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici:
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. NORCAS 2018: 1-6

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