Hiroe Iwasaki

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Yuya Omori

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Publications

2023
[j12]
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Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106(6): 312-320 (2023)
[j11]
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Daisuke Kobayashi, Ken Nakamura, Masaki Kitahara, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki:
A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. IEICE Trans. Inf. Syst. 106(1): 46-57 (2023)
2022
[c16]
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  - conf/coolchips/NakamuraOKNSSIK22
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Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS 2022: 1-3
[c15]
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  - conf/mwscas/WaidyasooriyaHI22
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Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano:
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4
[c14]
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  - conf/pdcat/SatoOENKIKK22
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Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT 2022: 288-300
2020
[j10]
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Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEICE Trans. Electron. 103-C(3): 77-84 (2020)
2019
[c13]
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  - conf/coolchips/NakamuraOKOONIS19
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Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS 2019: 1-3
[c12]
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  - conf/globecom/KobayashiNOOOI19
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Daisuke Kobayashi, Ken Nakamura, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki:
A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. GLOBECOM 2019: 1-6
[c11]
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  - conf/icecsys/OmoriNOKOI19
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Yuya Omori, Ken Nakamura, Takayuki Onishi, Daisuke Kobayashi, Tatsuya Osawa, Hiroe Iwasaki:
4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. ICECS 2019: 410-413
[c10]
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  - conf/iscas/OnishiONIS19
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Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki, Atsushi Shimizu:
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. ISCAS 2019: 1-5
2018
[j8]
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  - journals/tmscs/OmoriOIS18
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Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K. IEEE Trans. Multi Scale Comput. Syst. 4(4): 491-499 (2018)
2017
[c8]
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  - conf/coolchips/OmoriOIS17
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Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K. COOL Chips 2017: 1-3

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