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Shi-Yu Huang
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Publications
- 2001
- [j5]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001) - 2000
- [j4]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer:
AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000) - 1999
- [j3]Shi-Yu Huang, Kwang-Ting Cheng:
ErrorTracer: design error diagnosis based on fault simulation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1341-1352 (1999) - [j2]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1376-1384 (1999) - [j1]Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
Fault emulation: A new methodology for fault grading. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1487-1495 (1999) - 1998
- [c11]Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho:
A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556 - [c10]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu:
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637 - 1997
- [c9]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC 1997: 455-460 - [c8]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng:
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981 - [c7]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
Incremental logic rectification. VTS 1997: 143-149 - 1996
- [c6]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee:
Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164 - [c5]Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
Error Correction Based on Verification Techniques. DAC 1996: 258-261 - [c4]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277- - [c3]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee:
A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72 - [c2]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser:
An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874 - 1995
- [c1]Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686
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