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Nan Qi
Publications
- 2022
- [j41]Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi:
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1159-1170 (2022) - 2020
- [j26]Qiwen Liao, Nan Qi, Miaofeng Li, Shang Hu, Jian He, Bozhi Yin, Jingbo Shi, Jian Liu, Patrick Yin Chiang, Xi Xiao, Nanjian Wu:
A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. IEEE J. Solid State Circuits 55(5): 1282-1296 (2020) - [c36]Dan Li, Shengwei Gao, Yongjun Shi, Xiaoyan Gui, Nan Qi, Zhiyong Li, Quan Pan, Patrick Chiang, Li Geng:
A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. ISCAS 2020: 1-4 - 2019
- [j19]Juncheng Wang, Quan Pan, Yajie Qin, Xuefeng Chen, Shang Hu, Rui Bai, Xin Wang, Yaxin Cai, Tao Xia, Yuanxi Zhang, Jianxu Ma, Nan Qi, Patrick Yin Chiang:
A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1698-1702 (2019) - [c29]Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang:
A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. OFC 2019: 1-3 - 2018
- [c25]Juncheng Wang, Xuefeng Chen, Shang Hu, Yaxin Cai, Rui Bai, Xin Wang, Yuanxi Zhang, Shenglong Zhuo, Chang Liu, Bozhi Yin, Jianxu Ma, Hao Yan, Jiangao Xuan, Milton Lu, Tao Xia, Nan Qi, Patrick Yin Chiang:
A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. A-SSCC 2018: 67-68 - [c20]Chang Liu, Bozhi Yin, Tingyu Yao, Nan Qi, Dan Li, Jingbo Shi, Juncheng Wang, Hu Shang, Rui Bai, Patrick Yin Chiang:
A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. OFC 2018: 1-3 - 2017
- [c19]Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang:
A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. A-SSCC 2017: 89-92 - 2016
- [c14]Nan Qi, Xi Xiao, Shang Hu, Miaofeng Li, Hao Li, Zhiyong Li, Patrick Chiang:
A 32Gb/s NRZ, 25GBaud/s PAM4 reconfigurable, Si-Photonic MZM transmitter in CMOS. OFC 2016: 1-3 - 2015
- [j6]Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang:
A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS. IEEE J. Solid State Circuits 50(12): 3145-3159 (2015) - [c13]Shuo Li, Nan Qi, Vahid Behravan, Zhiliang Hong, Patrick Yin Chiang:
A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system. ASICON 2015: 1-4 - [c11]Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang:
22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS. ISSCC 2015: 1-3 - [c9]Nan Qi, Xianyao Li, Hao Li, Xi Xiao, Lei Wang, Zhiyong Li, Zhuo Gao, Yude Yu, Miki Moyal, Patrick Chiang:
A 25Gb/s, 520mW, 6.4Vpp Silicon-Photonic Mach-Zehnder Modulator with distributed driver in CMOS. OFC 2015: 1-3 - 2014
- [j4]Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan:
A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS. IEEE J. Solid State Circuits 49(12): 3018-3030 (2014) - [c7]Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan:
9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS. ISSCC 2014: 168-169 - 2012
- [j3]Yang Xu, Baoyong Chi, Xiaobao Yu, Nan Qi, Patrick Chiang, Zhihua Wang:
Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver. IEEE Trans. Circuits Syst. II Express Briefs 59-II(1): 30-34 (2012) - [j2]Nan Qi, Yang Xu, Baoyong Chi, Yang Xu, Xiaobao Yu, Xing Zhang, Ni Xu, Patrick Chiang, Woogeun Rhee, Zhihua Wang:
A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1720-1732 (2012)
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