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Ying Zhang 0016
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Publications
- 2017
- [j9]Ying Zhang, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Andrew Herdrich, Lu Peng:
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications. IEEE Syst. J. 11(4): 2096-2107 (2017) - [j8]Shaoming Chen, Samuel Irving, Lu Peng, Yue Hu, Ying Zhang, Ashok Srivastava:
Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors. IEEE Trans. Parallel Distributed Syst. 28(1): 274-289 (2017) - 2016
- [j7]Ying Zhang, Samuel Irving, Lu Peng, Xin Fu, David M. Koppelman, Weihua Zhang, Jesse Ardonne:
Design space exploration for device and architectural heterogeneity in chip-multiprocessors. Microprocess. Microsystems 40: 88-101 (2016) - 2015
- [j6]Ying Zhang, Sui Chen, Lu Peng, Shaoming Chen:
NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity. Integr. 51: 10-20 (2015) - [j5]Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors. Microprocess. Microsystems 39(4-5): 271-285 (2015) - [j4]Shaoming Chen, Lu Peng, Yue Hu, Zhou Zhao, Ashok Srivastava, Ying Zhang, Jin-Woo Choi, Bin Li, Edward Song:
Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching. IEEE Trans. Emerg. Top. Comput. 3(4): 489-501 (2015) - 2014
- [j3]Ying Zhang, Lide Duan, Bin Li, Lu Peng, Xin Fu:
Design configuration selection for hard-error reliable processors via statistical rules. Microprocess. Microsystems 38(1): 22-30 (2014) - [j2]Lide Duan, Ying Zhang, Bin Li, Lu Peng:
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules. IEEE Trans. Computers 63(9): 2201-2214 (2014) - [c11]Ying Zhang, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Andrew Herdrich, Lu Peng:
QoS management on heterogeneous architecture for parallel applications. ICCD 2014: 332-339 - [c10]Shaoming Chen, Yue Hu, Ying Zhang, Lu Peng, Jesse Ardonne, Samuel Irving, Ashok Srivastava:
Increasing off-chip bandwidth in multi-core processors with switchable pins. ISCA 2014: 385-396 - [c9]Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors. ISQED 2014: 660-666 - [c8]Ying Zhang, Sui Chen, Lu Peng, Shaoming Chen:
Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity. ISVLSI 2014: 577-582 - 2013
- [c7]Ying Zhang, Lu Peng, Xin Fu, Yue Hu:
Lighting the dark silicon by exploiting heterogeneity on future processors. DAC 2013: 82:1-82:7 - 2012
- [c6]Ying Zhang, Lide Duan, Bin Li, Lu Peng:
Optimal microarchitectural design configuration selection for processor hard-error reliability. ISQED 2012: 91-96 - 2011
- [c5]Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, Jih-Kwon Peir:
Statistical GPU power analysis using tree-based methods. IGCC 2011: 1-6 - [c4]Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, Jih-Kwon Peir:
Tree structured analysis on GPU power study. ICCD 2011: 57-64 - [c3]Ying Zhang, Lu Peng, Bin Li, Jih-Kwon Peir, Jianmin Chen:
Architecture comparisons between Nvidia and ATI GPUs: Computation parallelism and data communications. IISWC 2011: 205-215 - [c2]Lide Duan, Ying Zhang, Bin Li, Lu Peng:
Universal rules guided design parameter selection for soft error resilient processors. ISPASS 2011: 247-256 - [c1]Ying Zhang, Yue Hu, Bin Li, Lu Peng:
Performance and Power Analysis of ATI GPU: A Statistical Approach. NAS 2011: 149-158 - 2010
- [j1]Ying Zhang, Lu Peng, Wencheng Lu, Lide Duan, Suresh Rai:
Expediating IP lookups with reduced power via TBM and SST supernode caching. Comput. Commun. 33(3): 390-397 (2010)
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