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Natividad Martínez Madrid

◀ ▶ joint publications with Peter T. Breuer

> Home > Persons > Natividad Martínez Madrid

Publications

1999
[c7]
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  - conf/date/BreuerMBFLK99
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  - https://dblp.org/rec/conf/date/BreuerMBFLK99
Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, Maria M. Larrondo-Petrie, Carlos Delgado Kloos:
Reasoning about VHDL and VHDL-AMS using Denotational Semantics. DATE 1999: 346-352
1998
[c6]
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  dblp key:
  - conf/nada/BreuerMK98
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  - https://dblp.org/rec/conf/nada/BreuerMK98
Peter T. Breuer, Natividad Martínez Madrid, Carlos Delgado Kloos:
The Computational Description of Analogue System Behaviour. Prospects for Hardware Foundations 1998: 309-332
1997
[j1]
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  - journals/toplas/BreuerKLMF97
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  - https://dblp.org/rec/journals/toplas/BreuerKLMF97
Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez Fernández:
A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL. ACM Trans. Program. Lang. Syst. 19(4): 585-616 (1997)
[c5]
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  - conf/charme/MadridBK97
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Natividad Martínez Madrid, Peter T. Breuer, Carlos Delgado Kloos:
A semantic model for VHDL-AMS. CHARME 1997: 106-123
1996
[c3]
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  - conf/ecrts/BreuerMSMK96
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Peter T. Breuer, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín, Carlos Delgado Kloos:
A Formal Method for Specification and Refinement of Real-Time Systems. RTS 1996: 200-204
[c2]
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  - conf/eurodac/BreuerKMSM96
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  - https://dblp.org/rec/conf/eurodac/BreuerKMSM96
Peter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín:
A refinement calculus for VHDL. EURO-DAC 1996: 482-487
1995
[c1]
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  - conf/eurodac/BreuerM95
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Peter T. Breuer, Natividad Martínez Madrid:
A native process algebra for VHDL. EURO-DAC 1995: 420-426

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