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Xiaoliang Bai
- > Home > Persons > Xiaoliang Bai
Publications
- 2007
- [j5]Chong Zhao, Xiaoliang Bai, Sujit Dey:
Evaluating Transient Error Effects in Digital Nanometer Circuits. IEEE Trans. Reliab. 56(3): 381-391 (2007) - 2005
- [j4]Chong Zhao, Sujit Dey, Xiaoliang Bai:
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. IEEE Des. Test Comput. 22(4): 362-375 (2005) - [c11]Chong Zhao, Xiaoliang Bai, Sujit Dey:
A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits. ITC 2005: 10 - 2004
- [j3]Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1256-1263 (2004) - [j2]Xiaoliang Bai, Sujit Dey:
High-level crosstalk defect Simulation methodology for system-on-chip interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1355-1361 (2004) - [c10]Chong Zhao, Xiaoliang Bai, Sujit Dey:
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. DAC 2004: 894-899 - 2003
- [c8]Xiaoliang Bai, Li Chen, Sujit Dey:
Software-based self-test methodology for crosstalk faults in processors. HLDVT 2003: 11-16 - [c7]Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Noise-Aware Driver Modeling for Nanometer Technology. ISQED 2003: 177-182 - [c6]Xiaoliang Bai, Sujit Dey, Angela Krstic:
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ITC 2003: 112-121 - 2002
- [j1]Li Chen, Xiaoliang Bai, Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. J. Electron. Test. 18(4-5): 529-538 (2002) - 2001
- [c4]Li Chen, Xiaoliang Bai, Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. DAC 2001: 317-320 - [c3]Xiaoliang Bai, Sujit Dey:
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. VTS 2001: 169-177 - 2000
- [c2]Xiaoliang Bai, Sujit Dey, Janusz Rajski:
Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC 2000: 619-624 - 1999
- [c1]Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao:
Fault modeling and simulation for crosstalk in system-on-chip interconnects. ICCAD 1999: 297-303
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