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Tamás Roska
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Publications
- 2013
- [j77]Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Péter Földesy, Alberto Rodríguez-Pérez, Carlos M. Domínguez-Matas, Jorge Fernández-Berni, Gustavo Liñán Cembrano, Maria Belen Pérez-Verdú, Zoltán Kárász, Manuel Suárez-Cambre, Víctor Manuel Brea Sánchez, Tamás Roska, Ángel Rodríguez-Vázquez:
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips. J. Syst. Archit. 59(10-A): 908-919 (2013) - 2009
- [c38]Péter Földesy, Ricardo Carmona-Galán, Ákos Zarándy, Csaba Rekeczky, Ángel Rodríguez-Vázquez, Tamás Roska:
3D multi-layer vision architecture for surveillance and reconnaissance applications. ECCTD 2009: 185-188 - 2004
- [j53]Dávid Bálya, István Petrás, Tamás Roska, Ricardo Carmona, Ángel Rodríguez-Vázquez:
Implementing the Multilayer Retinal Model on the Complex-Cell CNN-um Chip Prototype. Int. J. Bifurc. Chaos 14(2): 427-451 (2004) - 2003
- [j46]István Petrás, Csaba Rekeczky, Tamás Roska, Ricardo Carmona, Francisco Jiménez-Garrido, Ángel Rodríguez-Vázquez:
Exploration Of Spatial-Temporal Dynamic Phenomena In A 32*32-Cell Stored Program Two-Layer CNN Universal Machine Chip Prototype. J. Circuits Syst. Comput. 12(6): 691-710 (2003) - [j44]Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Tamás Roska, Csaba Rekeczky, István Petrás, Ángel Rodríguez-Vázquez:
A bio-inspired two-layer mixed-signal flexible programmable chip for early vision. IEEE Trans. Neural Networks 14(5): 1313-1336 (2003) - 1999
- [j33]Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez, Servando Espejo-Meana, Rafael Domínguez-Castro, Tamás Roska, Tibor Kozek, Leon O. Chua:
An 0.5-µm CMOS Analog Random Access Memory Chip for TeraOPS Speed Multimedia Video Processing. IEEE Trans. Multim. 1(2): 121-135 (1999) - 1997
- [j20]Rafael Domínguez-Castro, Servando Espejo, Ángel Rodríguez-Vázquez, Ricardo Carmona, Péter Földesy, Ákos Zarándy, Péter Szolgay, Tamás Szirányi, Tamás Roska:
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage. IEEE J. Solid State Circuits 32(7): 1013-1026 (1997)
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