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Hao San
Publications
- 2023
- [j17]Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta:
Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(5): 823-831 (2023) - 2021
- [c27]Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta:
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. ISPACS 2021: 1-2 - [c26]Taichi Maebou, Yuanchi Chen, Eiki Kayama, Kenta Mori, Hao San, Tatsuji Matsuura, Masao Hotta:
A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. ISPACS 2021: 1-2 - [c25]Kenta Mori, Eiki Kayama, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta:
A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. ISPACS 2021: 1-2 - 2019
- [c23]Shuichiro Yamada, Toshiki Ohtsu, Minami Sasaki, Hao San, Tatsuji Matsuura, Masao Hotta:
A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. ISPACS 2019: 1-2 - 2017
- [j11]Hao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara:
A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 534-540 (2017) - [c20]Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta:
A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. ASP-DAC 2017: 15-16 - [c19]Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San, Masao Hotta:
Non-binary cyclic ADC with correlated level shifting technique. ASP-DAC 2017: 17-18 - [c18]Koken Chin, Yuta Mishima, Yuki Watanabe, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta:
A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. ISPACS 2017: 602-605 - [c17]Hiroyuki Tsuchiya, Yuki Watanabe, Koken Chin, Hao San, Tatsuji Matsuura, Masao Hotta:
The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. ISPACS 2017: 606-610 - [c16]Yuki Watanabe, Koken Chin, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta:
Experimental results of reconfigurable non-binary cyclic ADC. ISPACS 2017: 611-615 - 2015
- [c11]Yuta Mishima, Toshiki Yamada, Asato Uchiyama, Tatsuji Matsuura, Hao San, Masao Hotta:
A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. ISPACS 2015: 294-298 - 2014
- [j10]Rompei Sugawara, Hao San, Kazuyuki Aihara, Masao Hotta:
Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm. IEICE Trans. Electron. 97-C(4): 308-315 (2014) - [c9]Hao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara:
An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. CICC 2014: 1-4 - 2013
- [j9]Hao San, Tomonari Kato, Tsubasa Maruyama, Kazuyuki Aihara, Masao Hotta:
Non-binary Pipeline Analog-to-Digital Converter Based on β-Expansion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 415-421 (2013) - [j8]Rie Suzuki, Tsubasa Maruyama, Hao San, Kazuyuki Aihara, Masao Hotta:
Robust Cyclic ADC Architecture Based on β-Expansion. IEICE Trans. Electron. 96-C(4): 553-559 (2013) - [c8]Takaki Makino, Yukiko Iwata, Yutaka Jitsumatsu, Masao Hotta, Hao San, Kazuyuki Aihara:
Rigorous analysis of quantization error of an A/D converter based on β-map. ISCAS 2013: 369-372 - 2010
- [j6]Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori:
SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 415-423 (2010) - [c7]Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori:
Non-binary SAR ADC with digital error correction for low power applications. APCCAS 2010: 196-199 - 2008
- [c6]Tomohiko Ogawa, Haruo Kobayashi, Masao Hotta, Yosuke Takahashi, Hao San, Nobukazu Takai:
SAR ADC algorithm with redundancy. APCCAS 2008: 268-271 - 2007
- [j3]Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. 90-C(6): 1181-1188 (2007) - [c3]Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Masao Hotta:
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. ASP-DAC 2007: 96-97 - 2006
- [j2]Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 908-915 (2006)
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