Ken Chang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Mohamed Elzeftawi

> Home > Persons > Ken Chang

Publications

2017
[j14]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/FransSZUIKEHPAB17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/FransSZUIKEHPAB17
Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, Vassili Kireev, Mohamed Elzeftawi, Hiva Hedayati, Toan Pham, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang:
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. IEEE J. Solid State Circuits 52(4): 1101-1110 (2017)
2016
[j10]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/FransMHENLIUC16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/FransMHENLIUC16
Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang:
A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET. IEEE J. Solid State Circuits 51(12): 3167-3177 (2016)
[c24]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/FransMHENLIUC16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/FransMHENLIUC16
Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang:
3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. ISSCC 2016: 68-70
[c23]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/ElkholyEECH16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/ElkholyEECH16
Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu:
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. ISSCC 2016: 192-193
[c21]
- view
  authority control:
- export record
  dblp key:
  - conf/vlsic/FransEHIKPSUZAB16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/FransEHIKPSUZAB16
Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang:
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. VLSI Circuits 2016: 1-2

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.