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Weizheng Wang
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Publications
- 2023
- [j69]Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin:
Four-input-C-element-based multiple-node-upset-self-recoverable latch designs. Integr. 90: 11-21 (2023) - [j68]Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu:
Low-power and high-speed SRAM cells for double-node-upset recovery. Integr. 91: 1-9 (2023) - [j67]Weizheng Wang, Jian Liang, Xiangqi Wang, Xianmin Pan, Shuo Cai:
A secure scan architecture using parallel latch-based lock. Integr. 93: 102067 (2023) - [j63]Shuo Cai, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li:
A highly reliable and low-power cross-coupled 18T SRAM cell. Microelectron. J. 134: 105729 (2023) - [c16]Shuo Cai, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu:
A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design. ATS 2023: 1-5 - 2022
- [j42]Shuo Cai, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu:
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation. J. Electron. Test. 38(2): 165-180 (2022) - [j22]Weizheng Wang, Xiangqi Wang, Jin Wang, Neal N. Xiong, Shuo Cai, Peng Liu:
Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture. IEEE Trans. Syst. Man Cybern. Syst. 52(3): 2009-2023 (2022) - 2021
- [j18]Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han:
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. IEEE Trans. Emerg. Top. Comput. 9(2): 745-758 (2021) - [c7]Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang:
A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design. ITC-Asia 2021: 1-5 - 2020
- [j17]Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li:
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. J. Electron. Test. 36(4): 469-483 (2020) - 2019
- [j15]Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu, Shuo Cai:
A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks. IEEE Access 7: 22206-22213 (2019) - [j14]Shuo Cai, Weizheng Wang, Fei Yu, Binyong He:
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. J. Electron. Test. 35(2): 163-172 (2019) - [j11]Weizheng Wang, Zhuo Deng, Jin Wang, Arun Kumar Sangaiah, Shuo Cai, Zafer Al-Makhadmeh, Amr Tolba:
Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications. Sensors 19(20): 4598 (2019) - 2018
- [c3]Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai:
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. ATS 2018: 25-29 - 2017
- [j9]Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang:
Reliability evaluation of logic circuits based on transient faults propagation metrics. IEICE Electron. Express 14(7): 20170128 (2017) - 2013
- [j5]Weizheng Wang, Peng Liu, Shuo Cai, Lingyun Xiang:
Low power logic BIST with high test effectiveness. IEICE Electron. Express 10(23): 20130853 (2013)
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