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Parag Upadhyaya

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Zhaoyin Daniel Wu

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Publications

2022
[j9]
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  - journals/jssc/PoonZCMWCLHLWTU22
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  - https://dblp.org/rec/journals/jssc/PoonZCMWCLHLWTU22
Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans:
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. IEEE J. Solid State Circuits 57(4): 1199-1210 (2022)
2021
[c22]
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  - conf/vlsic/PoonZCM00LHLWTU21
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  - https://dblp.org/rec/conf/vlsic/PoonZCM00LHLWTU21
Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans:
A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. VLSI Circuits 2021: 1-2
2015
[j2]
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  - journals/jssc/FransCEAFTJBIUW15
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Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang:
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. IEEE J. Solid State Circuits 50(8): 1932-1944 (2015)
[c9]
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  - conf/isscc/UpadhyayaSABJXW15
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Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang:
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. ISSCC 2015: 1-3
2014
[c8]
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  - conf/cicc/SavojACEFFHIJTUWC14
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Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang:
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. CICC 2014: 1-4
2013
[j1]
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  - journals/jssc/SavojHAGIJJKLRTUWC13
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Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang:
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. IEEE J. Solid State Circuits 48(11): 2582-2594 (2013)
2012
[c6]
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  - conf/cicc/SavojHUAIJKLWAC12
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Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang:
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. CICC 2012: 1-4
[c4]
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  - conf/vlsic/SavojHUABCJLPST12
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Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang:
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. VLSIC 2012: 104-105

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