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Andreas G. Veneris
- > Home > Persons > Andreas G. Veneris
Publications
- 2007
- [c38]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543 - 2005
- [j7]Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi:
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electron. Test. 21(5): 495-502 (2005) - [c26]Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour:
Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196 - [c24]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876 - [c23]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47 - 2004
- [c20]Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir:
Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209 - [c19]Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri:
Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) 2004: 221-224 - [c18]Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49 - 2003
- [c17]Andreas G. Veneris, Alexander Smith, Magdy S. Abadir:
Logic verification based on diagnosis techniques. ASP-DAC 2003: 93-98 - 2002
- [j3]Andreas G. Veneris, Magdy S. Abadir:
Design rewiring using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1469-1479 (2002) - [c13]Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir:
Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE 2002: 716-721 - [c11]Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri:
Design Rewiring Using ATPG. ITC 2002: 223-232 - [c9]Jiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir:
Efficient and Exact Diagnosis of Multiple Stuck-At Faults. LATW 2002: 132-136 - 2001
- [c8]Andreas G. Veneris, Magdy S. Abadir, Ivor Ting:
Design rewiring based on diagnosis techniques. ASP-DAC 2001: 479-484 - [c7]Ivor Ting, Andreas G. Veneris, Magdy S. Abadir:
ATPG Driven Logic Synthesis for Delay and Power Minimization. LATW 2001: 96-99 - 2000
- [c6]Andreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji:
Design Optimization Based on Diagnosis Techniques. LATW 2000: 244-249
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