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Dipanjan Sengupta
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Publications
- 2015
- [c13]Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris:
Constructing stability-based clock gating with hierarchical clustering. PATMOS 2015: 97-102 - 2013
- [c9]Bao Le, Dipanjan Sengupta, Andreas G. Veneris:
Reviving erroneous stability-based clock-gating using partial Max-SAT. ASP-DAC 2013: 717-722 - [c7]Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos:
Accelerating post silicon debug of deep electrical faults. IOLTS 2013: 61-66 - [c6]Dipanjan Sengupta, Erhan Ergin, Andreas G. Veneris:
Early detection of current hot spots in power gated designs. ISLPED 2013: 45-50 - 2012
- [j3]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov:
Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. 2(2): 58-70 (2012) - [c5]Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov:
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. ACM Great Lakes Symposium on VLSI 2012: 189-194 - 2011
- [c4]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh:
Sequence pair based voltage island floorplanning. IGCC 2011: 1-6 - 2009
- [j2]Dipanjan Sengupta, Resve A. Saleh:
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 316-326 (2009) - 2008
- [c3]Dipanjan Sengupta, Resve A. Saleh:
Application-driven floorplan-aware voltage island design. DAC 2008: 155-160 - [c2]Dipanjan Sengupta, Resve A. Saleh:
Supply voltage selection in Voltage Island based SoC design. SoCC 2008: 219-222 - 2007
- [j1]Dipanjan Sengupta, Resve A. Saleh:
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 183-189 (2007) - 2005
- [c1]Dipanjan Sengupta, Resve A. Saleh:
Power-Delay Metrics Revisited for 90nm CMOS Technology. ISQED 2005: 291-296
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