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Semantic ScholarGrace Li Zhang
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2010 – today
- 2019
[j2]Grace Li Zhang
, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann:
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 38(4): 705-718 (2019)- [c8]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing. DATE 2019: 1751-1756 - 2018
- [j1]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. IEEE Trans. on CAD of Integrated Circuits and Systems 37(2): 392-405 (2018) - [c7]Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC 2018: 26:1-26:6 - [c6]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c5]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. ISVLSI 2018: 715-718 - 2017
- [c4]Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann:
Application of machine learning methods in post-silicon yield improvement. SoCC 2017: 243-248 - [i4]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability. CoRR abs/1705.04990 (2017) - [i3]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. CoRR abs/1705.04992 (2017) - [i2]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model. CoRR abs/1705.04993 (2017) - [i1]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. CoRR abs/1705.04995 (2017) - 2016
- [c3]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. DAC 2016: 60:1-60:6 - [c2]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based buffer insertion for post-silicon yield improvement under process variability. DATE 2016: 1457-1460 - [c1]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model. ICCAD 2016: 100
Coauthor Index
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