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ORCIDSergey Ostanin
Person information
- affiliation: Tomsk State University, Russia
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2010 – 2019
- 2019
[c26]Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov:
Masking Robust Testable PDFs. EWDTS 2019: 1-4- 2018
- [c25]Anzhela Yu. Matrosova, Sergey Ostanin:
Trojan circuits masking and debugging of combinational circuits with LUT insertion. AQTR 2018: 1-6 - [c24]Sergey Ostanin, Valentina Andreeva
, Natalia Butorina, D. Tretyakov:
Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults. EWDTS 2018: 1-4 - [c23]Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov:
Finding False Paths for Sequential Circuits Using Operations on ROBDDs. IOLTS 2018: 240-242 - 2017
- [c22]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko:
Preventing and masking Trojan circuits triggering out of working area. ECCTD 2017: 1-4 - [c21]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergey Ostanin, Ekaterina Nikolaeva:
Detection and masking of Trojan Circuits in sequential logic. EWDTS 2017: 1-4 - [c20]Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina:
Logic circuit design with gates, LUTs and MUXs oriented to mask faults. EWDTS 2017: 1-4 - [c19]Sergey Ostanin:
Self-checking synchronous FSM network design for path delay faults. EWDTS 2017: 1-4 - [c18]Anjela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko:
Trojan circuits preventing and masking in sequential circuits. IOLTS 2017: 213-214 - 2016
- [c17]Anjela Yu. Matrosova, Sergey Ostanin, Valentina Andreeva:
Patching circuit design based on reserved CLBs. AQTR 2016: 1-5 - [c16]Sergey Ostanin, Anzhela Yu. Matrosova, Natalia Butorina, V. Lavrov:
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit. EWDTS 2016: 1-4 - [c15]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva:
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors. IOLTS 2016: 5-6 - 2015
- [c14]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko:
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit. DDECS 2015: 267-270 - [c13]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva:
Fault-tolerant high performance scheme design. EWDTS 2015: 1-4 - [c12]Sergey Ostanin, Irina Kirienko, V. Lavrov:
A fault-tolerant combinational circuit design. EWDTS 2015: 1-4 - 2014
- [c11]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh:
Partially programmable circuit design. EWDTS 2014: 1-4 - 2013
- [j2]Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh:
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. 74(7): 1164-1177 (2013) - [c10]Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh:
Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. EWDTS 2013: 1-6 - [c9]Sergey Ostanin:
Testable combinational circuit design based on free ZDD-implementation of irredundant SOPof Boolean function. EWDTS 2013: 1-4 - 2011
- [c8]Natalia Butorina, Sergey Ostanin:
Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker. EWDTS 2011: 255-258 - 2010
- [c7]Sergey Ostanin, R. Muchamedov:
Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function. EWDTS 2010: 171-174
2000 – 2009
- 2007
- [c6]Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva:
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs. DFT 2007: 206-214 - 2002
- [c5]Roman Goot, Ilya Levin, Sergei Ostanin:
Fault Latencies of Concurrent Checking FSMs. DSD 2002: 174-179 - [c4]Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky:
Self-checking sequential circuits with self-healing ability. ACM Great Lakes Symposium on VLSI 2002: 71-76 - [c3]Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin:
Sequential Circuits Applicable for Detecting Different Types of Faults. IOLTW 2002: 44- - 2001
- [c2]Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin:
Survivable Self-Checking Sequential Circuits. DFT 2001: 395-402 - 2000
- [j1]Anzhela Yu. Matrosova, Ilya Levin, Sergey Ostanin:
Self-checking Synchronous FSM Network Design with Low Overhead. VLSI Design 11(1): 47-58 (2000) - [c1]Anzhela Yu. Matrosova, Sergey Ostanin:
Self-Checking FSM Design with Observing only FSM Outputs. IOLTW 2000: 153-154
Coauthor Index
aka: Anjela Yu. Matrosova
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last updated on 2023-09-28 02:32 CEST by the dblp team
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