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ORCIDZoltán Nagy 0001
Person information
- affiliation: Hungarian Academy of Sciences, Institute for Computer Science and Control, Budapest, Hungary
- affiliation: Péter Pázmány Catholic University, Budapest, Hungary
- affiliation (former): University of Veszprém, Hungary
Other persons with the same name
- Zoltán Nagy — disambiguation page
- Zoltán Nagy 0002
![[0000-0002-6014-3228]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-6014-3228")
— University of Texas at Austin, TX, USA (and 1 more) - Zoltán Nagy 0003 — University of Zurich, Switzerland (and 2 more)
- Zoltán Nagy 0004 — Sommelweiss University, Budapest, Hungary
- Zoltán Nagy 0005 — Dresden University of Technology, Germany
- Zoltán Nagy 0006 — Technical University of Cluj-Napoca, Department of Automation, Romania
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2020 – today
- 2022
[j13]Attila Fejér, Zoltán Nagy, Jenny Benois-Pineau, Péter Szolgay, Aymar de Rugy, Jean-Philippe Domenger:
Hybrid FPGA-CPU-Based Architecture for Object Recognition in Visual Servoing of Arm Prosthesis. J. Imaging 8(2): 44 (2022)- 2021
- [j12]Attila Fejér, Zoltán Nagy, Jenny Benois-Pineau, Péter Szolgay, Aymar de Rugy, Jean-Philippe Domenger:
Implementation of Scale Invariant Feature Transform detector on FPGA for low-power wearable devices for prostheses control. Int. J. Circuit Theory Appl. 49(7): 2255-2273 (2021) - [j11]Laszlo Schäffer, Zoltán Nagy, Zoltán Kincses, Richárd Fiáth, István Ulbert:
Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA. IEEE Trans. Biomed. Eng. 68(1): 99-108 (2021)
2010 – 2019
- 2019
- [c22]Attila Fejér, Zoltán Nagy, Jenny Benois-Pineau, Péter Szolgay, Aymar de Rugy, Jean-Philippe Domenger:
FPGA-based SIFT implementation for wearable computing. DDECS 2019: 1-4 - 2017
- [c21]András Kiss, Zoltán Nagy, György Csaba:
Fast evaluation of magnetic fields with multipole method implemented on FPGA. ECCTD 2017: 1-4 - [c20]Laszlo Schäffer, Zoltán Nagy, Zoltán Kincses, Richárd Fiáth:
FPGA-based real-time multichannel neural dataset generation. ECCTD 2017: 1-4 - [c19]Laszlo Schäffer, Zoltán Nagy, Zoltán Kincses, Richárd Fiáth:
FPGA-based neural probe positioning to improve spike sorting with OSort algorithm. ISCAS 2017: 1-4 - 2016
- [j10]Ákos Zarándy, Máté Németh, Zoltán Nagy, András Kiss, Levente Santha, Tamás Zsedrovits:
A real-time multi-camera vision system for UAV collision warning and navigation. J. Real Time Image Process. 12(4): 709-724 (2016) - 2015
- [c18]Ákos Zarándy, Máté Németh, Borbala Jani Matyasne Pencz, Zoltán Nagy, Tamás Zsedrovits:
Cellular sensor-processor array based visual collision warning sensor. ISCAS 2015: 1973-1976 - [c17]Endre László, Zoltán Nagy, Michael B. Giles, István Z. Reguly, Jeremy Appleyard, Péter Szolgay:
Analysis of parallel processor architectures for the solution of the Black-Scholes PDE. ISCAS 2015: 1977-1980 - [c16]András Kiss, Zoltán Nagy, Péter Szolgay, György Csaba, Xiaobo Sharon Hu, Wolfgang Porod:
Emulating massively parallel non-Boolean operators on FPGA. ISCAS 2015: 1981-1984 - 2014
- [j9]Zoltán Nagy, Csaba Nemes, Antal Hiba, Árpád Csík, András Kiss, Miklós Ruszinkó, Péter Szolgay:
Accelerating unstructured finite volume computations on field-programmable gate arrays. Concurr. Comput. Pract. Exp. 26(3): 615-643 (2014) - [j8]Csaba Nemes, Gergely Barcza, Zoltán Nagy, Örs Legeza, Péter Szolgay:
The density matrix renormalization group algorithm on kilo-processor architectures: Implementation and trade-offs. Comput. Phys. Commun. 185(6): 1570-1581 (2014) - [i3]Zoltán Nagy, Csaba Nemes, Antal Hiba, Árpád Csík, András Kiss, Miklós Ruszinkó, Péter Szolgay:
Accelerating unstructured finite volume computations on field-programmable gate arrays. CoRR abs/1408.5715 (2014) - 2013
- [c15]Bence J. Borbely, Zoltán Kincses, Zsolt Vörösházi, Zoltán Nagy, Péter Szolgay:
Analysis of myoelectric signals using a Field Programmable SoC. ECCTD 2013: 1-4 - [c14]András Kiss, Zoltán Nagy, Péter Szolgay, Tamás Roska, György Csaba, Xiaobo Sharon Hu, Wolfgang Porod:
FPGA-implementation of a holographic pattern-matching algorithm. ECCTD 2013: 1-4 - [c13]Csaba Nemes, Gergely Barcza, Zoltán Nagy, Ors Legeza, Péter Szolgay:
Implementation trade-offs of the density matrix renormalization group algorithm on kilo-processor architectures. ECCTD 2013: 1-4 - [c12]Ákos Zarándy, Zoltán Nagy, Bálint Vanek, Tamás Zsedrovits, András Kiss, Máté Németh:
A Five-Camera Vision System for UAV Visual Attitude Calculation and Collision Warning. ICVS 2013: 11-20 - 2012
- [c11]Zoltán Nagy, Csaba Nemes, Antal Hiba, András Kiss, Árpád Csík, Péter Szolgay:
FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry. FPL 2012: 128-135 - [c10]Zoltán Nagy, András Kiss, Ákos Zarándy, Tamás Zsedrovits, Bálint Vanek, Tamas Peni, Jozsef Bokor, Tamás Roska:
Volume and power optimized high-performance system for UAV collision avoidance. ISCAS 2012: 189-192 - 2011
- [j7]Zoltán Kincses, László Orzó, Zoltán Nagy, György Mezo, Péter Szolgay:
High-Speed, SAD Based Wavefront Sensor Architecture Implementation on FPGA. J. Signal Process. Syst. 64(3): 279-290 (2011) - [c9]Csaba Nemes, Zoltán Nagy, Péter Szolgay:
Efficient mapping of mathematical expressions to FPGAs: Exploring different design methodologies. ECCTD 2011: 717-720
2000 – 2009
- 2009
- [j6]Sándor Kocsárdi, Zoltán Nagy, Árpád Csík, Péter Szolgay:
Simulation of Two-Dimensional Supersonic Flows on Emulated-Digital CNN-UM. EURASIP J. Adv. Signal Process. 2009 (2009) - [j5]Zsolt Vörösházi, Zoltán Nagy, Péter Szolgay:
FPGA-Based Real Time, Multichannel Emulated-Digital Retina Model Implementation. EURASIP J. Adv. Signal Process. 2009 (2009) - [j4]Sándor Kocsárdi, Zoltán Nagy, Árpád Csík, Péter Szolgay:
Simulation of 2D inviscid, adiabatic, compressible flows on emulated digital CNN-UM. Int. J. Circuit Theory Appl. 37(4): 569-585 (2009) - [c8]Zoltán Kincses, Zoltán Nagy, László Orzó, Péter Szolgay, György Mezo:
Implementation of a parallel SAD based wavefront sensor architecture on FPGA. ECCTD 2009: 823-826 - [c7]Zoltán Nagy, András Kiss, Sándor Kocsárdi, Árpád Csík:
Computational fluid flow simulation on body fitted mesh geometry with IBM cell broadband engine architecture. ECCTD 2009: 827-830 - [c6]Zoltán Nagy, András Kiss, Sándor Kocsárdi, Árpád Csík:
Supersonic Flow Simulation on IBM Cell Processor based Emulated Digital Cellular Neural Networks. ISCAS 2009: 1225-1228 - 2008
- [b1]Zoltán Nagy:
Emulált digitális CNN-UM architektúra megvalósítása újrakonfigurálható áramkörökön és alkalmazásai. University of Pannonia, Hungary, 2008 - [j3]Zsolt Vörösházi, András Kiss, Zoltán Nagy, Péter Szolgay:
Implementation of embedded emulated-digital CNN-UM global analogic programming unit on FPGA and its application. Int. J. Circuit Theory Appl. 36(5-6): 589-603 (2008) - [j2]Zoltán Nagy, László Kék, Zoltán Kincses, András Kiss, Péter Szolgay:
Toward exploitation of cell multi-processor array in time-consuming applications by using CNN model. Int. J. Circuit Theory Appl. 36(5-6): 605-622 (2008) - [i2]Sándor Kocsárdi, Zoltán Nagy, Árpád Csík, Péter Szolgay:
Supersonic Flow Simulation on Emulated Digital Cellular Neural Networks. ERCIM News 2008(74) (2008) - [i1]Zoltán Nagy, László Kék, Zoltán Kincses, András Kiss, Péter Szolgay:
Exploitation of Cell Multi-Processor Array in Solution of Spatio-Temporal Dynamics. ERCIM News 2008(74) (2008) - 2007
- [c5]Zoltán Nagy, László Kék, Zoltán Kincses, Péter Szolgay:
CNN model on cell multiprocessor array. ECCTD 2007: 276-279 - [c4]Péter Sonkoly, István Noé, José M. Carcione, Zoltán Nagy, Péter Szolgay:
CNN-UM based transversely isotropic elastic wave propagation simulation. ECCTD 2007: 284-287 - [c3]Sándor Kocsárdi, Zoltán Nagy, Péter Szolgay:
Emulated digital CNN solution for two dimensional compressible flows. ECCTD 2007: 288-291 - 2006
- [j1]Zoltán Nagy, Zsolt Vörösházi, Péter Szolgay:
Emulated digital CNN-UM solution of partial differential equations. Int. J. Circuit Theory Appl. 34(4): 445-470 (2006) - [c2]Zoltán Nagy, Zsolt Vörösházi, Péter Szolgay:
An advanced emulated digital retina model on FPGA to implement a real-time test environment. ISCAS 2006 - 2002
- [c1]Zoltán Nagy, Péter Szolgay:
Configurable multi-layer CNN-UM emulator on FPGA using distributed arithmetic. ICECS 2002: 1251-1254
Coauthor Index
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