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ORCIDPing Lu 0002
Person information
- affiliation: Lund University, Department of Electrical and Information Technology, Sweden
- affiliation (PhD 2007): Fudan University, Department of Microelectronics Engineering, Shanghai, China
Other persons with the same name
- Ping Lu — disambiguation page
- Ping Lu 0001 — University of Science and Technology of China, School of Information Science and Technology, Hefei, China
- Ping Lu 0003
![[0000-0002-0199-3783]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-0199-3783")
— University of Bern, Institute for Surgical Technology and Biomechanics, Switzerland - Ping Lu 0004 — National Research Council Canada, Ottawa, ON, Canada
- Ping Lu 0005 — Beihang University, School of Computer Science and Engineering, SKLSDE, Beijing, China
- Ping Lu 0006 — Huazhong University of Science and Technology, School of Optical and Electronic Information, Wuhan National Laboratory for Optoelectronics and National Engineering Laboratory for Next Generation Internet Access System, Wuhan, China (and 1 more)
- Ping Lu 0007 — Beihang University, Beijing Advanced Innovation Center for Big Data and Brain Computing, Beijing, China (and 1 more)
- Ping Lu 0008 — Zhongxing Telecom Equipment (ZTE) Corporation, Cloud Computing and IT Institute, Big Data Research Institute, Shenzhen, China (and 2 more)
- Ping Lu 0009 — Chinese Academy of Sciences, Institute of Acoustics, ThinkIT Speech Lab, Beijing, China
- Ping Lu 0010 — Tongji University, College of Surveying and Geo-Informatics, Shanghai, China (and 2 more)
- Ping Lu 0011 — San Diego State University, Department of Aerospace Engineering, San Diego, CA, USA (and 1 more)
- Ping Lu 0012 — Xiamen University of Technology, School of Economic and Management, Xiamen, China
- Ping Lu 0013 — Tongji University, Department of Control Science and Engineering, Frontiers Science Center for Intelligent Autonomous Systems, Shanghai, China (and 1 more)
- Ping Lu 0014 — University of Science and Technology of China, National Synchrotron Radiation Laboratory, Hefei, China
- Ping Lu 0015 — OFS Fitel, Avon, CT, USA (and 2 more)
- Ping Lu 0016 — Sichuan University, School of Electronics and Information Engineering, Chengdu, China
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2020 – today
- 2020
[j4]Ying Wu, Ping Lu, Robert Bogdan Staszewski:
A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2532-2545 (2020)
2010 – 2019
- 2017
- [j3]Ying Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski:
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise. IEEE J. Solid State Circuits 52(7): 1885-1903 (2017) - 2016
- [j2]Ping Lu, Ying Wu, Pietro Andreani:
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1019-1023 (2016) - [c12]Ying Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski:
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. ESSCIRC 2016: 209-212 - 2015
- [c11]Ahmed Mahmoud, Pietro Andreani, Ping Lu:
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise. NORCAS 2015: 1-4 - 2014
- [c10]Ping Lu, Pietro Andreani:
A 1-1 MASH 2-D vernier time-to-digital converter with 2nd-order noise shaping. ISCAS 2014: 1324-1327 - [c9]Ji Wang, Manuel Bejarano Carmona, Helgi Hall, Dejan Radjen, Ping Lu:
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio. NORCHIP 2014: 1-4 - 2013
- [c8]Dawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee:
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. ISCAS 2013: 169-172 - 2012
- [j1]Ping Lu, Antonio Liscidini, Pietro Andreani:
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps. IEEE J. Solid State Circuits 47(7): 1626-1635 (2012) - [c7]Ping Lu, Ying Wu, Pietro Andreani:
A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter. ISCAS 2012: 2593-2596 - [c6]Ping Lu, Pietro Andreani, Antonio Liscidini:
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter. NORCHIP 2012: 1-4 - 2011
- [c5]Ping Lu, Pietro Andreani, Antonio Liscidini:
A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs. ESSCIRC 2011: 459-462 - [c4]Mohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani:
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS. NORCHIP 2011: 1-4 - [c3]Muhammad Shakir, Mohammed Abdulaziz, Ping Lu, Pietro Andreani:
A mixed mode design flow for multi GHz ADPLLs. NORCHIP 2011: 1-4 - [c2]Ying Wu, Ping Lu, Pietro Andreani:
A digital PLL with a multi-delay coarse-fine TDC. NORCHIP 2011: 1-4 - [c1]Ying Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland:
A 0.13µm CMOS ΔΣ PLL FM transmitter. NORCHIP 2011: 1-4
Coauthor Index
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