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2010 – today
- 2019
[j79]Zhanwei Zhong
, Zipeng Li, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques. IEEE Trans. Biomed. Circuits and Systems 13(2): 292-313 (2019)- [j78]Heng-Wei Hsu, Tung-Yu Wu, Sheng Wan, Wing Hung Wong, Chen-Yi Lee:
QuatNet: Quaternion-Based Head Pose Estimation With Multiregression Loss. IEEE Trans. Multimedia 21(4): 1035-1046 (2019) - [c109]Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips. ASP-DAC 2019: 468-473 - [c108]Yun-Sheng Chan, Kuan-Yu Lung, Yun-Ming Wang, Chen-Yi Lee:
Joint Capacitive Sensing and Frequency Selection for Fast Medical Tests. ISCAS 2019: 1-5 - [c107]Eugene Lee, Tsu-Jui Hsu, Chen-Yi Lee:
Centralized State Sensing using Sensor Array on Wearable Device. ISCAS 2019: 1-5 - [c106]Yun-Wen Lu, Antoon Purnal, Simon Vandenhende, Chen-Yi Lee, Ingrid Verbauwhede, Hsie-Chia Chang:
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR. VLSI-DAT 2019: 1-4 - 2018
- [j77]Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu:
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. J. Solid-State Circuits 53(11): 3314-3326 (2018) - [j76]Zipeng Li, Kelvin Yi-Tse Lai, John McCrone, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee:
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip. IEEE Trans. on CAD of Integrated Circuits and Systems 37(3): 601-614 (2018) - [j75]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 37(5): 968-981 (2018) - [c105]Yi-Wei Chen, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee:
Diabetic Retinopathy Detection Based on Deep Convolutional Neural Networks. ICASSP 2018: 1030-1034 - [c104]Sheng Wan, Tung-Yu Wu, Wing H. Wong, Chen-Yi Lee:
Confnet: Predict with Confidence. ICASSP 2018: 2921-2925 - [c103]Heng-Wei Hsu, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee:
Correlation-Based Face Detection for Recognizing Faces in Videos. ICASSP 2018: 3101-3105 - [c102]Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee:
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. VLSI-DAT 2018: 1-4 - 2017
- [j74]Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee:
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications. J. Solid-State Circuits 52(10): 2601-2612 (2017) - [j73]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. IEEE Trans. Biomed. Circuits and Systems 11(3): 612-626 (2017) - [j72]Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips. IEEE Trans. Biomed. Circuits and Systems 11(6): 1380-1391 (2017) - [j71]Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee:
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications. IEEE Trans. on Circuits and Systems 64-I(9): 2522-2531 (2017) - [c101]Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw:
Design considerations and clinical applications of closed-loop neural disorder control SoCs. ASP-DAC 2017: 295-298 - [c100]Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips. ISVLSI 2017: 146-151 - 2016
- [j70]Yingchieh Ho, Shu-Yu Hsu, Chen-Yi Lee:
A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces. IEEE Trans. on Circuits and Systems 63-II(2): 161-165 (2016) - [j69]Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. IEEE Trans. on Circuits and Systems 63-II(9): 863-867 (2016) - [c99]Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee:
A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications. A-SSCC 2016: 265-268 - [c98]Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. A-SSCC 2016: 337-340 - [c97]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
High-level synthesis for micro-electrode-dot-array digital microfluidic biochips. DAC 2016: 146:1-146:6 - [c96]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee:
Error recovery in a micro-electrode-dot-array digital microfluidic biochip? ICCAD 2016: 105 - [c95]Yingchieh Ho, Gary Wang, Kelvin Yi-Tse Lai, Yi-Wen Lu, Keng-Ming Liu, Yun-Ming Wang, Chen-Yi Lee:
Design of a micro-electrode cell for programmable lab-on-CMOS platform. ISCAS 2016: 2871-2874 - [c94]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips. ITC 2016: 1-10 - 2015
- [j68]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. on Circuits and Systems 62-I(2): 507-516 (2015) - [j67]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. on Circuits and Systems 62-II(3): 301-305 (2015) - [j66]Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. IEEE Trans. on Circuits and Systems 62-I(10): 2523-2532 (2015) - [j65]Chang-Hung Tsai, Yu-Ting Chih, Wing Hung Wong, Chen-Yi Lee:
A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System. IEEE Trans. on Circuits and Systems 62-II(11): 1073-1077 (2015) - [j64]Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. IEEE Trans. VLSI Syst. 23(1): 88-97 (2015) - [j63]Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. IEEE Trans. VLSI Syst. 23(7): 1235-1244 (2015) - [j62]Kelvin Yi-Tse Lai, Yu-Tao Yang, Chen-Yi Lee:
An Intelligent Digital Microfluidic Processor for Biomedical Detection. Signal Processing Systems 78(1): 85-93 (2015) - [c93]Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee:
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. A-SSCC 2015: 1-4 - [c92]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015: 96-99 - [c91]Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee:
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS 2015: 1450-1453 - [c90]Ping-Yuan Tsai, Yu-Yun Chang, Shu-Yu Hsu, Chen-Yi Lee:
An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver. VLSI-DAT 2015: 1-4 - 2014
- [j61]Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee:
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. J. Solid-State Circuits 49(4): 801-811 (2014) - [j60]Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Trans. on Circuits and Systems 61-I(7): 2110-2118 (2014) - [j59]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. IEEE Trans. VLSI Syst. 22(1): 49-61 (2014) - [c89]Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee:
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. A-SSCC 2014: 229-232 - [c88]Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee:
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. A-SSCC 2014: 293-296 - [c87]Chang-Hung Tsai, Hui-Hsuan Lee, Wan-Ju Yu, Chen-Yi Lee:
A 2 GOPS quad-mean shift processor with early termination for machine learning applications. ISCAS 2014: 157-160 - [c86]Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS 2014: 409-412 - [c85]Chen-Yi Lee, Kelvin Yi-Tse Lai, Shu-Yu Hsu:
Event-driven read-out circuits for energy-efficient sensor-SoC's. VLSI-DAT 2014: 1-2 - [c84]Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee:
A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. VLSIC 2014: 1-2 - 2013
- [j58]Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang:
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access 1: 123-130 (2013) - [j57]Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. IEEE Trans. VLSI Syst. 21(11): 2160-2164 (2013) - [c83]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Processor with side-channel attack resistance. ISSCC 2013: 50-51 - [c82]Kelvin Yi-Tse Lai, Yu-Tao Yang, Gary Wang, Yi-Wen Lu, Chen-Yi Lee:
A digital microfluidic processor for biomedical applications. SiPS 2013: 54-58 - 2012
- [j56]Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. J. Solid-State Circuits 47(4): 817-831 (2012) - [j55]Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. J. Solid-State Circuits 47(9): 2246-2257 (2012) - [j54]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine. IEEE Trans. on Circuits and Systems 59-II(2): 103-107 (2012) - [j53]Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. IEEE Trans. on Circuits and Systems 59-II(5): 287-291 (2012) - [j52]Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee:
A Low-Power DCO Using Interlaced Hysteresis Delay Cells. IEEE Trans. on Circuits and Systems 59-II(10): 673-677 (2012) - [j51]Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee:
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling. IEEE Trans. VLSI Syst. 20(9): 1615-1620 (2012) - [c81]Chia-Lin Liu, Chang-Hung Tsai, Hsiuan-Ting Wang, Yao Li, Chen-Yi Lee:
A memory-efficient architecture for intra predictor and de-blocking filter in video coding system. APCCAS 2012: 555-558 - [c80]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. CHES 2012: 548-564 - [c79]Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. ISCAS 2012: 1456-1459 - [c78]Yi-Huan Ou-Yang, Chien-Yu Kao, Jen-Yuan Hsu, Pangan Ting, Chen-Yi Lee:
Extrinsic data compression method for double-binary turbo codes. ISCAS 2012: 1775-1778 - [c77]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Stochastic decoding for LDPC convolutional codes. ISCAS 2012: 2621-2624 - [c76]Daisuke Yamaguchi, Takumi Yajima, Chen-Yi Lee, Hiromasa Shimada, Yuki Kinebuchi, Tatsuo Nakajima:
Spatial Isolation on Realtime Hypervisor using Core-local Memory. PECCS 2012: 415-421 - [c75]Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A low cost DPA-resistant 8-bit AES core based on ring oscillators. VLSI-DAT 2012: 1-4 - [c74]Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee:
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC 2012: 156-157 - 2011
- [j50]Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee:
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters. J. Solid-State Circuits 46(11): 2514-2523 (2011) - [j49]Chien-Chen Lin, Yao Li, Chen-Yi Lee:
A Predefined Bit-Plane Comparison Coding for Mobile Video Applications. IEEE Trans. on Circuits and Systems 58-II(7): 437-441 (2011) - [j48]Wei-Hao Sung, Jui-Yuan Yu, Chen-Yi Lee:
A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems. IEEE Trans. on Circuits and Systems 58-II(10): 637-641 (2011) - [j47]Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. on Circuits and Systems 58-II(10): 682-686 (2011) - [j46]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. IEEE Trans. VLSI Syst. 19(6): 1113-1117 (2011) - [j45]Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, Chen-Yi Lee:
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. Signal Processing Systems 64(2): 241-248 (2011) - [c73]Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee:
A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications. A-SSCC 2011: 189-192 - [c72]Shu-Yu Hsu, Yao-Lin Chen, Po-Yao Chang, Jui-Yuan Yu, Ten-Fang Yang, Ray-Jade Chen, Chen-Yi Lee:
A micropower biomedical signal processor for mobile healthcare applications. A-SSCC 2011: 301-304 - [c71]Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. ESSCIRC 2011: 71-74 - [c70]Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems. ESSCIRC 2011: 79-82 - [c69]Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, Jui-Yuan Yu, Chen-Yi Lee:
A low power all-digital signal component separator for uneven multi-level LINC systems. ESSCIRC 2011: 403-406 - [c68]Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. ISCAS 2011: 713-716 - [c67]Ming-Yu Kuo, Yao Li, Chen-Yi Lee:
An area-efficient high-accuracy prediction-based CABAC decoder architecture for H.264/AVC. ISCAS 2011: 1960-1963 - [c66]Tsung-Han Lin, Yuki Kinebuchi, Alexandre Courbot, Hiromasa Shimada, Takushi Morita, Hitoshi Mitake, Chen-Yi Lee, Tatsuo Nakajima:
Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design. ISORC 2011: 241-249 - [c65]Tsung-Han Lin, Yuki Kinebuchi, Hiromasa Shimada, Hitoshi Mitake, Chen-Yi Lee, Tatsuo Nakajima:
Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design. RTCSA (2) 2011: 101-105 - [c64]Ping-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee:
A low-power all-digital phase modulator pair for LINC transmitters. SoCC 2011: 48-51 - [c63]Tzu-Chun Shih, Tsan-Wen Chen, Wei-Hao Sung, Ping-Yuan Tsai, Chen-Yi Lee:
An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications. SoCC 2011: 371-375 - 2010
- [j44]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. IEICE Electronic Express 7(9): 634-639 (2010) - [j43]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electronics 6(4): 551-562 (2010) - [j42]Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. J. Solid-State Circuits 45(2): 422-432 (2010) - [j41]Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. J. Solid-State Circuits 45(11): 2330-2340 (2010) - [j40]Chen-Fong Hsiao, Yuan Chen, Chen-Yi Lee:
A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors. IEEE Trans. on Circuits and Systems 57-II(1): 26-30 (2010) - [j39]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. IEEE Trans. on Circuits and Systems 57-II(7): 546-550 (2010) - [j38]Shu-Yu Hsu, Jui-Yuan Yu, Chen-Yi Lee:
A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications. IEEE Trans. on Circuits and Systems 57-II(12): 951-955 (2010) - [c62]Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee:
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. APCCAS 2010: 1203-1206 - [c61]Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An improved soft BCH decoder with one extra error compensation. ISCAS 2010: 3941-3944 - [c60]Chen-Yi Lee, Song-Bin Huang, Kang-Yi Lien, Ming-Yang Lin, Gwo-Bin Lee:
Tunable magnetic alginate microspheres by using a microfluidic device. NEMS 2010: 441-444
2000 – 2009
- 2009
- [j37]Tsan-Wen Chen, Jui-Yuan Yu, Chien-Ying Yu, Chen-Yi Lee:
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications. J. Solid-State Circuits 44(11): 2966-2976 (2009) - [j36]Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. on Circuits and Systems 56-II(9): 734-738 (2009) - [j35]Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee:
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. on Circuits and Systems 56-I(9): 1960-1967 (2009) - [c59]Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. CICC 2009: 191-194 - [c58]Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee:
An eCrystal Oscillator with Self-calibration Capability. ISCAS 2009: 237-240 - [c57]Yu-Fan Lai, Tsu-Ming Liu, Yao Li, Chen-Yi Lee:
Design of an Intra Predictor with Data Reuse for High-profile H.264 Applications. ISCAS 2009: 3018-3021 - 2008
- [j34]Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. J. Solid-State Circuits 43(3): 684-694 (2008) - [j33]Yuan Chen, Yu-Wei Lin, Yu-Chi Tsao, Chen-Yi Lee:
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems. J. Solid-State Circuits 43(5): 1260-1273 (2008) - [j32]Yuan Chen, Yu-Chi Tsao, Yu-Wei Lin, Chin-Hung Lin, Chen-Yi Lee:
An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications. IEEE Trans. on Circuits and Systems 55-II(2): 146-150 (2008) - [j31]Jui-Yuan Yu, Ching-Che Chung, Chen-Yi Lee:
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. IEEE Trans. on Circuits and Systems 55-II(9): 922-926 (2008) - [j30]Tsu-Ming Liu, Chen-Yi Lee:
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. Signal Processing Systems 50(1): 69-80 (2008) - [c56]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. APCCAS 2008: 850-853 - [c55]Wei-Chin Lee, Yao Li, Chen-Yi Lee:
Design of a memory-based VLC decoder for portable video applications. APCCAS 2008: 1340-1343 - [c54]Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder. ISCAS 2008: 752-755 - 2007
- [j29]Lei-Fone Chen, Chen-Yi Lee:
Design of a DVB-T/H COFDM Receiver for Portable Video Applications [Topics in Circuits for Communications]. IEEE Communications Magazine 45(8): 112-120 (2007) - [j28]Terng-Ren Hsu, Chien-Ching Lin, Terng-Yin Hsu, Chen-Yi Lee:
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications. IEICE Transactions 90-A(4): 879-884 (2007) - [j27]Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Jiun-Yan Yang, Kang-Cheng Hou, Chen-Yi Lee:
A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications. J. Solid-State Circuits 42(1): 161-169 (2007) - [j26]Yu-Wei Lin, Chen-Yi Lee:
Design of an FFT/IFFT Processor for MIMO OFDM Systems. IEEE Trans. on Circuits and Systems 54-I(4): 807-815 (2007) - [j25]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. IEEE Trans. on Circuits and Systems 54-II(11): 954-958 (2007) - [j24]Tsu-Ming Liu, Sheng-Zen Wang, Bai-Jue Shieh, Chen-Yi Lee:
A New Soft Variable Length Decoder for Wireless Video Transmission. IEEE Trans. Circuits Syst. Video Techn. 17(2): 224-236 (2007) - [j23]Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee:
An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule. IEEE Trans. Circuits Syst. Video Techn. 17(7): 937-943 (2007) - [c53]Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC 2007: 273-276 - [c52]Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee:
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. ISSCC 2007: 364-609 - [c51]