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ORCIDAntonio González 0001
Person information
- affiliation: Polytechnic University of Catalonia (UPC), Department of Computer Architecture
- affiliation: Intel Labs, Intel Barcelona Research Center
Other persons with the same name
- Antonio González — disambiguation page
- Antonio González 0002 — University College London
- Antonio González 0003 — Adasa Sistemas S.A.U., Barcelona, Spain
- Antonio González 0004
![[0000-0003-2690-0472]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-2690-0472")
(aka: Antonio González Sorribes) — University of Zaragoza, Spain (and 1 more) - Antonio González Muñoz (aka: Antonio González 0005) — University of Granada, Department of Computer Science and Artificial Ingelligence, Spain
- Antonio González 0006 (aka: Antonio González Torres) — Costa Rica Institute of Technology, Cartago, Costa Rica (and 2 more)
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2020 – today
- 2024
[i23]Rodrigo Huerta, Mojtaba Abaie Shoushtary, Antonio González:
Analyzing and Improving Hardware Modeling of Accel-Sim. CoRR abs/2401.10082 (2024)- 2023
- [j92]Raúl Taranco, José-María Arnau, Antonio González:
LOCATOR: Low-power ORB accelerator for autonomous cars. J. Parallel Distributed Comput. 174: 32-45 (2023) - [j91]Reza Yazdani Aminabadi, Olatunji Ruwase, Minjia Zhang, Yuxiong He, José-María Arnau, Antonio González:
SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks. ACM Trans. Embed. Comput. Syst. 22(2): 30:1-30:23 (2023) - [j90]Albert Segura, José-María Arnau, Antonio González:
Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads. J. Supercomput. 79(1): 762-787 (2023) - [c221]Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González:
Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs. PACT 2023: 124-136 - [c220]Bahareh Khabbazan, Marc Riera, Antonio González:
QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures. PACT 2023: 325-326 - [c219]Raúl Taranco, José-María Arnau, Antonio González:
SLIDEX: Sliding Window Extension for Image Processing. PACT 2023: 332-334 - [c218]Franyell Silfa, José-María Arnau, Antonio González:
Exploiting Kernel Compression on BNNs. DATE 2023: 1-6 - [c217]Pedro Henrique Exenberger Becker, José-María Arnau, Antonio González:
K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks. ISCA 2023: 20:1-20:13 - [c216]Raúl Taranco, José-María Arnau, Antonio González:
δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline. MICRO 2023: 1029-1043 - [i22]Pedro Henrique Exenberger Becker, José-María Arnau, Antonio González:
K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks. CoRR abs/2302.00361 (2023) - [i21]Mohammad Sabri, Marc Riera, Antonio González:
ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inference. CoRR abs/2306.16298 (2023) - [i20]Bahareh Khabbazan, Marc Riera, Antonio González:
DNA-TEQ: An Adaptive Exponential Quantization of Tensors for DNN Inference. CoRR abs/2306.16430 (2023) - [i19]Mojtaba Abaie Shoushtary, José-María Arnau, Jordi Tubella Murgadas, Antonio González:
A Lightweight, Compiler-Assisted Register File Cache for GPGPU. CoRR abs/2310.17501 (2023) - [i18]Bahareh Khabbazan, Marc Riera, Antonio González:
An Energy-Efficient Near-Data Processing Accelerator for DNNs that Optimizes Data Accesses. CoRR abs/2310.18181 (2023) - [i17]Nitesh Narayana GS, Marc Ordoñez, Lokananda Hari, Franyell Silfa, Antonio González:
ReuseSense: With Great Reuse Comes Greater Efficiency; Effectively Employing Computation Reuse on General-Purpose CPUs. CoRR abs/2311.10487 (2023) - 2022
- [j89]Marc Riera, José-María Arnau, Antonio González:
DNN pruning with principal component analysis and connection importance estimation. J. Syst. Archit. 122: 102336 (2022) - [j88]Marc Riera, José-María Arnau, Antonio González:
CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs. J. Syst. Archit. 129: 102604 (2022) - [j87]Mehdi Hassanpour, Marc Riera, Antonio González:
A Survey of Near-Data Processing Architectures for Neural Networks. Mach. Learn. Knowl. Extr. 4(1): 66-102 (2022) - [j86]Franyell Silfa, José-María Arnau, Antonio González:
E-BATCH: Energy-Efficient and High-Throughput RNN Batching. ACM Trans. Archit. Code Optim. 19(1): 14:1-14:23 (2022) - [j85]David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Joan-Manuel Parcerisa, Antonio González:
Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs. ACM Trans. Archit. Code Optim. 19(3): 39:1-39:20 (2022) - [j84]Albert Segura, José-María Arnau, Antonio González:
Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions. IEEE Trans. Computers 71(7): 1711-1723 (2022) - [j83]Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González:
Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs. J. Supercomput. 78(13): 14940-14964 (2022) - [j82]David Corbalán-Navarro, Juan L. Aragón, Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Antonio González:
Omega-Test: A Predictive Early-Z Culling to Improve the Graphics Pipeline Energy-Efficiency. IEEE Trans. Vis. Comput. Graph. 28(12): 4375-4388 (2022) - [c215]Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González:
TCOR: A Tile Cache with Optimal Replacement. HPCA 2022: 662-675 - [c214]Jorge Ortiz, David Corbalán-Navarro, Juan L. Aragón, Antonio González:
MEGsim: A Novel Methodology for Efficient Simulation of Graphics Workloads in GPUs. ISPASS 2022: 69-78 - [c213]Jorge Sierra Acosta, Andreas Diavastos, Antonio González:
XFeatur: Hardware Feature Extraction for DNN Auto-tuning. ISPASS 2022: 132-134 - [c212]Diya Joseph, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González:
DTexL: Decoupled Raster Pipeline for Texture Locality. MICRO 2022: 213-227 - [c211]David Corbalán-Navarro, Juan L. Aragón, Joan-Manuel Parcerisa, Antonio González:
DTM-NUCA: Dynamic Texture Mapping-NUCA for Energy-Efficient Graphics Rendering. PDP 2022: 144-151 - [i16]Dennis Pinto, José-María Arnau, Antonio González:
ASRPU: A Programmable Accelerator for Low-Power Automatic Speech Recognition. CoRR abs/2202.04971 (2022) - [i15]Dennis Pinto, José-María Arnau, Antonio González:
Mixture-of-Rookies: Saving DNN Computations by Predicting ReLU Outputs. CoRR abs/2202.04990 (2022) - [i14]Franyell Silfa, José-María Arnau, Antonio González:
Saving RNN Computations with a Neuron-Level Fuzzy Memoization Scheme. CoRR abs/2202.06563 (2022) - [i13]Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González:
Dynamic Sampling Rate: Harnessing Frame Coherence in Graphics Applications for Energy-Efficient GPUs. CoRR abs/2202.10533 (2022) - [i12]Franyell Silfa, José-María Arnau, Antonio González:
Exploiting Kernel Compression on BNNs. CoRR abs/2212.00608 (2022) - 2021
- [j81]Martí Anglada, Ramon Canal, Juan L. Aragón, Antonio González:
Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design. IEEE Trans. Sustain. Comput. 6(3): 427-440 (2021) - [c210]Raúl Taranco, José-María Arnau, Antonio González:
A Low-Power Hardware Accelerator for ORB Feature Extraction in Self-Driving Cars. SBAC-PAD 2021: 11-21 - [i11]Dennis Pinto, José-María Arnau, Antonio González:
Exploiting Beam Search Confidence for Energy-Efficient Speech Recognition. CoRR abs/2101.09083 (2021) - [i10]Marc Riera, José-María Arnau, Antonio González:
CREW: Computation Reuse and Efficient Weight Storage for Hardware-accelerated MLPs and RNNs. CoRR abs/2107.09408 (2021) - [i9]Mehdi Hassanpour, Marc Riera, Antonio González:
A Survey of Near-Data Processing Architectures for Neural Networks. CoRR abs/2112.12630 (2021) - 2020
- [j80]Dennis Pinto, José-María Arnau, Antonio González:
Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System. ACM Trans. Archit. Code Optim. 17(4): 41:1-41:19 (2020) - [j79]Reza Yazdani, José-María Arnau, Antonio González:
LAWS: Locality-AWare Scheme for Automatic Speech Recognition. IEEE Trans. Computers 69(8): 1197-1208 (2020) - [c209]Franyell Silfa, José-María Arnau, Antonio González:
Boosting LSTM Performance Through Dynamic Precision Selection. HiPC 2020: 323-333 - [c208]Pedro Henrique Exenberger Becker, José-María Arnau, Antonio González:
Demystifying Power and Performance Bottlenecks in Autonomous Driving Systems. IISWC 2020: 205-215 - [i8]Albert Segura, José-María Arnau, Antonio González:
Irregular Accesses Reorder Unit: Improving GPGPU Memory Coalescing for Graph-Based Workloads. CoRR abs/2007.07131 (2020) - [i7]Franyell Silfa, José-María Arnau, Antonio González:
E-BATCH: Energy-Efficient and High-Throughput RNN Batching. CoRR abs/2009.10656 (2020)
2010 – 2019
- 2019
- [j78]Marc Riera, José-María Arnau, Antonio González:
CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference. IEEE Micro 39(5): 36-45 (2019) - [j77]Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo:
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. IEEE Trans. Computers 68(5): 765-783 (2019) - [j76]Reza Yazdani, José-María Arnau, Antonio González:
A Low-Power, High-Performance Speech Recognition Accelerator. IEEE Trans. Computers 68(12): 1817-1831 (2019) - [j75]Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa, Antonio González:
Visibility Rendering Order: Improving Energy Efficiency on Mobile GPUs through Frame Coherence. IEEE Trans. Parallel Distributed Syst. 30(2): 473-485 (2019) - [c207]Reza Yazdani, José-María Arnau, Antonio González:
POSTER: Leveraging Run-Time Feedback for Efficient ASR Acceleration. PACT 2019: 463-464 - [c206]Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Pedro Marcuello, Antonio González:
Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline. HPCA 2019: 623-634 - [c205]Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Antonio González:
Early Visibility Resolution for Removing Ineffectual Computations in the Graphics Pipeline. HPCA 2019: 635-646 - [c204]Albert Segura, José-María Arnau, Antonio González:
SCU: a GPU stream compaction unit for graph processing. ISCA 2019: 424-435 - [c203]Franyell Silfa, Gem Dot, José-María Arnau, Antonio González:
Neuron-Level Fuzzy Memoization in RNNs. MICRO 2019: 782-793 - [i6]Marc Riera, José-María Arnau, Antonio González:
(Pen-) Ultimate DNN Pruning. CoRR abs/1906.02535 (2019) - [i5]Reza Yazdani, Olatunji Ruwase, Minjia Zhang, Yuxiong He, José-María Arnau, Antonio González:
LSTM-Sharp: An Adaptable, Energy-Efficient Hardware Accelerator for Long Short-Term Memory. CoRR abs/1911.01258 (2019) - [i4]Franyell Silfa, José-María Arnau, Antonio González:
Boosting LSTM Performance Through Dynamic Precision Selection. CoRR abs/1911.04244 (2019) - 2018
- [j74]Antonio González:
2018 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro 38(4): 76-77 (2018) - [j73]Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González:
Performance Analysis and Optimization of Automatic Speech Recognition. IEEE Trans. Multi Scale Comput. Syst. 4(4): 847-860 (2018) - [c202]Franyell Silfa, Gem Dot, José-María Arnau, Antonio González:
E-PUR: an energy-efficient processing unit for recurrent neural networks. PACT 2018: 18:1-18:12 - [c201]Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González:
A Novel Register Renaming Technique for Out-of-Order Processors. HPCA 2018: 259-270 - [c200]Marc Riera, José-María Arnau, Antonio González:
Computation Reuse in DNNs by Exploiting Input Similarity. ISCA 2018: 57-68 - [c199]Reza Yazdani, Marc Riera, José-María Arnau, Antonio González:
The Dark Side of DNN Pruning. ISCA 2018: 790-801 - [i3]Antonio González:
Trends in Processor Architecture. CoRR abs/1801.05215 (2018) - [i2]Martí Anglada, Enrique de Lucas, Joan-Manuel Parcerisa, Juan L. Aragón, Pedro Marcuello, Antonio González:
Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline. CoRR abs/1807.09449 (2018) - 2017
- [j72]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. J. Parallel Distributed Comput. 100: 30-41 (2017) - [j71]Reza Yazdani, Albert Segura, José-María Arnau, Antonio González:
Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator. IEEE Micro 37(1): 22-29 (2017) - [c198]Hamid Tabani, José-María Arnau, Jordi Tubella, Antonio González:
An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition. PACT 2017: 41-52 - [c197]Gem Dot, Alejandro Martínez, Antonio González:
Removing checks in dynamically typed languages through efficient profiling. CGO 2017: 257-268 - [c196]Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio González:
MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment. ISCA 2017: 241-254 - [c195]Reza Yazdani, José-María Arnau, Antonio González:
UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition. MICRO 2017: 69-81 - [i1]Franyell Silfa, Gem Dot, José-María Arnau, Antonio González:
E-PUR: An Energy-Efficient Processing Unit for Recurrent Neural Networks. CoRR abs/1711.07480 (2017) - 2016
- [j70]Gaurang Upasani, Xavier Vera, Antonio González:
A Case for Acoustic Wave Detectors for Soft-Errors. IEEE Trans. Computers 65(1): 5-18 (2016) - [j69]Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González:
An Energy-Efficient Memory Unit for Clustered Microarchitectures. IEEE Trans. Computers 65(8): 2631-2637 (2016) - [j68]Rakesh Kumar, Alejandro Martínez, Antonio González:
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. ACM Trans. Comput. Syst. 33(4): 12:1-12:33 (2016) - [j67]Sergi Abadal, Albert Mestres, Mario Nemirovsky, Heekwan Lee, Antonio González, Eduard Alarcón, Albert Cabellos-Aparicio:
Scalability of Broadcast Performance in Wireless Network-on-Chip. IEEE Trans. Parallel Distributed Syst. 27(12): 3631-3645 (2016) - [c194]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. Conf. Computing Frontiers 2016: 365-368 - [c193]Marc Riera, Ramon Canal, Jaume Abella, Antonio González:
A detailed methodology to compute Soft Error Rates in advanced technologies. DATE 2016: 217-222 - [c192]Gem Dot, Alejandro Martínez, Antonio González:
ERICO: Effective Removal of Inline Caching Overhead in Dynamic Typed Languages. HiPC 2016: 372-381 - [c191]Martí Anglada, Ramon Canal, Juan L. Aragón, Antonio González:
MASkIt: Soft error rate estimation for combinational circuits. ICCD 2016: 614-621 - [c190]José Cano, Rakesh Kumar, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio González:
Quantitative characterization of the software layer of a HW/SW co-designed processor. IISWC 2016: 138-147 - [c189]Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale:
Cross-layer system reliability assessment framework for hardware faults. ITC 2016: 1-10 - [c188]Reza Yazdani, Albert Segura, José-María Arnau, Antonio González:
An ultra low-power hardware accelerator for automatic speech recognition. MICRO 2016: 47:1-47:12 - 2015
- [c187]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Trevor E. Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio González, Lieven Eeckhout:
Chrysso: an integrated power manager for constrained many-core processors. Conf. Computing Frontiers 2015: 19:1-19:8 - [c186]Enrique de Lucas, Pedro Marcuello, Joan-Manuel Parcerisa, Antonio González:
Ultra-low power render-based collision detection for CPU/GPU systems. MICRO 2015: 445-456 - [c185]Gem Dot, Alejandro Martínez, Antonio González:
Analysis and Optimization of Engines for Dynamically Typed Languages. SBAC-PAD 2015: 41-48 - 2014
- [j66]Rakesh Kumar, Alejandro Martínez, Antonio González:
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment. ACM Trans. Archit. Code Optim. 11(3): 25:1-25:23 (2014) - [c184]Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert, Antonio González:
Accurate off-line phase classification for HW/SW co-designed processors. Conf. Computing Frontiers 2014: 5:1-5:10 - [c183]Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert, Antonio González:
Warm-Up Simulation Methodology for HW/SW Co-Designed Processors. CGO 2014: 284 - [c182]Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio:
INFORMER: An integrated framework for early-stage memory robustness analysis. DATE 2014: 1-4 - [c181]Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches. ICCD 2014: 68-74 - [c180]Antonio González, Carlos Aliagas:
Author retrospective for the dual data cache. ICS 25th Anniversary 2014: 32-34 - [c179]Gaurang Upasani, Xavier Vera, Antonio González:
Framework for economical error recovery in embedded cores. IOLTS 2014: 146-153 - [c178]Stefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio González, Ramon Canal, Riccardo Mariani, M. Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenbach, Gulzaib Rafiq, Trond Loekstad:
Cross-layer early reliability evaluation: Challenges and promises. IOLTS 2014: 228-233 - [c177]Gaurang Upasani, Xavier Vera, Antonio González:
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. ISCA 2014: 37-48 - 2013
- [j65]Javier Lira, Carlos Molina, Ryan N. Rakvic, Antonio González:
Replacement techniques for dynamic NUCA cache designs on CMPs. J. Supercomput. 64(2): 548-579 (2013) - [c176]Aleksandar Brankovic, Kyriakos Stavrou, Enric Gibert, Antonio González:
Performance analysis and predictability of the software layer in dynamic binary translators/optimizers. Conf. Computing Frontiers 2013: 15:1-15:10 - [c175]Rakesh Kumar, Alejandro Martínez, Antonio González:
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment. HiPC 2013: 79-88 - [c174]Rakesh Kumar, Alejandro Martínez, Antonio González:
Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. HPCC/EUC 2013: 518-525 - [c173]Gaurang Upasani, Xavier Vera, Antonio González:
Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery. IOLTS 2013: 85-91 - [c172]Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González:
Deconfigurable microprocessor architectures for silicon debug acceleration. ISCA 2013: 631-642 - [c171]Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
Effectiveness of hybrid recovery techniques on parametric failures. ISQED 2013: 258-264 - [c170]Rakesh Kumar, Alejandro Martínez, Antonio González:
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment. SBAC-PAD 2013: 81-88 - 2012
- [j64]Abhishek Deb, Josep M. Codina, Antonio González:
A HW/SW Co-designed Programmable Functional Unit. IEEE Comput. Archit. Lett. 11(1): 9-12 (2012) - [j63]Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González:
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. Integr. 45(3): 246-252 (2012) - [j62]Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González:
The migration prefetcher: Anticipating data promotion in dynamic NUCA caches. ACM Trans. Archit. Code Optim. 8(4): 45:1-45:20 (2012) - [c169]Rakesh Kumar, Alejandro Martínez, Antonio González:
Speculative dynamic vectorization for HW/SW co-designed processors. PACT 2012: 459-460 - [c168]Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio:
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. ICCD 2012: 472-477 - [c167]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks. IPDPS Workshops 2012: 1190-1196 - [c166]Gaurang Upasani, Xavier Vera, Antonio González:
Setting an error detection infrastructure with low cost acoustic wave detectors. ISCA 2012: 333-343 - [c165]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Exploiting temporal locality in network traffic using commodity multi-cores. ISPASS 2012: 110-111 - [c164]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic. MASCOTS 2012: 439-448 - [c163]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
Improving the Resilience of an IDS against Performance Throttling Attacks. SecureComm 2012: 167-184 - [c162]Demos Pavlou, Enric Gibert, Fernando Latorre, Antonio González:
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support. VEE 2012: 159-168 - 2011
- [j61]Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González:
Implementing End-to-End Register Data-Flow Continuous Self-Test. IEEE Trans. Computers 60(8): 1194-1206 (2011) - [j60]Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
CROB: Implementing a Large Instruction Window through Compression. Trans. High Perform. Embed. Archit. Compil. 3: 115-134 (2011) - [j59]Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González:
Compiler Directed Issue Queue Energy Reduction. Trans. High Perform. Embed. Archit. Compil. 4: 42-62 (2011) - [c161]Abhishek Deb, Josep M. Codina, Antonio González:
A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit. Interaction between Compilers and Computer Architectures 2011: 1-8 - [c160]Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González:
Beforehand Migration on D-NUCA Caches. PACT 2011: 197-198 - [c159]Abhishek Deb, Josep M. Codina, Antonio González:
SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion. Conf. Computing Frontiers 2011: 1 - [c158]Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González:
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. ACM Great Lakes Symposium on VLSI 2011: 277-282 - [c157]Javier Lira, Carlos Molina, David M. Brooks, Antonio González:
Implementing a hybrid SRAM / eDRAM NUCA architecture. HiPC 2011: 1-10 - [c156]Antonio González:
Moore's law implications on energy reduction. HiPEAC 2011: 1-2 - [c155]Rakesh Ranjan, Fernando Latorre, Pedro Marcuello, Antonio González:
Fg-STP: Fine-Grain Single Thread Partitioning on Multicores. HPCA 2011: 15-24 - [c154]Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González:
Hardware/software-based diagnosis of load-store queues using expandable activity logs. HPCA 2011: 321-331 - [c153]Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors. ICCD 2011: 332-338 - [c152]Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber:
New reliability mechanisms in memory design for sub-22nm technologies. IOLTS 2011: 111-114 - [c151]Govind Sreekar Shenoy, Jordi Tubella, Antonio González:
A Performance and Area Efficient Architecture for Intrusion Detection Systems. IPDPS 2011: 301-310 - [c150]Javier Lira, Carlos Molina, Antonio González:
HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors. IPDPS 2011: 419-430 - [c149]Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González:
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems. ISLPED 2011: 379-384 - [c148]Indu Bhagat, Enric Gibert, F. Jesús Sánchez, Antonio González:
Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations. LCTES 2011: 161-170 - [c147]Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González:
Accelerating microprocessor silicon validation by exposing ISA diversity. MICRO 2011: 386-397 - [c146]Abhishek Deb, Josep M. Codina, Antonio González:
A Power-Efficient Co-designed Out-of-Order Processor. SBAC-PAD 2011: 1-8 - [c145]Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
Design of complex circuits using the Via-Configurable transistor array regular layout fabric. SoCC 2011: 166-169 - [c144]Ramon Canal, Antonio Rubio, A. Asenov, A. Brown, Miguel Miranda, Paul Zuber, Antonio González, Xavier Vera:
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. FET 2011: 148-149 - [e2]Ravi R. Iyer, Qing Yang, Antonio González:
38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA. ACM 2011, ISBN 978-1-4503-0472-6 [contents] - 2010
- [b1]Antonio González, Fernando Latorre, Grigorios Magklis:
Processor Microarchitecture: An Implementation Perspective. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2010, ISBN 978-3-031-00601-2 - [j58]Ryan N. Rakvic, José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Antonio González:
Energy efficiency via thread fusion and value reuse. IET Comput. Digit. Tech. 4(2): 114-125 (2010) - [j57]Ryan N. Rakvic, Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González:
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors. ACM Trans. Archit. Code Optim. 7(2): 9:1-9:25 (2010) - [j56]Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González:
Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum. IEEE Trans. Computers 59(12): 1598-1610 (2010) - [c143]Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. DATE 2010: 417-422 - [c142]Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González:
High-Performance low-vcc in-order core. HPCA 2010: 1-11 - [c141]Javier Lira, Carlos Molina, Antonio González:
The auction: optimizing banks usage in Non-Uniform Cache Architectures. ICS 2010: 37-47 - [c140]Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
MODEST: a model for energy estimation under spatio-temporal variability. ISLPED 2010: 129-134 - [c139]Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González:
MT-SBST: Self-test optimization in multithreaded multicore architectures. ITC 2010: 734-743 - [c138]Marc Lupon, Grigorios Magklis, Antonio González:
A Dynamically Adaptable Hardware Transactional Memory. MICRO 2010: 27-38 - [c137]Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
VCTA: A Via-Configurable Transistor Array regular fabric. VLSI-SoC 2010: 335-340
2000 – 2009
- 2009
- [j55]Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin:
Exploring the limits of early register release: Exploiting compiler analysis. ACM Trans. Archit. Code Optim. 6(3): 12:1-12:30 (2009) - [j54]Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin:
Energy-efficient register caching with compiler assistance. ACM Trans. Archit. Code Optim. 6(4): 13:1-13:23 (2009) - [j53]Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli:
AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. IEEE Trans. Computers 58(6): 770-783 (2009) - [j52]Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González:
Reducing Soft Errors through Operand Width Aware Policies. IEEE Trans. Dependable Secur. Comput. 6(3): 217-230 (2009) - [j51]Xavier Vera, Jaume Abella, Javier Carretero, Antonio González:
Selective replication: A lightweight technique for soft errors. ACM Trans. Comput. Syst. 27(4): 8:1-8:30 (2009) - [c136]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. PACT 2009: 15-25 - [c135]Marc Lupon, Grigorios Magklis, Antonio González:
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. PACT 2009: 293-302 - [c134]Antonio González:
Key Microarchitectural Innovations for Future Microprocessors. ARCS 2009: 2 - [c133]Javier Lira, Carlos Molina, Antonio González:
Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs. Euro-Par 2009: 297-308 - [c132]Rakesh Ranjan, Pedro Marcuello, Fernando Latorre, Antonio González:
P-slice based efficient speculative multithreading. HiPC 2009: 119-128 - [c131]Javier Lira, Carlos Molina, Antonio González:
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors. ICCD 2009: 275-281 - [c130]Matteo Monchiero, Ramon Canal, Antonio González:
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. ICPP 2009: 1-8 - [c129]Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González:
Online error detection and correction of erratic bits in register files. IOLTS 2009: 81-86 - [c128]Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González:
End-to-end register data-flow continuous self-test. ISCA 2009: 105-115 - [c127]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
Boosting single-thread performance in multi-core systems through fine-grain multi-threading. ISCA 2009: 474-483 - [c126]Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González:
Low Vccmin fault-tolerant cache with highly predictable performance. MICRO 2009: 111-121 - 2008
- [j50]Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz:
Refueling: Preventing Wire Degradation due to Electromigration. IEEE Micro 28(6): 37-46 (2008) - [j49]Matteo Monchiero, Ramon Canal, Antonio González:
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. IEEE Trans. Parallel Distributed Syst. 19(5): 666-681 (2008) - [j48]Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen:
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distributed Syst. 19(7): 914-925 (2008) - [c125]Qiong Cai, José González, Ryan N. Rakvic, Grigorios Magklis, Pedro Chaparro, Antonio González:
Meeting points: using thread criticality to adapt multicore hardware to parallel regions. PACT 2008: 240-249 - [c124]Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González:
On-Line Failure Detection and Confinement in Caches. IOLTS 2008: 3-9 - [c123]Qiong Cai, Josep M. Codina, José González, Antonio González:
A software-hardware hybrid steering mechanism for clustered microarchitectures. IPDPS 2008: 1-12 - [c122]Fernando Latorre, José González, Antonio González:
Efficient resources assignment schemes for clustered multithreaded processors. IPDPS 2008: 1-12 - [c121]José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Ryan N. Rakvic, Antonio González:
Thread fusion. ISLPED 2008: 363-368 - [c120]Marc Lupon, Grigorios Magklis, Antonio González:
Version management alternatives for hardware transactional memory. MEDEA@PACT 2008: 69-76 - 2007
- [j47]Ronny Ronen, Antonio González:
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. IEEE Micro 27(1): 8-11 (2007) - [j46]Antonio González, Scott A. Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi:
Reliability: Fallacy or Reality? IEEE Micro 27(6): 36-45 (2007) - [j45]Pedro Chaparro, José González, Grigorios Magklis, Qiong Cai, Antonio González:
Understanding the Thermal Implications of Multi-Core Architectures. IEEE Trans. Parallel Distributed Syst. 18(8): 1055-1065 (2007) - [c119]Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González:
Early Register Release for Out-of-Order Processors with RegisterWindows. PACT 2007: 225-234 - [c118]Josep M. Codina, F. Jesús Sánchez, Antonio González:
Virtual Cluster Scheduling Through the Scheduling Graph. CGO 2007: 89-101 - [c117]Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Heterogeneous Clustered VLIW Microarchitectures. CGO 2007: 354-366 - [c116]Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González:
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. HPCA 2007: 75-84 - [c115]Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González:
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. IOLTS 2007: 15-22 - [c114]Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
Building a large instruction window through ROB compression. MEDEA@PACT 2007: 41-48 - [c113]Jaume Abella, Xavier Vera, Antonio González:
Penelope: The NBTI-Aware Processor. MICRO 2007: 85-96 - 2006
- [j44]Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González:
Exploiting Narrow Values for Soft Error Tolerance. IEEE Comput. Archit. Lett. 5(2) (2006) - [j43]Enric Gibert, F. Jesús Sánchez, Antonio González:
Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. Concurr. Comput. Pract. Exp. 18(11): 1391-1411 (2006) - [j42]Alex Settle, Dan Connors, Enric Gibert, Antonio González:
A dynamically reconfigurable cache for multithreaded processors. J. Embed. Comput. 2(2): 221-233 (2006) - [j41]Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin:
Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26(6): 30-39 (2006) - [j40]Juan L. Aragón, José M. González, Antonio González:
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. IEEE Trans. Computers 55(3): 281-291 (2006) - [c112]Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González:
Selective predicate prediction for out-of-order processors. ICS 2006: 46-54 - [c111]Matteo Monchiero, Ramon Canal, Antonio González:
Design space exploration for multicore architectures: a power/performance/thermal view. ICS 2006: 177-186 - [c110]Jaume Abella, Antonio González:
Heterogeneous way-size cache. ICS 2006: 239-248 - [c109]Jaume Abella, Antonio González:
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. IPDPS 2006 - [c108]Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González:
Empowering a helper cluster through data-width aware instruction selection policies. IPDPS 2006 - [c107]Grigorios Magklis, Pedro Chaparro, José González, Antonio González:
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. ISLPED 2006: 49-54 - 2005
- [j39]Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero:
Hardware support for early register release. Int. J. High Perform. Comput. Netw. 3(2/3): 83-94 (2005) - [j38]Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency. SIGARCH Comput. Archit. News 33(3): 49-56 (2005) - [j37]Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle:
IATAC: a smart predictor to turn-off L2 cache lines. ACM Trans. Archit. Code Optim. 2(1): 55-77 (2005) - [j36]Enric Gibert, F. Jesús Sánchez, Antonio González:
Distributed Data Cache Designs for Clustered VLIW Processors. IEEE Trans. Computers 54(10): 1227-1241 (2005) - [j35]Xavier Vera, Jaume Abella, Josep Llosa, Antonio González:
An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. 27(5): 946-987 (2005) - [j34]Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato:
On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. IEEE Trans. Parallel Distributed Syst. 16(2): 130-144 (2005) - [c106]Carlos Molina, Antonio González, Jordi Tubella:
Compiler analysis for trace-level speculative multithreaded architectures. Interaction between Compilers and Computer Architectures 2005: 2-10 - [c105]Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin:
Compiler Directed Early Register Release. IEEE PACT 2005: 110-122 - [c104]Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González:
Variable-Based Multi-module Data Caches for Clustered VLIW Processors. IEEE PACT 2005: 207-217 - [c103]Ramon Canal, Antonio González, James E. Smith:
Value Compression for Efficient Computation. Euro-Par 2005: 519-529 - [c102]Pedro Chaparro, Grigorios Magklis, José González, Antonio González:
Distributing the Frontend for Temperature Reduction. HPCA 2005: 61-70 - [c101]Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González:
Software Directed Issue Queue Power Reduction. HPCA 2005: 144-153 - [c100]Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González:
Memory Bank Predictors. ICCD 2005: 666-670 - [c99]Jaume Abella, Antonio González:
Inherently Workload-Balanced Clustered Microarchitecture. IPDPS 2005 - [c98]Alex Pajuelo, Antonio González, Mateo Valero:
Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS 2005 - [c97]Carlos Molina, Jordi Tubella, Antonio González:
Reducing Misspeculation Penalty in Trace-Level Speculative Multithreaded Architectures. ISHPC 2005: 43-55 - [c96]Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González:
The Mitosis Speculative Multithreaded Architectures. PARCO 2005: 27-40 - [c95]Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Demystifying on-the-fly spill code. PLDI 2005: 180-189 - [c94]Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen:
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. PLDI 2005: 269-279 - 2004
- [j33]Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. 1(2): 127-151 (2004) - [j32]Pedro Marcuello, Antonio González, Jordi Tubella:
Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism. IEEE Trans. Computers 53(2): 114-125 (2004) - [j31]Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero:
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004) - [j30]Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González:
A fast and accurate framework to analyze and optimize cache memory behavior. ACM Trans. Program. Lang. Syst. 26(2): 263-300 (2004) - [c93]Ramon Canal, Antonio González, James E. Smith:
Software-Controlled Operand-Gating. CGO 2004: 125-136 - [c92]Jaume Abella, Antonio González:
Low-Complexity Distributed Issue Queue. HPCA 2004: 73-83 - [c91]Pedro Chaparro, José González, Antonio González:
Thermal-Aware Clustered Microarchitectures. ICCD 2004: 48-53 - [c90]Grigorios Magklis, José González, Antonio González:
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. ICCD 2004: 250-255 - [c89]Fernando Latorre, José González, Antonio González:
Back-end assignment schemes for clustered multithreaded processors. ICS 2004: 316-325 - [c88]Alex Pajuelo, Antonio González, Mateo Valero:
Speculative execution for hiding memory latency. MEDEA@PACT 2004: 49-56 - [c87]José González, Fernando Latorre, Antonio González:
Cache organizations for clustered microarchitectures. WMPI 2004: 46-55 - 2003
- [j29]Jaume Abella, Ramon Canal, Antonio González:
Power- and Complexity-Aware Issue Queue Designs. IEEE Micro 23(5): 50-58 (2003) - [c86]Xavier Vera, Jaume Abella, Antonio González, Josep Llosa:
Optimizing Program Locality Through CMEs and GAs. IEEE PACT 2003: 68-78 - [c85]Enric Gibert, F. Jesús Sánchez, Antonio González:
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. CGO 2003: 193-203 - [c84]Carles Aliagas, Carlos Molina, Montse Garcia, Antonio González, Jordi Tubella:
Value Compression to Reduce Power in Data Caches. Euro-Par 2003: 616-622 - [c83]Jaume Abella, Antonio González:
Power-Aware Adaptive Issue Queue and Register File. HiPC 2003: 34-43 - [c82]Juan L. Aragón, José González, Antonio González:
Power-Aware Control Speculation through Selective Throttling. HPCA 2003: 103-112 - [c81]Jaume Abella, Antonio González:
Power Efficient Data Cache Designs. ICCD 2003: 8-13 - [c80]Jaume Abella, Antonio González:
On Reducing Register Pressure and Energy in Multiple-Banked Register Files. ICCD 2003: 14-20 - [c79]José González, Antonio González:
Dynamic Cluster Resizing. ICCD 2003: 375- - [c78]Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella:
Non redundant data cache. ISLPED 2003: 274-277 - [c77]Enric Gibert, F. Jesús Sánchez, Antonio González:
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. MICRO 2003: 315-325 - [c76]Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Instruction Replication for Clustered Microarchitectures. MICRO 2003: 326-338 - [c75]Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen:
A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24 - [e1]Utpal Banerjee, Kyle A. Gallivan, Antonio González:
Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003. ACM 2003, ISBN 1-58113-733-8 [contents] - 2002
- [j28]Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero:
Errata on "Measuring Experimental Error in Microprocessor Simulation". SIGARCH Comput. Archit. News 30(1): 2-4 (2002) - [j27]Luis Díaz de Cerio, Miguel Valero-García, Antonio González:
Hypercube Algorithms on Mesh Connected Multicomputers. IEEE Trans. Parallel Distributed Syst. 13(12): 1247-1260 (2002) - [c74]Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli:
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. IEEE PACT 2002: 281-290 - [c73]Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato:
Efficient Interconnects for Clustered Microarchitectures. IEEE PACT 2002: 291-300 - [c72]Pedro Marcuello, Antonio González:
Thread-Spawning Schemes for Speculative Multithreading. HPCA 2002: 55-64 - [c71]Carlos Molina, Antonio González, Jordi Tubella:
Trace-Level Speculative Multithreaded Architecture. ICCD 2002: 402-407 - [c70]Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero:
Hardware Schemes for Early Register Release. ICPP 2002: 5-13 - [c69]Jaume Abella, Antonio González, Josep Llosa, Xavier Vera:
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops 2002: 568-580 - [c68]Josep M. Codina, Josep Llosa, Antonio González:
A comparative study of modulo scheduling techniques. ICS 2002: 97-106 - [c67]Enric Gibert, F. Jesús Sánchez, Antonio González:
An interleaved cache clustered VLIW processor. ICS 2002: 210-219 - [c66]Juan L. Aragón, José González, Antonio González, James E. Smith:
Dual path instruction processing. ICS 2002: 220-229 - [c65]Alex Pajuelo, Antonio González, Mateo Valero:
Speculative Dynamic Vectorization. ISCA 2002: 271-280 - [c64]Xavier Vera, Josep Llosa, Antonio González:
Near-Optimal Padding for Removing Conflict Misses. LCPC 2002: 329-343 - [c63]Enric Gibert, F. Jesús Sánchez, Antonio González:
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. MICRO 2002: 123-133 - 2001
- [j26]Luis Díaz de Cerio, Miguel Valero-García, Antonio González, Dolors Royo:
CALMANT: Un Método Sistemático para la Ejecución de Algoritmos Hipercubo en Sistemas Multiprocesador. Computación y Sistemas 4(4): 289-297 (2001) - [j25]Luis Díaz de Cerio, Miguel Valero-García, Antonio González, Dolors Royo:
CALMANT: A Systematic Method for the Execution of Hypercube Algorithms in Multiprocessor Systems. Computación y Sistemas 4(4): 298-305 (2001) - [j24]Ramon Canal, Joan-Manuel Parcerisa, Antonio González:
Dynamic Code Partitioning for Clustered Architectures. Int. J. Parallel Program. 29(1): 59-79 (2001) - [j23]F. Jesús Sánchez, Antonio González:
Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . J. Instr. Level Parallelism 3 (2001) - [j22]Dolors Royo, Miguel Valero-García, Antonio González:
Implementing the one-sided Jacobi method on a 2D/3D mesh multicomputer. Parallel Comput. 27(9): 1253-1271 (2001) - [j21]Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt:
Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers 50(3): 234-249 (2001) - [j20]Joan-Manuel Parcerisa, Antonio González:
Improving Latency Tolerance of Multithreading through Decoupling. IEEE Trans. Computers 50(10): 1084-1094 (2001) - [j19]José González, Antonio González:
Control-Flow Speculation through Value Prediction. IEEE Trans. Computers 50(12): 1362-1376 (2001) - [c62]Josep M. Codina, F. Jesús Sánchez, Antonio González:
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. IEEE PACT 2001: 175-184 - [c61]Juan L. Aragón, José González, José M. García, Antonio González:
Confidence Estimation for Branch Prediction Reversal. HiPC 2001: 214-223 - [c60]Juan L. Aragón, José González, José M. García, Antonio González:
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. ICCD 2001: 228-233 - [c59]Ramon Canal, Antonio González:
Reducing the complexity of the issue logic. ICS 2001: 312-320 - [c58]Daniele Folegnani, Antonio González:
Energy-effective issue logic. ISCA 2001: 230-239 - [c57]Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González:
Graph-partitioning based instruction scheduling for clustered processors. MICRO 2001: 150-159 - 2000
- [j18]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000) - [j17]F. Jesús Sánchez, Antonio González:
Analyzing Data Locality in Numeric Applications. IEEE Micro 20(4): 58-66 (2000) - [j16]Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa:
Optimizing cache miss equations polyhedra. SIGARCH Comput. Archit. News 28(1): 43-52 (2000) - [c56]Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo:
A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). Euro-Par 2000: 194-198 - [c55]Luis Díaz de Cerio, Miguel Valero-García, Antonio González:
Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach (Research Note). Euro-Par 2000: 591-594 - [c54]Ramon Canal, Joan-Manuel Parcerisa, Antonio González:
Dynamic Cluster Assignment Mechanisms. HPCA 2000: 133-142 - [c53]F. Jesús Sánchez, Antonio González:
The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. ICPP 2000: 555-564 - [c52]Ramon Canal, Antonio González:
A low-complexity issue logic. ICS 2000: 327-335 - [c51]Pedro Marcuello, Antonio González:
A Quantitative Assessment of Thread-Level Speculation Techniques. IPDPS 2000: 595-601 - [c50]José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham:
Multiple-banked register file architectures. ISCA 2000: 316-325 - [c49]Nerina Bermudo, Xavier Vera, Antonio González, Josep Llosa:
An efficient solver for Cache Miss Equations. ISPASS 2000: 139-145 - [c48]F. Jesús Sánchez, Antonio González:
Instruction Scheduling for Clustered VLIW Architectures. ISSS 2000: 41-46 - [c47]F. Jesús Sánchez, Antonio González:
Modulo scheduling for a fully-distributed clustered VLIW architecture. MICRO 2000: 124-133 - [c46]Ramon Canal, Antonio González, James E. Smith:
Very low power pipelines using significance compression. MICRO 2000: 181-190 - [c45]Joan-Manuel Parcerisa, Antonio González:
Reducing wire delay penalty through value prediction. MICRO 2000: 317-326
1990 – 1999
- 1999
- [j15]F. Jesús Sánchez, Antonio González:
Software Data Prefetching for Software Pipelined Loops. J. Parallel Distributed Comput. 58(2): 236-259 (1999) - [j14]Nigel P. Topham, Antonio González:
Randomized Cache Placement for Eliminating Conflicts. IEEE Trans. Computers 48(2): 185-192 (1999) - [j13]Dolors Royo, Antonio González, Miguel Valero-García:
Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes. J. Supercomput. 14(2): 171-193 (1999) - [c44]José González, Antonio González:
Control-Flow Speculation through Value Prediction for Superscalar Processors. IEEE PACT 1999: 57-65 - [c43]Ramon Canal, Joan-Manuel Parcerisa, Antonio González:
A Cost-Effective Clustered Architecture. IEEE PACT 1999: 160-168 - [c42]Joan-Manuel Parcerisa, Antonio González:
The Synergy of Multithreading and Access/Execute Decoupling. HPCA 1999: 59-63 - [c41]Pedro Marcuello, Antonio González:
Exploiting Speculative Thread-Level Parallelism on a SMT Processor. HPCN Europe 1999: 754-763 - [c40]Carlos Molina, Antonio González, Jordi Tubella:
Reducing Memory Traffic Via Redundant Store Instructions. HPCN Europe 1999: 1246-1249 - [c39]Antonio González, Jordi Tubella, Carlos Molina:
Trace-Level Reuse. ICPP 1999: 30-39 - [c38]F. Jesús Sánchez, Antonio González:
A locality sensitive multi-module cache with explicit management. International Conference on Supercomputing 1999: 51-59 - [c37]Pedro Marcuello, Antonio González:
Clustered speculative multithreaded processors. International Conference on Supercomputing 1999: 365-372 - [c36]Carlos Molina, Antonio González, Jordi Tubella:
Dynamic removal of redundant computations. International Conference on Supercomputing 1999: 474-481 - [c35]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-192 - [c34]Pedro Marcuello, Jordi Tubella, Antonio González:
Value Prediction for Speculative Multithreaded Architectures. MICRO 1999: 230-236 - 1998
- [j12]José González, Antonio González:
Data value speculation in superscalar processors. Microprocess. Microsystems 22(6): 293-301 (1998) - [j11]Luis Díaz de Cerio, Miguel Valero-García, Antonio González:
A Method for Exploiting Communication/Computation Overlap in Hypercubes. Parallel Comput. 24(2): 221-245 (1998) - [j10]Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers 47(6): 625-638 (1998) - [c33]F. Jesús Sánchez, Antonio González:
Fast, Accurate and Flexible Data Locality Analysis. IEEE PACT 1998: 124-129 - [c32]Joan-Manuel Parcerisa, Antonio González:
The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. EUROMICRO 1998: 10293-10300 - [c31]Pedro Marcuello, Antonio González:
Data Speculative Multithreaded Architecture. EUROMICRO 1998: 10321-10324 - [c30]Miguel Valero-García, Antonio González, Luis Díaz de Cerio, Dolors Royo:
Divide-and-Conquer Algorithms on Two-Dimensional Meshes. Euro-Par 1998: 1051-1056 - [c29]F. Jesús Sánchez, Antonio González:
Software Prefetching for Software Pipelined Loops. HICSS (7) 1998: 778-779 - [c28]Jordi Tubella, Antonio González:
Control Speculation in Multithreaded Processors through Dynamic Loop Detection. HPCA 1998: 14-23 - [c27]Antonio González, José González, Mateo Valero:
Virtual-Physical Registers. HPCA 1998: 175-184 - [c26]José González, Antonio González:
The Potential of Data Value Speculation to Boost ILP. International Conference on Supercomputing 1998: 21-28 - [c25]Pedro Marcuello, Antonio González, Jordi Tubella:
Speculative Multithreaded Processors. International Conference on Supercomputing 1998: 77-84 - [c24]Dolors Royo, Antonio González, Miguel Valero-García:
Jacobi Orderings for Multi-Port Hypercubes. IPPS/SPDP 1998: 88-97 - [c23]Dolors Royo, Miguel Valero-García, Antonio González:
A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh. PDP 1998: 463-469 - [c22]José González, Antonio González:
Limits of Instruction Level Parallelism with Data Value Speculation. VECPAR 1998: 452-465 - 1997
- [c21]F. Jesús Sánchez, Antonio González, Mateo Valero:
Static Locality Analysis for Cache Management. IEEE PACT 1997: 261-271 - [c20]Dolors Royo, Miguel Valero-García, Antonio González, Carme Mari:
A Methodology for User-Oriented Scalability Analysis. ASAP 1997: 304-315 - [c19]José González, Antonio González:
Memory Address Prediction for Data Speculation. Euro-Par 1997: 1084-1091 - [c18]Antonio Martínez, Fracisco Fraile, Jordi J. Mallorquí, Leonardo Nogueira, Jordi Gabaldá, Antoni Broquetas, Antonio González:
PARSAR: Parallelisation of a Chirp Scaling Algorithm SAR Processor. Euro-Par 1997: 1346-1350 - [c17]Antonio González, Mateo Valero, José González, Teresa Monreal Arnal:
Virtual registers. HiPC 1997: 364-369 - [c16]Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa:
Eliminating Cache Conflict Misses through XOR-Based Placement Functions. International Conference on Supercomputing 1997: 76-83 - [c15]José González, Antonio González:
Speculative Execution via Address Prediction and Data Prefetching. International Conference on Supercomputing 1997: 196-203 - [c14]Nigel P. Topham, Antonio González, José González:
The Design and Performance of a Conflict-Avoiding Cache. MICRO 1997: 71-80 - [c13]F. Jesús Sánchez, Antonio González:
Cache Sensitive Modulo Scheduling. MICRO 1997: 338-348 - 1996
- [j9]Jordi Tubella, Antonio González, E. Elias:
The Multipath Architecture for Prolog Programs. Comput. J. 39(9): 780-792 (1996) - [j8]Luis Díaz de Cerio, Antonio González, Miguel Valero-García:
Communication Pipelining in Hypercubes. Parallel Process. Lett. 6(4): 507-523 (1996) - [c12]Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero:
Swing module scheduling: a lifetime-sensitive approach. IEEE PACT 1996: 80-86 - [c11]Luis Díaz de Cerio, Miguel Valero-García, Antonio González:
Overlapping Communication and Computation in Hypercubes. Euro-Par, Vol. I 1996: 253-257 - 1995
- [j7]Antonio González, Miguel Valero-García, Luis Díaz de Cerio:
Executing Algorithms with Hypercube Topology on Torus Multicomputers. IEEE Trans. Parallel Distributed Syst. 6(8): 803-814 (1995) - [c10]Antonio González, Carlos Aliagas, Mateo Valero:
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. International Conference on Supercomputing 1995: 338-347 - [c9]Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Hypernode reduction modulo scheduling. MICRO 1995: 350-360 - [c8]Enric Fontdecaba, Antonio González, Jesús Labarta:
Load Balancing in a Network Flow Optimization Code. PARA 1995: 214-222 - [c7]Jordi Tubella, Antonio González:
Exploiting path parallelism in logic programming. PDP 1995: 164-173 - 1994
- [j6]Antonio González:
Design and Evaluation of an Instruction Cache for Reducing the Cost of Branches. Perform. Evaluation 20(1-3): 83-96 (1994) - [c6]Jordi Tubella, Antonio González:
Combining depth-first and breadth-first search in Prolog execution. GULP-PRODE (2) 1994: 452-453 - [c5]Jordi Tubella, Antonio González:
A Partial Breadth-First Execution Model for Prolog. ICTAI 1994: 129-137 - [c4]Antonio González, Jordi Tubella:
The Multipath Parallel Execution Model for Prolog. PASCO 1994: 164-173 - [c3]Antonio González:
Parallel Numerical Algorithms. PDP 1994: 238-239 - 1993
- [j5]Antonio González:
A survey of branch techniques in pipelined processors. Microprocess. Microprogramming 36(5): 243-257 (1993) - [j4]Mateo Valero, Jordi Cortadella, Antonio González:
Chairmen's introduction. Microprocess. Microprogramming 38(1-5) (1993) - [j3]Jordi Tubella, Antonio González:
MEM: A new execution model for Prolog. Microprocess. Microprogramming 39(2-5): 83-86 (1993) - [j2]Antonio González, José M. Llabería:
Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers 42(3): 363-371 (1993) - [c2]Antonio González, Miguel Valero-García:
The Xor embedding: An embedding of hypercubes onto rings and toruses. ASAP 1993: 15-28
1980 – 1989
- 1989
- [c1]Antonio González, José M. Llabería:
Instruction fetch unit for parallel execution of branch instructions. ICS 1989: 417-426 - 1988
- [j1]Antonio González, José María Llabería, Jordi Cortadella:
A mechanism for reducing the cost of branches in RISC architectures. Microprocess. Microprogramming 24(1-5): 565-572 (1988)
Coauthor Index
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