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ORCIDBibTeX records: Chia-Fu Lee
@inproceedings{DBLP:conf/isscc/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24,
author = {Hidehiro Fujiwara and
Haruki Mori and
Wei{-}Chang Zhao and
Kinshuk Khare and
Cheng{-}En Lee and
Xiaochen Peng and
Vineet Joshi and
Chao{-}Kai Chuang and
Shu{-}Huan Hsu and
Takeshi Hashizume and
Toshiaki Naganuma and
Chen{-}Hung Tien and
Yao{-}Yi Liu and
Yen{-}Chien Lai and
Chia{-}Fu Lee and
Tan{-}Li Chou and
Kerem Akarvardar and
Saman Adham and
Yih Wang and
Yu{-}Der Chih and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {34.4 {A} 3nm, 32.5TOPS/W, 55.0TOPS/mm\({}^{\mbox{2}}\) and 3.78Mb/mm\({}^{\mbox{2}}\)
Fully-Digital Compute-in-Memory Macro Supporting {INT12} {\texttimes}
{INT12} with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {572--574},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454556},
doi = {10.1109/ISSCC49657.2024.10454556},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MoriZLLHCHTLWACFWCCLC23,
author = {Haruki Mori and
Wei{-}Chang Zhao and
Cheng{-}En Lee and
Chia{-}Fu Lee and
Yu{-}Hao Hsu and
Chao{-}Kai Chuang and
Takeshi Hashizume and
Hao{-}Chun Tung and
Yao{-}Yi Liu and
Shin{-}Rung Wu and
Kerem Akarvardar and
Tan{-}Li Chou and
Hidehiro Fujiwara and
Yih Wang and
Yu{-}Der Chih and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {A 4nm 6163-TOPS/W/b {\textdollar}{\textbackslash}mathbf\{4790-TOPS/mm{\^{}}\{2\}/b\}{\textdollar}
{SRAM} Based Digital-Computing-in-Memory Macro Supporting Bit-Width
Flexibility and Simultaneous {MAC} and Weight Update},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {132--133},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067555},
doi = {10.1109/ISSCC42615.2023.10067555},
timestamp = {Wed, 29 Mar 2023 15:53:39 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MoriZLLHCHTLWACFWCCLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeLSLCLCLCKCWWWCWCC23,
author = {Po{-}Hao Lee and
Chia{-}Fu Lee and
Yi{-}Chun Shih and
Hon{-}Jarn Lin and
Yen{-}An Chang and
Cheng{-}Han Lu and
Yu{-}Lin Chen and
Chieh{-}Pu Lo and
Chung{-}Chieh Chen and
Cheng{-}Hsiung Kuo and
Tan{-}Li Chou and
Chia{-}Yu Wang and
J. J. Wu and
Roger Wang and
Harry Chuang and
Yih Wang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {A 16nm 32Mb Embedded {STT-MRAM} with a 6ns Read-Access Time, a 1M-Cycle
Write Endurance, 20-Year Retention at 150{\textdegree}C and {MTJ-OTP}
Solutions for Magnetic Immunity},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {494--495},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067837},
doi = {10.1109/ISSCC42615.2023.10067837},
timestamp = {Wed, 29 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LeeLSLCLCLCKCWWWCWCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraMZCNCHS22,
author = {Hidehiro Fujiwara and
Haruki Mori and
Wei{-}Chang Zhao and
Mei{-}Chen Chuang and
Rawan Naous and
Chao{-}Kai Chuang and
Takeshi Hashizume and
Dar Sun and
Chia{-}Fu Lee and
Kerem Akarvardar and
Saman Adham and
Tan{-}Li Chou and
Mahmut Ersin Sinangil and
Yih Wang and
Yu{-}Der Chih and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {A 5-nm 254-TOPS/W 221-TOPS/mm\({}^{\mbox{2}}\) Fully-Digital Computing-in-Memory
Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and
Simultaneous {MAC} and Write Operations},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731754},
doi = {10.1109/ISSCC42614.2022.9731754},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraMZCNCHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/LeeLLMFSCCC22,
author = {Chia{-}Fu Lee and
Cheng{-}Han Lu and
Cheng{-}En Lee and
Haruki Mori and
Hidehiro Fujiwara and
Yi{-}Chun Shih and
Tan{-}Li Chou and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based
Compute-in-Memory with Configurable Bit-width For {AI} Edge Applications},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {24--25},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830438},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830438},
timestamp = {Thu, 04 Aug 2022 10:53:40 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/LeeLLMFSCCC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChihLFSLNCLLMZS21,
author = {Yu{-}Der Chih and
Po{-}Hao Lee and
Hidehiro Fujiwara and
Yi{-}Chun Shih and
Chia{-}Fu Lee and
Rawan Naous and
Yu{-}Lin Chen and
Chieh{-}Pu Lo and
Cheng{-}Han Lu and
Haruki Mori and
Wei{-}Cheng Zhao and
Dar Sun and
Mahmut E. Sinangil and
Yen{-}Huei Chen and
Tan{-}Li Chou and
Kerem Akarvardar and
Hung{-}Jen Liao and
Yih Wang and
Meng{-}Fan Chang and
Tsung{-}Yung Jonathan Chang},
title = {An 89TOPS/W and 16.3TOPS/mm\({}^{\mbox{2}}\) All-Digital SRAM-Based
Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning
Edge Applications},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {252--254},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365766},
doi = {10.1109/ISSCC42613.2021.9365766},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChihLFSLNCLLMZS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChihSLCLLCLSSCC20,
author = {Yu{-}Der Chih and
Yi{-}Chun Shih and
Chia{-}Fu Lee and
Yen{-}An Chang and
Po{-}Hao Lee and
Hon{-}Jarn Lin and
Yu{-}Lin Chen and
Chieh{-}Pu Lo and
Meng{-}Chun Shih and
Kuei{-}Hung Shen and
Harry Chuang and
Tsung{-}Yung Jonathan Chang},
title = {13.3 {A} 22nm 32Mb Embedded {STT-MRAM} with 10ns Read Speed, 1M Cycle
Write Endurance, 10 Years Retention at 150{\textdegree}C and High
Immunity to Magnetic Field Interference},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {222--224},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062955},
doi = {10.1109/ISSCC19947.2020.9062955},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChihSLCLLCLSSCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ShihLCLLCLYYCCC19,
author = {Yi{-}Chun Shih and
Chia{-}Fu Lee and
Yen{-}An Chang and
Po{-}Hao Lee and
Hon{-}Jarn Lin and
Yu{-}Lin Chen and
Ku{-}Feng Lin and
Ta{-}Ching Yeh and
Hung{-}Chang Yu and
Harry Chuang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM
With Hybrid-Resistance Reference, Sub- {\textdollar}{\textbackslash}mu{\textdollar}
{A} Sensing Resolution, and 17.5-nS Read Access Time},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {4},
pages = {1029--1038},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2889106},
doi = {10.1109/JSSC.2018.2889106},
timestamp = {Wed, 07 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ShihLCLLCLYYCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GallagherCCHSWB19,
author = {William J. Gallagher and
Eric Chien and
Tien{-}Wei Chiang and
Jian{-}Cheng Huang and
Meng{-}Chun Shih and
C. Y. Wang and
Christine Bair and
George Lee and
Yi{-}Chun Shih and
Chia{-}Fu Lee and
Roger Wang and
Kuei{-}Hung Shen and
J. J. Wu and
Wayne Wang and
Harry Chuang},
title = {Recent Progress and Next Directions for Embedded {MRAM} Technology},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {190},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777932},
doi = {10.23919/VLSIC.2019.8777932},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GallagherCCHSWB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShihLCLLCLYYCCC18,
author = {Yi{-}Chun Shih and
Chia{-}Fu Lee and
Yen{-}An Chang and
Po{-}Hao Lee and
Hon{-}Jarn Lin and
Yu{-}Lin Chen and
Ku{-}Feng Lin and
Ta{-}Ching Yeh and
Hung{-}Chang Yu and
Harry Chuang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with
Hybrid-Resistance Reference, Sub-{\(\mu\)}A Sensing Resolution, and
17.5NS Read Access Time},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {79--80},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502260},
doi = {10.1109/VLSIC.2018.8502260},
timestamp = {Wed, 07 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cm/KuLLHWCP17,
author = {Yu{-}Jen Ku and
Dian{-}Yu Lin and
Chia{-}Fu Lee and
Ping{-}Jung Hsieh and
Hung{-}Yu Wei and
Chun{-}Ting Chou and
Ai{-}Chun Pang},
title = {5G Radio Access Network Design with the Fog Paradigm: Confluence of
Communications and Computing},
journal = {{IEEE} Commun. Mag.},
volume = {55},
number = {4},
pages = {46--52},
year = {2017},
url = {https://doi.org/10.1109/MCOM.2017.1600893},
doi = {10.1109/MCOM.2017.1600893},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cm/KuLLHWCP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LeeLLCC17,
author = {Chia{-}Fu Lee and
Hon{-}Jarn Lin and
Chiu{-}Wang Lien and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {A 1.4Mb 40-nm embedded ReRAM macro with 0.07um\({}^{\mbox{2}}\) bit
cell, 2.7mA/100MHz low-power read and hybrid write verify for high
endurance application},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
Korea (South), November 6-8, 2017},
pages = {9--12},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASSCC.2017.8240203},
doi = {10.1109/ASSCC.2017.8240203},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/LeeLLCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasc/HoCCL16,
author = {Chih{-}Wei Ho and
Chun{-}Ting Chou and
Yu{-}Chun Chien and
Chia{-}Fu Lee},
title = {Unsupervised Anomaly Detection Using Light Switches for Smart Nursing
Homes},
booktitle = {2016 {IEEE} 14th Intl Conf on Dependable, Autonomic and Secure Computing,
14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf
on Big Data Intelligence and Computing and Cyber Science and Technology
Congress, DASC/PiCom/DataCom/CyberSciTech 2016, Auckland, New Zealand,
August 8-12, 2016},
pages = {803--810},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/DASC-PICom-DataCom-CyberSciTec.2016.139},
doi = {10.1109/DASC-PICOM-DATACOM-CYBERSCITEC.2016.139},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasc/HoCCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChoWHWLLLFYLWCN13,
author = {Caleb Y.{-}S. Cho and
J. C. Wang and
Lion Huang and
Milo Weng and
Yu{-}Fan Lin and
Chia{-}Fu Lee and
C. W. Lien and
H. C. Feng and
Tassa Yang and
S. P. Liao and
J. J. Wu and
Yu{-}Der Chih and
Sreedhar Natarajan},
title = {A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power,
wide voltage supply range 2M-bit split-gate embedded Flash},
booktitle = {2013 International Symposium on {VLSI} Design, Automation, and Test,
{VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLDI-DAT.2013.6533877},
doi = {10.1109/VLDI-DAT.2013.6533877},
timestamp = {Mon, 25 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChoWHWLLLFYLWCN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LaiL07,
author = {Fang{-}Shi Lai and
Chia{-}Fu Lee},
title = {On-Chip Voltage Down Converter to Improve {SRAM} Read/Write Margin
and Static Power for Sub-Nano {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {9},
pages = {2061--2070},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2007.903072},
doi = {10.1109/JSSC.2007.903072},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LaiL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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