BibTeX records: Ian Zhuang

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@inproceedings{DBLP:conf/isscc/ChenZZIMNRSFC18,
  author    = {Stanley Chen and
               Lei Zhou and
               Ian Zhuang and
               Jay Im and
               Didem Turkur Melek and
               Jinyung Namkoong and
               Mayank Raj and
               Jaewook Shin and
               Yohan Frans and
               Ken Chang},
  title     = {A 4-to-16GHz inverter-based injection-locked quadrature clock generator
               with phase interpolators for multi-standard I/Os in 7nm FinFET},
  booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2018, San Francisco, CA, USA, February 11-15, 2018},
  pages     = {390--392},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/ISSCC.2018.8310348},
  doi       = {10.1109/ISSCC.2018.8310348},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/ChenZZIMNRSFC18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ImCFCZZCMLCZTBT18,
  author    = {Jay Im and
               Stanley Chen and
               Dave Freitas and
               Adam Chou and
               Lei Zhou and
               Ian Zhuang and
               Tim Cronin and
               David Mahashin and
               Winson Lin and
               Kok Lim Chan and
               Hongyuan Zhao and
               Kee Hian Tan and
               Ade Bekele and
               Didem Turker and
               Parag Upadhyaya and
               Yohan Frans and
               Ken Chang},
  title     = {A 0.5-28GB/S Wireline Tranceiver with 15-Tap {DFE} and Fast-Locking
               Digital {CDR} in 7NM FinFET},
  booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
               18-22, 2018},
  pages     = {145--146},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/VLSIC.2018.8502275},
  doi       = {10.1109/VLSIC.2018.8502275},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/ImCFCZZCMLCZTBT18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ImFRCCCCGMZZHLU17,
  author    = {Jay Im and
               Dave Freitas and
               Arianne Roldan and
               Ronan Casey and
               Stanley Chen and
               Adam Chou and
               Tim Cronin and
               Kevin Geary and
               Scott McLeod and
               Lei Zhou and
               Ian Zhuang and
               Jaeduk Han and
               Sen Lin and
               Parag Upadhyaya and
               Geoff Zhang and
               Yohan Frans and
               Ken Chang},
  title     = {A 40-to-56 Gb/s {PAM-4} Receiver With Ten-Tap Direct Decision-Feedback
               Equalization in 16-nm FinFET},
  journal   = {J. Solid-State Circuits},
  volume    = {52},
  number    = {12},
  pages     = {3486--3502},
  year      = {2017},
  url       = {https://doi.org/10.1109/JSSC.2017.2749432},
  doi       = {10.1109/JSSC.2017.2749432},
  timestamp = {Thu, 14 Dec 2017 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/jssc/ImFRCCCCGMZZHLU17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ImFRCCCCGMZZHLU17,
  author    = {Jay Im and
               Dave Freitas and
               Arianne Roldan and
               Ronan Casey and
               Stanley Chen and
               Adam Chou and
               Tim Cronin and
               Kevin Geary and
               Scott McLeod and
               Lei Zhou and
               Ian Zhuang and
               Jaeduk Han and
               Sen Lin and
               Parag Upadhyaya and
               Geoff Zhang and
               Yohan Frans and
               Ken Chang},
  title     = {6.3 {A} 40-to-56Gb/s {PAM-4} receiver with 10-tap direct decision-feedback
               equalization in 16nm FinFET},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {114--115},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870287},
  doi       = {10.1109/ISSCC.2017.7870287},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/ImFRCCCCGMZZHLU17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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