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ORCIDBibTeX records: Qiang Zhou 0001
@article{DBLP:journals/tcad/ZhaiBZCZY23,
author = {Jianwang Zhai and
Chen Bai and
Binwu Zhu and
Yici Cai and
Qiang Zhou and
Bei Yu},
title = {McPAT-Calib: {A} {RISC-V} {BOOM} Microarchitecture Power Modeling
Framework},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {1},
pages = {243--256},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3169464},
doi = {10.1109/TCAD.2022.3169464},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhaiBZCZY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Wang0C23,
author = {Haoyi Wang and
Qiang Zhou and
Yici Cai},
editor = {Atsushi Takahashi},
title = {Static Probability Analysis Guided {RTL} Hardware Trojan Test Generation},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {510--515},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567921},
doi = {10.1145/3566097.3567921},
timestamp = {Mon, 26 Jun 2023 20:46:40 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/Wang0C23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HaoCZ22,
author = {Rui Hao and
Yici Cai and
Qiang Zhou},
title = {Intelligent and kernelized placement: {A} survey},
journal = {Integr.},
volume = {86},
pages = {44--50},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.002},
doi = {10.1016/J.VLSI.2022.05.002},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HaoCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiCZ22,
author = {Lin Li and
Yici Cai and
Qiang Zhou},
title = {A survey on machine learning-based routing for {VLSI} physical design},
journal = {Integr.},
volume = {86},
pages = {51--56},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.05.003},
doi = {10.1016/J.VLSI.2022.05.003},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/LiCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cis/LuoGHZ22,
author = {Shiling Luo and
Wenchao Gao and
Le Huang and
Qiang Zhou},
title = {A circuit protection method based on minterm perturbation},
booktitle = {18th International Conference on Computational Intelligence and Security,
{CIS} 2022, Chengdu, China, December 16-18, 2022},
pages = {360--365},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CIS58238.2022.00082},
doi = {10.1109/CIS58238.2022.00082},
timestamp = {Sat, 22 Apr 2023 16:25:52 +0200},
biburl = {https://dblp.org/rec/conf/cis/LuoGHZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpr/0005C022,
author = {Wenyan Wu and
Yici Cai and
Qiang Zhou},
title = {TransMarker: {A} Pure Vision Transformer for Facial Landmark Detection},
booktitle = {26th International Conference on Pattern Recognition, {ICPR} 2022,
Montreal, QC, Canada, August 21-25, 2022},
pages = {3580--3587},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICPR56361.2022.9956248},
doi = {10.1109/ICPR56361.2022.9956248},
timestamp = {Thu, 01 Dec 2022 13:56:03 +0100},
biburl = {https://dblp.org/rec/conf/icpr/0005C022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2205-14328,
author = {Qiang Zhou and
Chaohui Yu and
Zhibin Wang and
Hao Li},
title = {Point {RCNN:} An Angle-Free Framework for Rotated Object Detection},
journal = {CoRR},
volume = {abs/2205.14328},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2205.14328},
doi = {10.48550/ARXIV.2205.14328},
eprinttype = {arXiv},
eprint = {2205.14328},
timestamp = {Thu, 02 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2205-14328.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2209-03063,
author = {Qiang Zhou and
Chaohui Yu and
Hao Luo and
Zhibin Wang and
Hao Li},
title = {MimCo: Masked Image Modeling Pre-training with Contrastive Teacher},
journal = {CoRR},
volume = {abs/2209.03063},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2209.03063},
doi = {10.48550/ARXIV.2209.03063},
eprinttype = {arXiv},
eprint = {2209.03063},
timestamp = {Tue, 05 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2209-03063.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ccfthpc/WangCZ21,
author = {Haoyi Wang and
Yici Cai and
Qiang Zhou},
title = {A game theory approach for {RTL} security verification resources allocation},
journal = {{CCF} Trans. High Perform. Comput.},
volume = {3},
number = {1},
pages = {57--69},
year = {2021},
url = {https://doi.org/10.1007/s42514-020-00054-5},
doi = {10.1007/S42514-020-00054-5},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ccfthpc/WangCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/WangCZ21,
author = {Jing Wang and
Yici Cai and
Qiang Zhou},
title = {Temperature-Aware Electromigration Analysis with Current-Tracking
in Power Grid Networks},
journal = {J. Comput. Sci. Technol.},
volume = {36},
number = {5},
pages = {1133--1144},
year = {2021},
url = {https://doi.org/10.1007/s11390-021-0909-8},
doi = {10.1007/S11390-021-0909-8},
timestamp = {Wed, 10 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/WangCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/ZhaiCZ21,
author = {Jianwang Zhai and
Yici Cai and
Qiang Zhou},
title = {Placement and Routing Methods Considering Shape Constraints of {JTL}
for {RSFQ} Circuits},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {68},
number = {5},
pages = {1571--1575},
year = {2021},
url = {https://doi.org/10.1109/TCSII.2021.3067136},
doi = {10.1109/TCSII.2021.3067136},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/ZhaiCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cvpr/0001YWQL21,
author = {Qiang Zhou and
Chaohui Yu and
Zhibin Wang and
Qi Qian and
Hao Li},
title = {Instant-Teaching: An End-to-End Semi-Supervised Object Detection Framework},
booktitle = {{IEEE} Conference on Computer Vision and Pattern Recognition, {CVPR}
2021, virtual, June 19-25, 2021},
pages = {4081--4090},
publisher = {Computer Vision Foundation / {IEEE}},
year = {2021},
url = {https://openaccess.thecvf.com/content/CVPR2021/html/Zhou\_Instant-Teaching\_An\_End-to-End\_Semi-Supervised\_Object\_Detection\_Framework\_CVPR\_2021\_paper.html},
doi = {10.1109/CVPR46437.2021.00407},
timestamp = {Mon, 18 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cvpr/0001YWQL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fgr/WuCZ21,
author = {Wenyan Wu and
Yici Cai and
Qiang Zhou},
title = {{SRL:} Separation-and-Recombination Learning for Video Facial Landmark
Detection with Limited Data},
booktitle = {16th {IEEE} International Conference on Automatic Face and Gesture
Recognition, {FG} 2021, Jodhpur, India, December 15-18, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FG52635.2021.9667064},
doi = {10.1109/FG52635.2021.9667064},
timestamp = {Wed, 11 Jan 2023 13:24:19 +0100},
biburl = {https://dblp.org/rec/conf/fgr/WuCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhaiBZC0021,
author = {Jianwang Zhai and
Chen Bai and
Binwu Zhu and
Yici Cai and
Qiang Zhou and
Bei Yu},
title = {McPAT-Calib: {A} Microarchitecture Power Modeling Framework for Modern
CPUs},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643508},
doi = {10.1109/ICCAD51958.2021.9643508},
timestamp = {Tue, 28 Dec 2021 12:29:05 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhaiBZC0021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icws/ZhouCWXZ21,
author = {Qiang Zhou and
Wei Chen and
Weiqing Wang and
Jiajie Xu and
Lei Zhao},
editor = {Carl K. Chang and
Ernesto Daminai and
Jing Fan and
Parisa Ghodous and
Michael Maximilien and
Zhongjie Wang and
Robert Ward and
Jia Zhang},
title = {Multiple Features Driven Author Name Disambiguation},
booktitle = {2021 {IEEE} International Conference on Web Services, {ICWS} 2021,
Chicago, IL, USA, September 5-10, 2021},
pages = {506--515},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICWS53863.2021.00071},
doi = {10.1109/ICWS53863.2021.00071},
timestamp = {Fri, 23 Jun 2023 11:36:46 +0200},
biburl = {https://dblp.org/rec/conf/icws/ZhouCWXZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiCZ21,
author = {Lin Li and
Yici Cai and
Qiang Zhou},
title = {An Efficient Approach for {DRC} Hotspot Prediction with Convolutional
Neural Network},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401274},
doi = {10.1109/ISCAS51556.2021.9401274},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCZ21,
author = {Jing Wang and
Yici Cai and
Qiang Zhou},
title = {A Power Grids Electromigration Analysis with Via Array Using Current-Tracing
Model},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401432},
doi = {10.1109/ISCAS51556.2021.9401432},
timestamp = {Thu, 11 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2101-11782,
author = {Qiang Zhou and
Chaohui Yu and
Chunhua Shen and
Zhibin Wang and
Hao Li},
title = {Object Detection Made Simpler by Eliminating Heuristic {NMS}},
journal = {CoRR},
volume = {abs/2101.11782},
year = {2021},
url = {https://arxiv.org/abs/2101.11782},
eprinttype = {arXiv},
eprint = {2101.11782},
timestamp = {Thu, 16 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2101-11782.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2103-11402,
author = {Qiang Zhou and
Chaohui Yu and
Zhibin Wang and
Qi Qian and
Hao Li},
title = {Instant-Teaching: An End-to-End Semi-Supervised Object Detection Framework},
journal = {CoRR},
volume = {abs/2103.11402},
year = {2021},
url = {https://arxiv.org/abs/2103.11402},
eprinttype = {arXiv},
eprint = {2103.11402},
timestamp = {Mon, 17 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2103-11402.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cvpr/YangZW00ZL20,
author = {Zhuoqian Yang and
Wentao Zhu and
Wayne Wu and
Chen Qian and
Qiang Zhou and
Bolei Zhou and
Chen Change Loy},
title = {TransMoMo: Invariance-Driven Unsupervised Video Motion Retargeting},
booktitle = {2020 {IEEE/CVF} Conference on Computer Vision and Pattern Recognition,
{CVPR} 2020, Seattle, WA, USA, June 13-19, 2020},
pages = {5305--5314},
publisher = {Computer Vision Foundation / {IEEE}},
year = {2020},
url = {https://openaccess.thecvf.com/content\_CVPR\_2020/html/Yang\_TransMoMo\_Invariance-Driven\_Unsupervised\_Video\_Motion\_Retargeting\_CVPR\_2020\_paper.html},
doi = {10.1109/CVPR42600.2020.00535},
timestamp = {Tue, 31 Aug 2021 14:00:04 +0200},
biburl = {https://dblp.org/rec/conf/cvpr/YangZW00ZL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2003-14401,
author = {Zhuoqian Yang and
Wentao Zhu and
Wayne Wu and
Chen Qian and
Qiang Zhou and
Bolei Zhou and
Chen Change Loy},
title = {TransMoMo: Invariance-Driven Unsupervised Video Motion Retargeting},
journal = {CoRR},
volume = {abs/2003.14401},
year = {2020},
url = {https://arxiv.org/abs/2003.14401},
eprinttype = {arXiv},
eprint = {2003.14401},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2003-14401.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cg/WuWCZ19,
author = {Wenyan Wu and
Xingzhe Wu and
Yici Cai and
Qiang Zhou},
title = {Deep coupling neural network for robust facial landmark detection},
journal = {Comput. Graph.},
volume = {82},
pages = {286--294},
year = {2019},
url = {https://doi.org/10.1016/j.cag.2019.05.031},
doi = {10.1016/J.CAG.2019.05.031},
timestamp = {Wed, 19 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cg/WuWCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangZCQ19,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Parallelizing SAT-based de-camouflaging attacks by circuit partitioning
and conflict avoiding},
journal = {Integr.},
volume = {67},
pages = {108--120},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.10.009},
doi = {10.1016/J.VLSI.2018.10.009},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangZCQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangWCZ19,
author = {Haoyi Wang and
Chenguang Wang and
Yici Cai and
Qiang Zhou},
title = {A high-level information flow tracking method for detecting information
leakage},
journal = {Integr.},
volume = {69},
pages = {393--399},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2019.08.001},
doi = {10.1016/J.VLSI.2019.08.001},
timestamp = {Thu, 06 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/WangWCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangWZWLCZ19,
author = {Jianlei Yang and
Xueyan Wang and
Qiang Zhou and
Zhaohao Wang and
Hai Li and
Yiran Chen and
Weisheng Zhao},
title = {Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit
Obfuscation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {1},
pages = {57--69},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2802870},
doi = {10.1109/TCAD.2018.2802870},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangWZWLCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Wang0CQ19,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Toward a Formal and Quantitative Evaluation Framework for Circuit
Obfuscation Methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1844--1857},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2864220},
doi = {10.1109/TCAD.2018.2864220},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Wang0CQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccv/SunWLYW0Y019,
author = {Keqiang Sun and
Wayne Wu and
Tinghao Liu and
Shuo Yang and
Quan Wang and
Qiang Zhou and
Zuochang Ye and
Chen Qian},
title = {{FAB:} {A} Robust Facial Landmark Detection Framework for Motion-Blurred
Videos},
booktitle = {2019 {IEEE/CVF} International Conference on Computer Vision, {ICCV}
2019, Seoul, Korea (South), October 27 - November 2, 2019},
pages = {5461--5470},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICCV.2019.00556},
doi = {10.1109/ICCV.2019.00556},
timestamp = {Fri, 18 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccv/SunWLYW0Y019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCY019,
author = {Jing Wang and
Yici Cai and
Ming Yan and
Qiang Zhou},
title = {Composite Optimization for Electromigration Reliability and Noise
in Power Grid Networks},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702122},
doi = {10.1109/ISCAS.2019.8702122},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangCY019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1910-12100,
author = {Keqiang Sun and
Wayne Wu and
Tinghao Liu and
Shuo Yang and
Quan Wang and
Qiang Zhou and
Zuochang Ye and
Chen Qian},
title = {{FAB:} {A} Robust Facial Landmark Detection Framework for Motion-Blurred
Videos},
journal = {CoRR},
volume = {abs/1910.12100},
year = {2019},
url = {http://arxiv.org/abs/1910.12100},
eprinttype = {arXiv},
eprint = {1910.12100},
timestamp = {Fri, 18 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1910-12100.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/WangZCQ18,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Spear and Shield: Evolution of Integrated Circuit Camouflaging},
journal = {J. Comput. Sci. Technol.},
volume = {33},
number = {1},
pages = {42--57},
year = {2018},
url = {https://doi.org/10.1007/s11390-018-1807-6},
doi = {10.1007/S11390-018-1807-6},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/WangZCQ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/JiangXWZ18,
author = {Shan Jiang and
Ning Xu and
Xueyan Wang and
Qiang Zhou},
title = {An Efficient Technique to Reverse Engineer Minterm Protection Based
Camouflaged Circuit},
journal = {J. Comput. Sci. Technol.},
volume = {33},
number = {5},
pages = {998--1006},
year = {2018},
url = {https://doi.org/10.1007/s11390-018-1870-z},
doi = {10.1007/S11390-018-1870-Z},
timestamp = {Tue, 02 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcst/JiangXWZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiaCZY18,
author = {Xiaotao Jia and
Yici Cai and
Qiang Zhou and
Bei Yu},
title = {A Multicommodity Flow-Based Detailed Router With Efficient Acceleration
Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {217--230},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693270},
doi = {10.1109/TCAD.2017.2693270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiaCZY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangCZW18,
author = {Chenguang Wang and
Yici Cai and
Qiang Zhou and
Haoyi Wang},
editor = {Youngsoo Shin},
title = {{ASAX:} Automatic security assertion extraction for detecting Hardware
Trojans},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {84--89},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297287},
doi = {10.1109/ASPDAC.2018.8297287},
timestamp = {Thu, 06 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WangCZW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangZCQ18,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
editor = {Youngsoo Shin},
title = {A conflict-free approach for parallelizing SAT-based de-camouflaging
attacks},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {259--264},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297315},
doi = {10.1109/ASPDAC.2018.8297315},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/WangZCQ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangC018,
author = {Chenguang Wang and
Yici Cai and
Qiang Zhou},
editor = {Youngsoo Shin},
title = {{HLIFT:} {A} high-level information flow tracking method for detecting
hardware Trojans},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {727--732},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297408},
doi = {10.1109/ASPDAC.2018.8297408},
timestamp = {Thu, 06 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WangC018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cvpr/Wu0YWC018,
author = {Wayne Wu and
Chen Qian and
Shuo Yang and
Quan Wang and
Yici Cai and
Qiang Zhou},
title = {Look at Boundary: {A} Boundary-Aware Face Alignment Algorithm},
booktitle = {2018 {IEEE} Conference on Computer Vision and Pattern Recognition,
{CVPR} 2018, Salt Lake City, UT, USA, June 18-22, 2018},
pages = {2129--2138},
publisher = {Computer Vision Foundation / {IEEE} Computer Society},
year = {2018},
url = {http://openaccess.thecvf.com/content\_cvpr\_2018/html/Wu\_Look\_at\_Boundary\_CVPR\_2018\_paper.html},
doi = {10.1109/CVPR.2018.00227},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cvpr/Wu0YWC018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/JiaWCZ18,
author = {Xiaotao Jia and
Jing Wang and
Yici Cai and
Qiang Zhou},
editor = {Deming Chen and
Houman Homayoun and
Baris Taskin},
title = {Electromigration Design Rule aware Global and Detailed Routing Algorithm},
booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI, {GLSVLSI}
2018, Chicago, IL, USA, May 23-25, 2018},
pages = {267--272},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3194554.3194567},
doi = {10.1145/3194554.3194567},
timestamp = {Wed, 10 Mar 2021 14:55:38 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/JiaWCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WangCWZ18,
author = {Chenguang Wang and
Yici Cai and
Haoyi Wang and
Qiang Zhou},
editor = {Iris Bahar},
title = {Electromagnetic equalizer: an active countermeasure against {EM} side-channel
attack},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {112},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240804},
doi = {10.1145/3240765.3240804},
timestamp = {Thu, 06 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/WangCWZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccnc/WeiZC18,
author = {Jia Wei and
Qiang Zhou and
Yici Cai},
title = {Poet-based Poetry Generation: Controlling Personal Style with Recurrent
Neural Networks},
booktitle = {2018 International Conference on Computing, Networking and Communications,
{ICNC} 2018, Maui, HI, USA, March 5-8, 2018},
pages = {156--160},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ICCNC.2018.8390270},
doi = {10.1109/ICCNC.2018.8390270},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccnc/WeiZC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1802-02789,
author = {Jianlei Yang and
Xueyan Wang and
Qiang Zhou and
Zhaohao Wang and
Hai Li and
Yiran Chen and
Weisheng Zhao},
title = {Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit
Obfuscation},
journal = {CoRR},
volume = {abs/1802.02789},
year = {2018},
url = {http://arxiv.org/abs/1802.02789},
eprinttype = {arXiv},
eprint = {1802.02789},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1802-02789.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1805-10483,
author = {Wayne Wu and
Chen Qian and
Shuo Yang and
Quan Wang and
Yici Cai and
Qiang Zhou},
title = {Look at Boundary: {A} Boundary-Aware Face Alignment Algorithm},
journal = {CoRR},
volume = {abs/1805.10483},
year = {2018},
url = {http://arxiv.org/abs/1805.10483},
eprinttype = {arXiv},
eprint = {1805.10483},
timestamp = {Fri, 18 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1805-10483.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WangZCQ17,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {An Empirical Study on Gate Camouflaging Methods Against Circuit Partition
Attack},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {345--350},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060493},
doi = {10.1145/3060403.3060493},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WangZCQ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/WangYCZY17,
author = {Chenguang Wang and
Ming Yan and
Yici Cai and
Qiang Zhou and
Jianlei Yang},
title = {Power Profile Equalizer: {A} Lightweight Countermeasure against Side-Channel
Attack},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {305--312},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.54},
doi = {10.1109/ICCD.2017.54},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/WangYCZY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/WangCZ17,
author = {Chenguang Wang and
Yici Cai and
Qiang Zhou},
title = {Automatic Security Property Generation for Detecting Information-Leaking
Hardware Trojans},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {321--328},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.56},
doi = {10.1109/ICCD.2017.56},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/WangCZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCZ17,
author = {Xueyan Wang and
Yici Cai and
Qiang Zhou},
title = {Cell spreading optimization for force-directed global placers},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050572},
doi = {10.1109/ISCAS.2017.8050572},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangCZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/PangZZGQT17,
author = {Zihan Pang and
Jiliang Zhang and
Qiang Zhou and
Shuqian Gong and
Xu Qian and
Bin Tang},
title = {Crossover Ring Oscillator {PUF}},
booktitle = {18th International Symposium on Quality Electronic Design, {ISQED}
2017, Santa Clara, CA, USA, March 14-15, 2017},
pages = {237--243},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISQED.2017.7918322},
doi = {10.1109/ISQED.2017.7918322},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/PangZZGQT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YanCWZ17,
author = {Ming Yan and
Yici Cai and
Chenguang Wang and
Qiang Zhou},
title = {An Effective Power Grid Optimization Approach for the Electromigration
Reliability},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {453--458},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.85},
doi = {10.1109/ISVLSI.2017.85},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YanCWZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/ZhangWDLZXSW16,
author = {Jiliang Zhang and
Qiang Wu and
Yipeng Ding and
Yong{-}Qiang Lv and
Qiang Zhou and
Zhihua Xia and
Xingming Sun and
Xing{-}Wei Wang},
title = {Techniques for Design and Implementation of an FPGA-Specific Physical
Unclonable Function},
journal = {J. Comput. Sci. Technol.},
volume = {31},
number = {1},
pages = {124--136},
year = {2016},
url = {https://doi.org/10.1007/s11390-016-1616-8},
doi = {10.1007/S11390-016-1616-8},
timestamp = {Thu, 08 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/ZhangWDLZXSW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/JiaCZY16,
author = {Xiaotao Jia and
Yici Cai and
Qiang Zhou and
Bei Yu},
editor = {Ayse K. Coskun and
Martin Margala and
Laleh Behjat and
Jie Han},
title = {MCFRoute 2.0: {A} Redundant Via Insertion Enhanced Concurrent Detailed
Router},
booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI,
{GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016},
pages = {87--92},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2902961.2902966},
doi = {10.1145/2902961.2902966},
timestamp = {Wed, 10 Mar 2021 14:55:38 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/JiaCZY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WangJZCYGQ16,
author = {Xueyan Wang and
Xiaotao Jia and
Qiang Zhou and
Yici Cai and
Jianlei Yang and
Mingze Gao and
Gang Qu},
editor = {Ayse K. Coskun and
Martin Margala and
Laleh Behjat and
Jie Han},
title = {Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers},
booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI,
{GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016},
pages = {133--136},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2902961.2903000},
doi = {10.1145/2902961.2903000},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WangJZCYGQ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenCZQ16,
author = {Zhuwei Chen and
Yici Cai and
Qiang Zhou and
Gang Qu},
title = {An efficient framework for configurable {RO} {PUF}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {742--745},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7527347},
doi = {10.1109/ISCAS.2016.7527347},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ChenCZQ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangZCQ16,
author = {Xueyan Wang and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Is the Secure {IC} camouflaging really secure?},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {1710--1713},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7538897},
doi = {10.1109/ISCAS.2016.7538897},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangZCQ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YaoYCZS15,
author = {Hailong Yao and
Fan Yang and
Yici Cai and
Qiang Zhou and
Chiu{-}Wing Sham},
title = {{SIAR:} Customized real-time interactive router for analog circuits},
journal = {Integr.},
volume = {48},
pages = {170--182},
year = {2015},
url = {https://doi.org/10.1016/j.vlsi.2014.03.001},
doi = {10.1016/J.VLSI.2014.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YaoYCZS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/DengCZ15,
author = {Chao Deng and
Yici Cai and
Qiang Zhou},
title = {Register Clustering Methodology for Low Power Clock Tree Synthesis},
journal = {J. Comput. Sci. Technol.},
volume = {30},
number = {2},
pages = {391--403},
year = {2015},
url = {https://doi.org/10.1007/s11390-015-1531-4},
doi = {10.1007/S11390-015-1531-4},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/DengCZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/QiCZ15,
author = {Zhongdong Qi and
Yici Cai and
Qiang Zhou},
title = {Design-Rule-Aware Congestion Model with Explicit Modeling of Vias
and Local Pin Access Paths},
journal = {J. Comput. Sci. Technol.},
volume = {30},
number = {3},
pages = {614--628},
year = {2015},
url = {https://doi.org/10.1007/s11390-015-1515-4},
doi = {10.1007/S11390-015-1515-4},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/QiCZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaiDZYNS15,
author = {Yici Cai and
Chao Deng and
Qiang Zhou and
Hailong Yao and
Feifei Niu and
Cliff N. Sze},
title = {Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient
Buffer Insertion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {1},
pages = {142--155},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2300174},
doi = {10.1109/TVLSI.2014.2300174},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CaiDZYNS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangCZZ15,
author = {Jianlei Yang and
Yici Cai and
Qiang Zhou and
Wei Zhao},
title = {A Selected Inversion Approach for Locality Driven Vectorless Power
Grid Verification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {11},
pages = {2617--2628},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2365520},
doi = {10.1109/TVLSI.2014.2365520},
timestamp = {Sun, 05 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangCZZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/GaoLZQCZ15,
author = {Mingze Gao and
Khai Lai and
Jiliang Zhang and
Gang Qu and
Aijiao Cui and
Qiang Zhou},
title = {Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators},
booktitle = {14th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2015, Xi'an, China, August 26-28, 2015},
pages = {194--201},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CADGRAPHICS.2015.54},
doi = {10.1109/CADGRAPHICS.2015.54},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/GaoLZQCZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/DengCZ15,
author = {Chao Deng and
Yici Cai and
Qiang Zhou},
title = {Fast synthesis of low power clock trees based on register clustering},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {303--309},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085444},
doi = {10.1109/ISQED.2015.7085444},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/DengCZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/ZhangQLZ14,
author = {Jiliang Zhang and
Gang Qu and
Yong{-}Qiang Lv and
Qiang Zhou},
title = {A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs},
journal = {J. Comput. Sci. Technol.},
volume = {29},
number = {4},
pages = {664--678},
year = {2014},
url = {https://doi.org/10.1007/s11390-014-1458-1},
doi = {10.1007/S11390-014-1458-1},
timestamp = {Thu, 08 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/ZhangQLZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/LvZCQ14,
author = {Yong{-}Qiang Lv and
Qiang Zhou and
Yici Cai and
Gang Qu},
title = {Trusted Integrated Circuits: The Problem and Challenges},
journal = {J. Comput. Sci. Technol.},
volume = {29},
number = {5},
pages = {918--928},
year = {2014},
url = {https://doi.org/10.1007/s11390-014-1479-9},
doi = {10.1007/S11390-014-1479-9},
timestamp = {Thu, 08 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/LvZCQ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/YaoGCZS14,
author = {Hailong Yao and
Qiang Gao and
Yici Cai and
Qiang Zhou and
Chiu{-}Wing Sham},
title = {Length matching in detailed routing for analog and mixed signal circuits},
journal = {Microelectron. J.},
volume = {45},
number = {6},
pages = {604--612},
year = {2014},
url = {https://doi.org/10.1016/j.mejo.2014.04.007},
doi = {10.1016/J.MEJO.2014.04.007},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/YaoGCZS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangCZS14,
author = {Jianlei Yang and
Yici Cai and
Qiang Zhou and
Jin Shi},
title = {Friendly Fast Poisson Solver Preconditioning Technique for Power Grid
Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {4},
pages = {899--912},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2252375},
doi = {10.1109/TVLSI.2013.2252375},
timestamp = {Sun, 05 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangCZS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangLCZ14,
author = {Jianlei Yang and
Zuowei Li and
Yici Cai and
Qiang Zhou},
title = {PowerRush: An Efficient Simulator for Static Power Grid Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {10},
pages = {2103--2116},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2282418},
doi = {10.1109/TVLSI.2013.2282418},
timestamp = {Sun, 05 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangLCZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/QiCZLC14,
author = {Zhongdong Qi and
Yici Cai and
Qiang Zhou and
Zhuoyuan Li and
Mike Chen},
title = {{VFGR:} {A} very fast parallel global router with accurate congestion
modeling},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {525--530},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742945},
doi = {10.1109/ASPDAC.2014.6742945},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/QiCZLC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YangWCZ14,
author = {Jianlei Yang and
Chenguang Wang and
Yici Cai and
Qiang Zhou},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {Power supply noise aware evaluation framework for side channel attacks
and countermeasures},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {161--166},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082770},
doi = {10.1109/FPT.2014.7082770},
timestamp = {Thu, 06 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YangWCZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JiaCZCLL14,
author = {Xiaotao Jia and
Yici Cai and
Qiang Zhou and
Gang Chen and
Zhuoyuan Li and
Zuowei Li},
editor = {Yao{-}Wen Chang},
title = {MCFRoute: a detailed router based on multi-commodity flow method},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {397--404},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001382},
doi = {10.1109/ICCAD.2014.7001382},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/JiaCZCLL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/QiCZ14,
author = {Zhongdong Qi and
Yici Cai and
Qiang Zhou},
title = {Accurate prediction of detailed routing congestion using supervised
data learning},
booktitle = {32nd {IEEE} International Conference on Computer Design, {ICCD} 2014,
Seoul, South Korea, October 19-22, 2014},
pages = {97--103},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ICCD.2014.6974668},
doi = {10.1109/ICCD.2014.6974668},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/QiCZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DengCZ14,
author = {Chao Deng and
Yici Cai and
Qiang Zhou},
title = {A register clustering algorithm for low power clock tree synthesis},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {389--392},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865147},
doi = {10.1109/ISCAS.2014.6865147},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DengCZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/QiMZC14,
author = {Ziyang Qi and
Kun Ma and
Qiang Zhou and
Yici Cai},
title = {{RSMT} construction algorithm based on Congestion-Oriented Flexibility},
booktitle = {{IEEE} 5th Latin American Symposium on Circuits and Systems, {LASCAS}
2014, Santiago, Chile, February 25-28, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/LASCAS.2014.6820275},
doi = {10.1109/LASCAS.2014.6820275},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/lascas/QiMZC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiMZCXH13,
author = {Zuowei Li and
Yuchun Ma and
Qiang Zhou and
Yici Cai and
Yuan Xie and
Tingting Huang},
title = {Thermal-aware {P/G} {TSV} planning for {IR} drop reduction in 3D ICs},
journal = {Integr.},
volume = {46},
number = {1},
pages = {1--9},
year = {2013},
url = {https://doi.org/10.1016/j.vlsi.2012.05.002},
doi = {10.1016/J.VLSI.2012.05.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiMZCXH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ChenYCZ13,
author = {Weijie Chen and
Hailong Yao and
Yici Cai and
Qiang Zhou},
title = {Analog routing considering min-area constraint},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6811904},
doi = {10.1109/ASICON.2013.6811904},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/ChenYCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ZhaoYCZ13,
author = {Jinming Zhao and
Hailong Yao and
Yici Cai and
Qiang Zhou},
title = {A new splitting graph construction algorithm for {SIAR} router},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6811918},
doi = {10.1109/ASICON.2013.6811918},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ZhaoYCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/QiCZ13,
author = {Zhongdong Qi and
Yici Cai and
Qiang Zhou},
title = {Bridging the Gap between Global Routing and Detailed Routing: {A}
Practical Congestion Model},
booktitle = {2013 International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2013, Guangzhou, China, November 16-18, 2013},
pages = {74--80},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CADGraphics.2013.17},
doi = {10.1109/CADGRAPHICS.2013.17},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/QiCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/ZhangWLZCLQ13,
author = {Jiliang Zhang and
Qiang Wu and
Yongqiang Lyu and
Qiang Zhou and
Yici Cai and
Yaping Lin and
Gang Qu},
title = {Design and Implementation of a Delay-Based {PUF} for {FPGA} {IP} Protection},
booktitle = {2013 International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2013, Guangzhou, China, November 16-18, 2013},
pages = {107--114},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CADGraphics.2013.22},
doi = {10.1109/CADGRAPHICS.2013.22},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/ZhangWLZCLQ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YinQZ13,
author = {Chi{-}En Daniel Yin and
Gang Qu and
Qiang Zhou},
editor = {Enrico Macii},
title = {Design and implementation of a group-based {RO} {PUF}},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {416--421},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.094},
doi = {10.7873/DATE.2013.094},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/YinQZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ZhangLLCCZB13,
author = {Jiliang Zhang and
Yaping Lin and
Yongqiang Lu and
Ray C. C. Cheung and
Wenjie Che and
Qiang Zhou and
Jinian Bian},
title = {Binding Hardware IPs to Specific {FPGA} Device via Inter-twining the
{PUF} Response with the {FSM} of Sequential Circuits},
booktitle = {21st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2013, Seattle, WA, USA, April 28-30, 2013},
pages = {227},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/FCCM.2013.12},
doi = {10.1109/FCCM.2013.12},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/ZhangLLCCZB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZhangLLQCCZB13,
author = {Jiliang Zhang and
Yaping Lin and
Yongqiang Lyu and
Gang Qu and
Ray C. C. Cheung and
Wenjie Che and
Qiang Zhou and
Jinian Bian},
title = {{FPGA} {IP} protection by binding Finite State Machine to Physical
Unclonable Function},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645555},
doi = {10.1109/FPL.2013.6645555},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/ZhangLLQCCZB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/YangCZZ13,
author = {Jianlei Yang and
Yici Cai and
Qiang Zhou and
Wei Zhao},
title = {Selected inversion for vectorless power grid verification by exploiting
locality},
booktitle = {2013 {IEEE} 31st International Conference on Computer Design, {ICCD}
2013, Asheville, NC, USA, October 6-9, 2013},
pages = {257--263},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ICCD.2013.6657051},
doi = {10.1109/ICCD.2013.6657051},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/YangCZZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/ZhangLZWLZ12,
author = {Jiliang Zhang and
Yongqiang Lu and
Qiang Zhou and
Qiang Wu and
Yaping Lin and
Kang Zhao},
title = {TimFastPlace: Critical-path based timing driven FastPlace},
journal = {{IEICE} Electron. Express},
volume = {9},
number = {16},
pages = {1310--1315},
year = {2012},
url = {https://doi.org/10.1587/elex.9.1310},
doi = {10.1587/ELEX.9.1310},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/ZhangLZWLZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiMZCWHX12,
author = {Zuowei Li and
Yuchun Ma and
Qiang Zhou and
Yici Cai and
Yu Wang and
Tingting Huang and
Yuan Xie},
title = {Thermal-aware power network design for {IR} drop reduction in 3D ICs},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {47--52},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164995},
doi = {10.1109/ASPDAC.2012.6164995},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiMZCWHX12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangLCZ12,
author = {Jianlei Yang and
Zuowei Li and
Yici Cai and
Qiang Zhou},
editor = {Alan J. Hu},
title = {PowerRush : Efficient transient simulation for power grid analysis},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {653--659},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429526},
doi = {10.1145/2429384.2429526},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YangLCZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GaoZQC12,
author = {Wenchao Gao and
Qiang Zhou and
Xu Qian and
Yici Cai},
editor = {Keith A. Bowman and
Kamesh V. Gadepally and
Pallab Chatterjee and
Mark M. Budnik and
Lalitha Immaneni},
title = {A DyadicCluster method used for nonlinear placement},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
2012, Santa Clara, CA, USA, March 19-21, 2012},
pages = {418--423},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISQED.2012.6187527},
doi = {10.1109/ISQED.2012.6187527},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/GaoZQC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouSLC11,
author = {Qiang Zhou and
Jin Shi and
Bin Liu and
Yici Cai},
title = {Floorplanning Considering {IR} Drop in Multiple Supply Voltages Island
Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {4},
pages = {638--646},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2037428},
doi = {10.1109/TVLSI.2009.2037428},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouSLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiuLZ11,
author = {Liu Liu and
Yongqiang Lu and
Qiang Zhou},
title = {A timing-perspective study on the wire model in placement},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {910--913},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157353},
doi = {10.1109/ASICON.2011.6157353},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/LiuLZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscwd/ZhuBZC11,
author = {Limin Zhu and
Jinian Bian and
Qiang Zhou and
Yici Cai},
editor = {Weiming Shen and
Jean{-}Paul A. Barth{\`{e}}s and
Junzhou Luo and
Peter G. Kropf and
Michel Pouly and
Jianming Yong and
Yunjiao Xue and
Milton Pires Ramos},
title = {A fast recursive detailed routing algorithm for hierarchical FPGAs},
booktitle = {Proceedings of the 2011 15th International Conference on Computer
Supported Cooperative Work in Design, {CSCWD} 2011, June 8-10, 2011,
Lausanne, Switzerland},
pages = {91--96},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CSCWD.2011.5960060},
doi = {10.1109/CSCWD.2011.5960060},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/cscwd/ZhuBZC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NiuZYCYS11,
author = {Feifei Niu and
Qiang Zhou and
Hailong Yao and
Yici Cai and
Jianlei Yang and
Chin Ngai Sze},
editor = {David Atienza and
Yuan Xie and
Jos{\'{e}} L. Ayala and
Ken S. Stevens},
title = {Obstacle-avoiding and slew-constrained buffered clock tree synthesis
for skew optimization},
booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
Lausanne, Switzerland, May 2-6, 2011},
pages = {199--204},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1973009.1973049},
doi = {10.1145/1973009.1973049},
timestamp = {Sun, 05 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/NiuZYCYS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YangYZC11,
author = {Fan Yang and
Hailong Yao and
Qiang Zhou and
Yici Cai},
editor = {David Atienza and
Yuan Xie and
Jos{\'{e}} L. Ayala and
Ken S. Stevens},
title = {{SIAR:} splitting-graph-based interactive analog router},
booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
Lausanne, Switzerland, May 2-6, 2011},
pages = {367--370},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1973009.1973084},
doi = {10.1145/1973009.1973084},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/YangYZC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangLCZ11,
author = {Jianlei Yang and
Zuowei Li and
Yici Cai and
Qiang Zhou},
editor = {Joel R. Phillips and
Alan J. Hu and
Helmut Graeb},
title = {PowerRush: {A} linear simulator for power grid},
booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2011, San Jose, California, USA, November 7-10, 2011},
pages = {482--487},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCAD.2011.6105372},
doi = {10.1109/ICCAD.2011.6105372},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YangLCZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangCZS11,
author = {Jianlei Yang and
Yici Cai and
Qiang Zhou and
Jin Shi},
editor = {Joel R. Phillips and
Alan J. Hu and
Helmut Graeb},
title = {Fast poisson solver preconditioned method for robust power grid analysis},
booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2011, San Jose, California, USA, November 7-10, 2011},
pages = {531--536},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCAD.2011.6105381},
doi = {10.1109/ICCAD.2011.6105381},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YangCZS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GaoYZC11,
author = {Qiang Gao and
Hailong Yao and
Qiang Zhou and
Yici Cai},
title = {A novel detailed routing algorithm with exact matching constraint
for analog and mixed signal circuits},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {36--41},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770700},
doi = {10.1109/ISQED.2011.5770700},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/GaoYZC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/QiZJCLY11,
author = {Zhongdong Qi and
Qiang Zhou and
Yanming Jia and
Yici Cai and
Zhuoyuan Li and
Hailong Yao},
title = {A novel fine-grain track routing approach for routability and crosstalk
optimization},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {621--626},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770793},
doi = {10.1109/ISQED.2011.5770793},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/QiZJCLY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ZhouYZC11,
author = {Shuzhe Zhou and
Hailong Yao and
Qiang Zhou and
Yici Cai},
title = {Minimization of Circuit Delay and Power through Gate Sizing and Threshold
Voltage Assignment},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
July 2011, Chennai, India},
pages = {212--217},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISVLSI.2011.29},
doi = {10.1109/ISVLSI.2011.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ZhouYZC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/MaZZH10,
author = {Yuchun Ma and
Qiang Zhou and
Pingqiang Zhou and
Xianlong Hong},
title = {Thermal Impacts of Leakage Power in 2D/3D floorplanning},
journal = {J. Circuits Syst. Comput.},
volume = {19},
number = {7},
pages = {1483--1495},
year = {2010},
url = {https://doi.org/10.1142/S0218126610006773},
doi = {10.1142/S0218126610006773},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/MaZZH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/DaiZB10,
author = {Hui Dai and
Qiang Zhou and
Jinian Bian},
title = {Multilevel Optimization for Large-Scale Hierarchical {FPGA} Placement},
journal = {J. Comput. Sci. Technol.},
volume = {25},
number = {5},
pages = {1083--1091},
year = {2010},
url = {https://doi.org/10.1007/s11390-010-9389-y},
doi = {10.1007/S11390-010-9389-Y},
timestamp = {Thu, 01 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/DaiZB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenZCH10,
author = {Yin Shen and
Qiang Zhou and
Yici Cai and
Xianlong Hong},
title = {{ECP-} and CMP-Aware Detailed Routing Algorithm for {DFM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {1},
pages = {153--157},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2008.2008020},
doi = {10.1109/TVLSI.2008.2008020},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenZCH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscwd/ZhuZCB10,
author = {Limin Zhu and
Qiang Zhou and
Yici Cai and
Jinian Bian},
editor = {Weiming Shen and
Ning Gu and
Tun Lu and
Jean{-}Paul A. Barth{\`{e}}s and
Junzhou Luo},
title = {An architecture-aware routing optimization via satisfiabilty for hierarchical
{FPGA}},
booktitle = {Proceedings of the 2010 14th International Conference on Computer
Supported Cooperative Work in Design, {CSCWD} 2010, April 14-16, 2010,
Fudan University, Shanghai, China},
pages = {701--706},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CSCWD.2010.5471886},
doi = {10.1109/CSCWD.2010.5471886},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/cscwd/ZhuZCB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YuZQB10,
author = {Junbo Yu and
Qiang Zhou and
Gang Qu and
Jinian Bian},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Behavioral level dual-vth design for reduced leakage power with thermal
awareness},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1261--1266},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457000},
doi = {10.1109/DATE.2010.5457000},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/YuZQB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YangCZH10,
author = {Fan Yang and
Yici Cai and
Qiang Zhou and
Jiang Hu},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {{SAT} based multi-net rip-up-and-reroute for manufacturing hotspot
removal},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1369--1372},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457024},
doi = {10.1109/DATE.2010.5457024},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/YangCZH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GuQYZ10,
author = {Junjun Gu and
Gang Qu and
Lin Yuan and
Qiang Zhou},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Peak current reduction by simultaneous state replication and re-encoding},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {592--595},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654204},
doi = {10.1109/ICCAD.2010.5654204},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/GuQYZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ShenCCLZH10,
author = {Weixiang Shen and
Yici Cai and
Wei Chen and
Yongqiang Lu and
Qiang Zhou and
Jiang Hu},
title = {Useful clock skew optimization under a multi-corner multi-mode design
framework},
booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED}
2010), 22-24 March 2010, San Jose, CA, {USA}},
pages = {62--68},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISQED.2010.5450402},
doi = {10.1109/ISQED.2010.5450402},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ShenCCLZH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiuZLB10,
author = {Dawei Liu and
Qiang Zhou and
Yongqiang Lu and
Jinian Bian},
title = {A low power clock network placement framework},
booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED}
2010), 22-24 March 2010, San Jose, CA, {USA}},
pages = {771--776},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISQED.2010.5450494},
doi = {10.1109/ISQED.2010.5450494},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/LiuZLB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpt/2010,
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
publisher = {{IEEE}},
year = {2010},
isbn = {978-1-4244-8981-7},
timestamp = {Thu, 01 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YuZQB09,
author = {Junbo Yu and
Qiang Zhou and
Gang Qu and
Jinian Bian},
title = {Peak Temperature Reduction by Physical Information Driven Behavioral
Synthesis with Resource Usage Allocation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {92-A},
number = {12},
pages = {3151--3159},
year = {2009},
url = {https://doi.org/10.1587/transfun.E92.A.3151},
doi = {10.1587/TRANSFUN.E92.A.3151},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/YuZQB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/YanZH09,
author = {Haixia Yan and
Qiang Zhou and
Xianlong Hong},
title = {Thermal aware placement in 3D ICs using quadratic uniformity modeling
approach},
journal = {Integr.},
volume = {42},
number = {2},
pages = {175--180},
year = {2009},
url = {https://doi.org/10.1016/j.vlsi.2008.06.001},
doi = {10.1016/J.VLSI.2008.06.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/YanZH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhouZCH09,
author = {Qiang Zhou and
Xin Zhao and
Yici Cai and
Xianlong Hong},
title = {An {MTCMOS} technology for low-power physical design},
journal = {Integr.},
volume = {42},
number = {3},
pages = {340--345},
year = {2009},
url = {https://doi.org/10.1016/j.vlsi.2008.09.004},
doi = {10.1016/J.VLSI.2008.09.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhouZCH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YuZB09,
author = {Junbo Yu and
Qiang Zhou and
Jinian Bian},
editor = {Kazutoshi Wakabayashi},
title = {Peak temperature control in thermal-aware behavioral synthesis through
allocating the number of resources},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {85--90},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796446},
doi = {10.1109/ASPDAC.2009.4796446},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YuZB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/DaiZCBH09,
author = {Hui Dai and
Qiang Zhou and
Yici Cai and
Jinian Bian and
Xianlong Hong},
title = {Fast placement for large-scale hierarchical FPGAs},
booktitle = {11th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2009, Huangshan, China, August 19-21, 2009},
pages = {190--194},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/CADCG.2009.5246907},
doi = {10.1109/CADCG.2009.5246907},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/cadgraphics/DaiZCBH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/LiuZBJ09,
author = {Dawei Liu and
Qiang Zhou and
Jinian Bian and
Yanming Jia},
title = {Global density smoothing technique for analytical placement algorithm},
booktitle = {11th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2009, Huangshan, China, August 19-21, 2009},
pages = {389--393},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/CADCG.2009.5246870},
doi = {10.1109/CADCG.2009.5246870},
timestamp = {Thu, 01 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/LiuZBJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/HuangZCY09,
author = {Yun Huang and
Qiang Zhou and
Yici Cai and
Haixia Yan},
title = {A thermal-driven force-directed floorplanning algorithm for 3D ICs},
booktitle = {11th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2009, Huangshan, China, August 19-21, 2009},
pages = {497--502},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/CADCG.2009.5246852},
doi = {10.1109/CADCG.2009.5246852},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/HuangZCY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GuQZ09,
author = {Junjun Gu and
Gang Qu and
Qiang Zhou},
title = {Information hiding for trusted system design},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {698--701},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1630093},
doi = {10.1145/1629911.1630093},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GuQZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/ZhaoZC09,
author = {Jinpeng Zhao and
Qiang Zhou and
Yici Cai},
title = {Fast congestion-aware timing-driven placement for island {FPGA}},
booktitle = {Proceedings of the 2009 {IEEE} Symposium on Design and Diagnostics
of Electronic Circuits and Systems, {DDECS} 2009, April 15-17, 2009,
Liberec, Czech Republic},
pages = {24--27},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DDECS.2009.5012092},
doi = {10.1109/DDECS.2009.5012092},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/ZhaoZC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/ChenWJZ09,
author = {Juanjuan Chen and
Xing Wei and
Yunjian Jiang and
Qiang Zhou},
title = {Improve clock gating through power-optimal enable function selection},
booktitle = {Proceedings of the 2009 {IEEE} Symposium on Design and Diagnostics
of Electronic Circuits and Systems, {DDECS} 2009, April 15-17, 2009,
Liberec, Czech Republic},
pages = {30--33},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DDECS.2009.5012094},
doi = {10.1109/DDECS.2009.5012094},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/ChenWJZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WangCZTE09,
author = {Xiaoyi Wang and
Yici Cai and
Qiang Zhou and
Sheldon X.{-}D. Tan and
Thom Jefferson A. Eguia},
editor = {Jaijeet S. Roychowdhury},
title = {Decoupling capacitance efficient placement for reducing transient
power supply noise},
booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009,
San Jose, CA, USA, November 2-5, 2009},
pages = {745--751},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1687399.1687538},
doi = {10.1145/1687399.1687538},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/WangCZTE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/DaweiZBCH09,
author = {Dawei Liu and
Qiang Zhou and
Jinian Bian and
Yici Cai and
Xianlong Hong},
title = {Cell shifting aware of wirelength and overlap},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {506--510},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810346},
doi = {10.1109/ISQED.2009.4810346},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/DaweiZBCH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/CaiZHSW08,
author = {Yici Cai and
Qiang Zhou and
Xianlong Hong and
Rui Shi and
Yang Wang},
title = {Application of optical proximity correction technology},
journal = {Sci. China Ser. {F} Inf. Sci.},
volume = {51},
number = {2},
pages = {213--224},
year = {2008},
url = {https://doi.org/10.1007/s11432-008-0006-4},
doi = {10.1007/S11432-008-0006-4},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/CaiZHSW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/GuoCZH08,
author = {Liangpeng Guo and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {Logic and Layout Aware Level Converter Optimization for Multiple Supply
Voltage},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {91-A},
number = {8},
pages = {2084--2090},
year = {2008},
url = {https://doi.org/10.1093/ietfec/e91-a.8.2084},
doi = {10.1093/IETFEC/E91-A.8.2084},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/GuoCZH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/DongZCH08,
author = {Changdao Dong and
Qiang Zhou and
Yici Cai and
Xianlong Hong},
title = {Wire density driven top-down global placement for {CMP} variation
control},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {1676--1679},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746360},
doi = {10.1109/APCCAS.2008.4746360},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/DongZCH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangZCHHB08,
author = {Yanfeng Wang and
Qiang Zhou and
Yici Cai and
Jiang Hu and
Xianlong Hong and
Jinian Bian},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Low power clock buffer planning methodology in {F-D} placement for
large scale circuit design},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {370--375},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483977},
doi = {10.1109/ASPDAC.2008.4483977},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WangZCHHB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/WeiCZCBH08,
author = {Xing Wei and
Juanjuan Chen and
Qiang Zhou and
Yici Cai and
Jinian Bian and
Xianlong Hong},
title = {MacroMap: {A} technology mapping algorithm for heterogeneous FPGAs
with effective area estimation},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {559--562},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4630008},
doi = {10.1109/FPL.2008.4630008},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/WeiCZCBH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GuoCZKH08,
author = {Liangpeng Guo and
Yici Cai and
Qiang Zhou and
Le Kang and
Xianlong Hong},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {A novel performance driven power gating based on distributed sleep
transistor network},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {255--260},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366173},
doi = {10.1145/1366110.1366173},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GuoCZKH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/YanZH08,
author = {Haixia Yan and
Qiang Zhou and
Xianlong Hong},
title = {Efficient Thermal Aware Placement Approach Integrated with 3D {DCT}
Placement Algorithm},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {289--292},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479741},
doi = {10.1109/ISQED.2008.4479741},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/YanZH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ShenCZH08,
author = {Yin Shen and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {{DFM} Based Detailed Routing Algorithm for {ECP} and {CMP}},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {357--360},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479756},
doi = {10.1109/ISQED.2008.4479756},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ShenCZH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/CaiLZH07,
author = {Yici Cai and
Bin Liu and
Qiang Zhou and
Xianlong Hong},
title = {Voltage Island Generation in Cell Based Dual-Vdd Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {90-A},
number = {1},
pages = {267--273},
year = {2007},
url = {https://doi.org/10.1093/ietfec/e90-a.1.267},
doi = {10.1093/IETFEC/E90-A.1.267},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/CaiLZH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LuHZCG07,
author = {Yongqiang Lu and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Jun Gu},
title = {An efficient quadratic placement based on search space traversing
technology},
journal = {Integr.},
volume = {40},
number = {3},
pages = {253--260},
year = {2007},
url = {https://doi.org/10.1016/j.vlsi.2005.10.002},
doi = {10.1016/J.VLSI.2005.10.002},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LuHZCG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/ZhouCLH07,
author = {Qiang Zhou and
Yici Cai and
Duo Li and
Xianlong Hong},
title = {A Yield-Driven Gridless Router},
journal = {J. Comput. Sci. Technol.},
volume = {22},
number = {5},
pages = {653--660},
year = {2007},
url = {https://doi.org/10.1007/s11390-007-9092-9},
doi = {10.1007/S11390-007-9092-9},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/ZhouCLH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiHZZBYYPC07,
author = {Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou and
Shan Zeng and
Jinian Bian and
Wenjian Yu and
Hannah Honghua Yang and
Vijay Pitchumani and
Chung{-}Kuan Cheng},
title = {Efficient Thermal via Planning Approach and Its Application in 3-D
Floorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {4},
pages = {645--658},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885831},
doi = {10.1109/TCAD.2006.885831},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiHZZBYYPC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZouCZHTK07,
author = {Yi Zou and
Yici Cai and
Qiang Zhou and
Xianlong Hong and
Sheldon X.{-}D. Tan and
Le Kang},
title = {Practical Implementation of Stochastic Parameterized Model Order Reduction
via Hermite Polynomial Chaos},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {367--372},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358013},
doi = {10.1109/ASPDAC.2007.358013},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZouCZHTK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuoCZH07,
author = {Liangpeng Guo and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {Logic and Layout Aware Voltage Island Generation for Low Power Design},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {666--671},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358063},
doi = {10.1109/ASPDAC.2007.358063},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuoCZH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MaLCHRDZ07,
author = {Yuchun Ma and
Zhuoyuan Li and
Jason Cong and
Xianlong Hong and
Glenn Reinman and
Sheqin Dong and
Qiang Zhou},
title = {Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {920--925},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358107},
doi = {10.1109/ASPDAC.2007.358107},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MaLCHRDZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/ZhouMZH07,
author = {Pingqiang Zhou and
Yuchun Ma and
Qiang Zhou and
Xianlong Hong},
title = {Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning},
booktitle = {10th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2007, Beijing, China, 15-18 October, 2007},
pages = {338--343},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/CADCG.2007.4407905},
doi = {10.1109/CADCG.2007.4407905},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/cadgraphics/ZhouMZH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/WangZBQ07,
author = {Yanhua Wang and
Qiang Zhou and
Jinian Bian and
Junhua Qu},
title = {{VPH:} Versatile Routability-Driven Place Algorithm for Hierarchical
FPGAs Based on {VPR}},
booktitle = {10th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2007, Beijing, China, 15-18 October, 2007},
pages = {349--354},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/CADCG.2007.4407907},
doi = {10.1109/CADCG.2007.4407907},
timestamp = {Thu, 01 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/WangZBQ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhuoLZCH07,
author = {Yue Zhuo and
Hao Li and
Qiang Zhou and
Yici Cai and
Xianlong Hong},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {New timing and routability driven placement algorithms for {FPGA}
synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {570--575},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228918},
doi = {10.1145/1228784.1228918},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhuoLZCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhouMLDSZHZ07,
author = {Pingqiang Zhou and
Yuchun Ma and
Zhuoyuan Li and
Robert P. Dick and
Li Shang and
Hai Zhou and
Xianlong Hong and
Qiang Zhou},
editor = {Georges G. E. Gielen},
title = {3D-STAF: scalable temperature and leakage aware floorplanning for
three-dimensional integrated circuits},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {590--597},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397329},
doi = {10.1109/ICCAD.2007.4397329},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ZhouMLDSZHZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangZHC07,
author = {Yanfeng Wang and
Qiang Zhou and
Xianlong Hong and
Yici Cai},
title = {Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {2040--2043},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378498},
doi = {10.1109/ISCAS.2007.378498},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangZHC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YanLHZ07,
author = {Haixia Yan and
Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou},
title = {Unified Quadratic Programming Approach For 3-D Mixed Mode Placement},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3411--3414},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378300},
doi = {10.1109/ISCAS.2007.378300},
timestamp = {Thu, 01 Feb 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YanLHZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/CaiLSZH07,
author = {Yici Cai and
Bin Liu and
Jin Shi and
Qiang Zhou and
Xianlong Hong},
title = {Power Delivery Aware Floorplanning for Voltage Island Designs},
booktitle = {8th International Symposium on Quality of Electronic Design {(ISQED}
2007), 26-28 March 2007, San Jose, CA, {USA}},
pages = {350--355},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISQED.2007.121},
doi = {10.1109/ISQED.2007.121},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/CaiLSZH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiuBZD07,
author = {Zhipeng Liu and
Jinian Bian and
Qiang Zhou and
Hui Dai},
title = {Interconnect Delay and Power Optimization by Module Duplication for
Integration of High Level Synthesis and Floorplan},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {279--284},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.60},
doi = {10.1109/ISVLSI.2007.60},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiuBZD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/CaiLXZH06,
author = {Yici Cai and
Bin Liu and
Yan Xiong and
Qiang Zhou and
Xianlong Hong},
title = {Priority-Based Routing Resource Assignment Considering Crosstalk},
journal = {J. Comput. Sci. Technol.},
volume = {21},
number = {6},
pages = {913--921},
year = {2006},
url = {https://doi.org/10.1007/s11390-006-0913-z},
doi = {10.1007/S11390-006-0913-Z},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/CaiLXZH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Cai0ZH06,
author = {Yici Cai and
Bin Liu and
Qiang Zhou and
Xianlong Hong},
title = {A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource
Assignment},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {10},
pages = {1007--1011},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.882353},
doi = {10.1109/TCSII.2006.882353},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Cai0ZH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/YaoCZH06,
author = {Hailong Yao and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {Multilevel Routing With Redundant Via Insertion},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {10},
pages = {1148--1152},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.881822},
doi = {10.1109/TCSII.2006.881822},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/YaoCZH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LiHZCBYPC06,
author = {Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Jinian Bian and
Hannah Honghua Yang and
Vijay Pitchumani and
Chung{-}Kuan Cheng},
title = {Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {53-I},
number = {12},
pages = {2637--2646},
year = {2006},
url = {https://doi.org/10.1109/TCSI.2006.883857},
doi = {10.1109/TCSI.2006.883857},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LiHZCBYPC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiHZBYP06,
author = {Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou and
Jinian Bian and
Hannah Honghua Yang and
Vijay Pitchumani},
title = {Efficient thermal-oriented 3D floorplanning and thermal via planning
for two-stacked-die integration},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {11},
number = {2},
pages = {325--345},
year = {2006},
url = {https://doi.org/10.1145/1142155.1142159},
doi = {10.1145/1142155.1142159},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiHZBYP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ZhouZCH06,
author = {Qiang Zhou and
Yi Zou and
Yici Cai and
Xianlong Hong},
title = {Variational Circuit Simulator based on a Unified Methodology using
Arithmetic over Taylor Polynomials},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {1635--1638},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342078},
doi = {10.1109/APCCAS.2006.342078},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/ZhouZCH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuCZH06,
author = {Bin Liu and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
editor = {Fumiyasu Hirose},
title = {Power driven placement with layout aware supply voltage assignment
for voltage island generation in Dual-Vdd designs},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {582--587},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594748},
doi = {10.1109/ASPDAC.2006.1594748},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiuCZH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LuoZCHW06,
author = {Lijuan Luo and
Qiang Zhou and
Yici Cai and
Xianlong Hong and
Yibo Wang},
title = {A novel technique integrating buffer insertion into timing driven
placement},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693904},
doi = {10.1109/ISCAS.2006.1693904},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LuoZCHW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhaoCZH06,
author = {Xin Zhao and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {A novel low-power physical design methodology for {MTCMOS}},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693905},
doi = {10.1109/ISCAS.2006.1693905},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhaoCZH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/LiHZZBYPC06,
author = {Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou and
Shan Zeng and
Jinian Bian and
Hannah Honghua Yang and
Vijay Pitchumani and
Chung{-}Kuan Cheng},
editor = {Louis Scheffer},
title = {Integrating dynamic thermal via planning with 3D floorplanning algorithm},
booktitle = {Proceedings of the 2006 International Symposium on Physical Design,
{ISPD} 2006, San Jose, California, USA, April 9-12, 2006},
pages = {178--185},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1123008.1123048},
doi = {10.1145/1123008.1123048},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/LiHZZBYPC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LiuCZH05,
author = {Bin Liu and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {Crosstalk and Congestion Driven Layer Assignment Algorithm},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {6},
pages = {1565--1572},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.6.1565},
doi = {10.1093/IETFEC/E88-A.6.1565},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LiuCZH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZouCZHT05,
author = {Yi Zou and
Yici Cai and
Qiang Zhou and
Xianlong Hong and
Sheldon X.{-}D. Tan},
title = {A Fast Delay Computation for the Hybrid Structured Clock Network},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {7},
pages = {1964--1970},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.7.1964},
doi = {10.1093/IETFEC/E88-A.7.1964},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZouCZHT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LuSHZCHH05,
author = {Yongqiang Lu and
Chin Ngai Sze and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Liang Huang and
Jiang Hu},
title = {Navigating Register Placement for Low Power Clock Network Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3405--3411},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3405},
doi = {10.1093/IETFEC/E88-A.12.3405},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/LuSHZCHH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/YaoCZH05,
author = {Hailong Yao and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {Crosstalk-Aware Routing Resource Assignment},
journal = {J. Comput. Sci. Technol.},
volume = {20},
number = {2},
pages = {231--236},
year = {2005},
url = {https://doi.org/10.1007/s11390-005-0231-x},
doi = {10.1007/S11390-005-0231-X},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/YaoCZH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/CaiZZH05,
author = {Yici Cai and
Xin Zhao and
Qiang Zhou and
Xianlong Hong},
title = {Shielding Area Optimization Under the Solution of Interconnect Crosstalk},
journal = {J. Comput. Sci. Technol.},
volume = {20},
number = {6},
pages = {901--906},
year = {2005},
url = {https://doi.org/10.1007/s11390-005-0901-8},
doi = {10.1007/S11390-005-0901-8},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/CaiZZH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZouZCHT05,
author = {Yi Zou and
Qiang Zhou and
Yici Cai and
Xianlong Hong and
Sheldon X.{-}D. Tan},
editor = {Tingao Tang},
title = {Analysis of buffered hybrid structured clock networks},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {93--98},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120754},
doi = {10.1145/1120725.1120754},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZouZCHT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HuangCZHHL05,
author = {Liang Huang and
Yici Cai and
Qiang Zhou and
Xianlong Hong and
Jiang Hu and
Yongqiang Lu},
editor = {Tingao Tang},
title = {Clock network minimization methodology based on incremental placement},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {99--102},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120755},
doi = {10.1145/1120725.1120755},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HuangCZHHL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LuSHZCHH05,
author = {Yongqiang Lu and
Cliff C. N. Sze and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Liang Huang and
Jiang Hu},
editor = {Tingao Tang},
title = {Register placement for low power clock network},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {588--593},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120971},
doi = {10.1145/1120725.1120971},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LuSHZCHH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LuSHZCHH05,
author = {Yongqiang Lu and
Cliff C. N. Sze and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Liang Huang and
Jiang Hu},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Navigating registers in placement for clock network minimization},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {176--181},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065628},
doi = {10.1145/1065579.1065628},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LuSHZCHH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YaoCHZ05,
author = {Hailong Yao and
Yici Cai and
Xianlong Hong and
Qiang Zhou},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {Improved multilevel routing with redundant via placement for yield
and reliability},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {143--146},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057696},
doi = {10.1145/1057661.1057696},
timestamp = {Wed, 15 Dec 2021 17:59:57 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/YaoCHZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LuoHZC05,
author = {Qinglang Luo and
Xianlong Hong and
Qiang Zhou and
Yici Cai},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {A new algorithm for layout of dark field alternating phase shifting
masks},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {221--224},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057715},
doi = {10.1145/1057661.1057715},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LuoHZC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccsa/LuoZHZ05,
author = {Lijuan Luo and
Qiang Zhou and
Xianlong Hong and
Hanbin Zhou},
editor = {Osvaldo Gervasi and
Marina L. Gavrilova and
Vipin Kumar and
Antonio Lagan{\`{a}} and
Heow Pueh Lee and
Youngsong Mun and
David Taniar and
Chih Jeng Kenneth Tan},
title = {Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode
Layout Design},
booktitle = {Computational Science and Its Applications - {ICCSA} 2005, International
Conference, Singapore, May 9-12, 2005, Proceedings, Part {IV}},
series = {Lecture Notes in Computer Science},
volume = {3483},
pages = {896--905},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11424925\_94},
doi = {10.1007/11424925\_94},
timestamp = {Thu, 28 Apr 2022 16:17:38 +0200},
biburl = {https://dblp.org/rec/conf/iccsa/LuoZHZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icess/WangBHYZW05,
author = {Yunfeng Wang and
Jinian Bian and
Xianlong Hong and
Liu Yang and
Qiang Zhou and
Qiang Wu},
editor = {Laurence Tianruo Yang and
Xingshe Zhou and
Wei Zhao and
Zhaohui Wu and
Yian Zhu and
Man Lin},
title = {A New Methodology of Integrating High Level Synthesis and Floorplan
for SoC Design},
booktitle = {Embedded Software and Systems, Second International Conference, {ICESS}
2005, Xi'an, China, December 16-18, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3820},
pages = {275--286},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11599555\_28},
doi = {10.1007/11599555\_28},
timestamp = {Fri, 09 Apr 2021 18:39:46 +0200},
biburl = {https://dblp.org/rec/conf/icess/WangBHYZW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icnc/CaiLYZH05,
author = {Yici Cai and
Bin Liu and
Xiong Yan and
Qiang Zhou and
Xianlong Hong},
editor = {Lipo Wang and
Ke Chen and
Yew{-}Soon Ong},
title = {A Hybrid Genetic Algorithm and Application to the Crosstalk Aware
Track Assignment Problem},
booktitle = {Advances in Natural Computation, First International Conference, {ICNC}
2005, Changsha, China, August 27-29, 2005, Proceedings, Part {III}},
series = {Lecture Notes in Computer Science},
volume = {3612},
pages = {181--184},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11539902\_21},
doi = {10.1007/11539902\_21},
timestamp = {Sun, 02 Jun 2019 21:14:27 +0200},
biburl = {https://dblp.org/rec/conf/icnc/CaiLYZH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/CaiLZH05,
author = {Yici Cai and
Bin Liu and
Qiang Zhou and
Xianlong Hong},
title = {Integrated routing resource assignment for {RLC} crosstalk minimization},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {1871--1874},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464976},
doi = {10.1109/ISCAS.2005.1464976},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/CaiLZH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiHZCBYYSP05,
author = {Zhuoyuan Li and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Jinian Bian and
Hannal Yang and
Prashant Saxena and
Vijay Pitchumani},
title = {A divide-and-conquer 2.5-D floorplanning algorithm based on statistical
wirelength estimation},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {6230--6233},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1466064},
doi = {10.1109/ISCAS.2005.1466064},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/LiHZCBYYSP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CaiLZH05,
author = {Yici Cai and
Bin Liu and
Qiang Zhou and
Xianlong Hong},
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands
for Low Power {SOC} Design},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven,
Belgium, September 21-23, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3728},
pages = {257--266},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11556930\_27},
doi = {10.1007/11556930\_27},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CaiLZH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ZouCZHT04,
author = {Yi Zou and
Yici Cai and
Qiang Zhou and
Xianlong Hong and
Sheldon X.{-}D. Tan},
title = {A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network},
booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
Jose, CA, USA, Proceedings},
pages = {344--349},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICCD.2004.1347944},
doi = {10.1109/ICCD.2004.1347944},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ZouCZHT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YangHYZCL04,
author = {Changqi Yang and
Xianlong Hong and
Hannah Honghua Yang and
Qiang Zhou and
Yici Cai and
Yongqiang Lu},
title = {Recursively combine floorplan and Q-place in mixed mode placement
based on circuit's variety of block configuration},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {81--84},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YangHYZCL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiuCZH04,
author = {Bin Liu and
Yici Cai and
Qiang Zhou and
Xianlong Hong},
title = {Layer assignment algorithm for {RLC} crosstalk minimization},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {85--88},
publisher = {{IEEE}},
year = {2004},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/LiuCZH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YaoZHC04,
author = {Hailong Yao and
Qiang Zhou and
Xianlong Hong and
Yici Cai},
title = {Crosstalk driven routing resource assignment},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {89--92},
publisher = {{IEEE}},
year = {2004},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YaoZHC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCHZ04,
author = {Yang Wang and
Yici Cai and
Xianlong Hong and
Qiang Zhou},
title = {Algorithm for yield driven correction of layout},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {241--245},
publisher = {{IEEE}},
year = {2004},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangCHZ04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhaoCZHHX04,
author = {Xin Zhao and
Yici Cai and
Qiang Zhou and
Xianlong Hong and
Lei He and
Jinjun Xiong},
title = {Shielding area optimization under the solution of interconnect crosstalk},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {297--300},
publisher = {{IEEE}},
year = {2004},
timestamp = {Tue, 30 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhaoCZHHX04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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