BibTeX records: Jun-Kai Zhao

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@inproceedings{DBLP:conf/iscas/ChiuHZJC16,
  author       = {Yi{-}Wei Chiu and
                  Yu{-}Hao Hu and
                  Jun{-}Kai Zhao and
                  Shyh{-}Jye Jou and
                  Ching{-}Te Chuang},
  title        = {A subthreshold {SRAM} with embedded data-aware write-assist and adaptive
                  data-aware keeper},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
                  Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
  pages        = {1014--1017},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISCAS.2016.7527415},
  doi          = {10.1109/ISCAS.2016.7527415},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ChiuHZJC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/HongCZJWL15,
  author       = {Chi{-}Hao Hong and
                  Yi{-}Wei Chiu and
                  Jun{-}Kai Zhao and
                  Shyh{-}Jye Jou and
                  Wen{-}Tai Wang and
                  Reed Lee},
  title        = {A 28nm 36kb high speed 6T {SRAM} with source follower {PMOS} read
                  and bit-line under-drive},
  booktitle    = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  2015, Lisbon, Portugal, May 24-27, 2015},
  pages        = {2549--2552},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISCAS.2015.7169205},
  doi          = {10.1109/ISCAS.2015.7169205},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/HongCZJWL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/ChiuHTZCJC14,
  author       = {Yi{-}Wei Chiu and
                  Yu{-}Hao Hu and
                  Ming{-}Hsien Tu and
                  Jun{-}Kai Zhao and
                  Yuan{-}Hua Chu and
                  Shyh{-}Jye Jou and
                  Ching{-}Te Chuang},
  title        = {40 nm Bit-Interleaving 12T Subthreshold {SRAM} With Data-Aware Write-Assist},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {61-I},
  number       = {9},
  pages        = {2578--2585},
  year         = {2014},
  url          = {https://doi.org/10.1109/TCSI.2014.2332267},
  doi          = {10.1109/TCSI.2014.2332267},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/ChiuHTZCJC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/HongCZJWL14,
  author       = {Chi{-}Hao Hong and
                  Yi{-}Wei Chiu and
                  Jun{-}Kai Zhao and
                  Shyh{-}Jye Jou and
                  Wen{-}Tai Wang and
                  Reed Lee},
  editor       = {Kaijian Shi and
                  Thomas B{\"{u}}chner and
                  Danella Zhao and
                  Ramalingam Sridhar},
  title        = {A low-power charge sharing hierarchical bitline and voltage-latched
                  sense amplifier for {SRAM} macro in 28 nm {CMOS} technology},
  booktitle    = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
                  Las Vegas, NV, USA, September 2-5, 2014},
  pages        = {160--164},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/SOCC.2014.6948919},
  doi          = {10.1109/SOCC.2014.6948919},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/HongCZJWL14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/ChiuHTZJC13,
  author       = {Yi{-}Wei Chiu and
                  Yu{-}Hao Hu and
                  Ming{-}Hsien Tu and
                  Jun{-}Kai Zhao and
                  Shyh{-}Jye Jou and
                  Ching{-}Te Chuang},
  editor       = {Pai H. Chou and
                  Ru Huang and
                  Yuan Xie and
                  Tanay Karnik},
  title        = {A 40 nm 0.32 {V} 3.5 MHz 11T single-ended bit-interleaving subthreshold
                  {SRAM} with data-aware write-assist},
  booktitle    = {International Symposium on Low Power Electronics and Design (ISLPED),
                  Beijing, China, September 4-6, 2013},
  pages        = {51--56},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISLPED.2013.6629266},
  doi          = {10.1109/ISLPED.2013.6629266},
  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/ChiuHTZJC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}