BibTeX records: Geoff Zhang

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@article{DBLP:journals/jssc/UpadhyayaPLCRZN19,
  author       = {Parag Upadhyaya and
                  Chi Fung Poon and
                  Siok{-}Wei Lim and
                  Junho Cho and
                  Arianne Roldan and
                  Wenfeng Zhang and
                  Jin Namkoong and
                  Toan Pham and
                  Bruce Xu and
                  Winson Lin and
                  Hongtao Zhang and
                  Nakul Narang and
                  Kee Hian Tan and
                  Geoff Zhang and
                  Yohan Frans and
                  Ken Chang},
  title        = {A Fully Adaptive 19-58-Gb/s {PAM-4} and 9.5-29-Gb/s {NRZ} Wireline
                  Transceiver With Configurable {ADC} in 16-nm FinFET},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {1},
  pages        = {18--28},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2018.2875091},
  doi          = {10.1109/JSSC.2018.2875091},
  timestamp    = {Thu, 30 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/UpadhyayaPLCRZN19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/UpadhyayaPLCRZN18,
  author       = {Parag Upadhyaya and
                  Chi Fung Poon and
                  Siok{-}Wei Lim and
                  Junho Cho and
                  Arianne Roldan and
                  Wenfeng Zhang and
                  Jin Namkoong and
                  Toan Pham and
                  Bruce Xu and
                  Winson Lin and
                  Hongtao Zhang and
                  Nakul Narang and
                  Kee Hian Tan and
                  Geoff Zhang and
                  Yohan Frans and
                  Ken Chang},
  title        = {A fully adaptive 19-to-56Gb/s {PAM-4} wireline transceiver with a
                  configurable {ADC} in 16nm FinFET},
  booktitle    = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2018, San Francisco, CA, USA, February 11-15, 2018},
  pages        = {108--110},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISSCC.2018.8310207},
  doi          = {10.1109/ISSCC.2018.8310207},
  timestamp    = {Thu, 30 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/UpadhyayaPLCRZN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/FransSZUIKEHPAB17,
  author       = {Yohan Frans and
                  Jaewook Shin and
                  Lei Zhou and
                  Parag Upadhyaya and
                  Jay Im and
                  Vassili Kireev and
                  Mohamed Elzeftawi and
                  Hiva Hedayati and
                  Toan Pham and
                  Santiago Asuncion and
                  Chris Borrelli and
                  Geoff Zhang and
                  Hongtao Zhang and
                  Ken Chang},
  title        = {A 56-Gb/s {PAM4} Wireline Transceiver Using a 32-Way Time-Interleaved
                  {SAR} {ADC} in 16-nm FinFET},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {52},
  number       = {4},
  pages        = {1101--1110},
  year         = {2017},
  url          = {https://doi.org/10.1109/JSSC.2016.2632300},
  doi          = {10.1109/JSSC.2016.2632300},
  timestamp    = {Thu, 30 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/FransSZUIKEHPAB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ImFRCCCCGMZZHLU17,
  author       = {Jay Im and
                  Dave Freitas and
                  Arianne Roldan and
                  Ronan Casey and
                  Stanley Chen and
                  Adam Chou and
                  Tim Cronin and
                  Kevin Geary and
                  Scott McLeod and
                  Lei Zhou and
                  Ian Zhuang and
                  Jaeduk Han and
                  Sen Lin and
                  Parag Upadhyaya and
                  Geoff Zhang and
                  Yohan Frans and
                  Ken Chang},
  title        = {A 40-to-56 Gb/s {PAM-4} Receiver With Ten-Tap Direct Decision-Feedback
                  Equalization in 16-nm FinFET},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {52},
  number       = {12},
  pages        = {3486--3502},
  year         = {2017},
  url          = {https://doi.org/10.1109/JSSC.2017.2749432},
  doi          = {10.1109/JSSC.2017.2749432},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ImFRCCCCGMZZHLU17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ImFRCCCCGMZZHLU17,
  author       = {Jay Im and
                  Dave Freitas and
                  Arianne Roldan and
                  Ronan Casey and
                  Stanley Chen and
                  Adam Chou and
                  Tim Cronin and
                  Kevin Geary and
                  Scott McLeod and
                  Lei Zhou and
                  Ian Zhuang and
                  Jaeduk Han and
                  Sen Lin and
                  Parag Upadhyaya and
                  Geoff Zhang and
                  Yohan Frans and
                  Ken Chang},
  title        = {6.3 {A} 40-to-56Gb/s {PAM-4} receiver with 10-tap direct decision-feedback
                  equalization in 16nm FinFET},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {114--115},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870287},
  doi          = {10.1109/ISSCC.2017.7870287},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ImFRCCCCGMZZHLU17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/FransEHIKPSUZAB16,
  author       = {Yohan Frans and
                  Mohamed Elzeftawi and
                  Hiva Hedayati and
                  Jay Im and
                  Vassili Kireev and
                  Toan Pham and
                  Jaewook Shin and
                  Parag Upadhyaya and
                  Lei Zhou and
                  Santiago Asuncion and
                  Chris Borrelli and
                  Geoff Zhang and
                  Hongtao Zhang and
                  Ken Chang},
  title        = {A 56Gb/s {PAM4} wireline transceiver using a 32-way time-interleaved
                  {SAR} {ADC} in 16nm FinFET},
  booktitle    = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
                  HI, USA, June 15-17, 2016},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/VLSIC.2016.7573474},
  doi          = {10.1109/VLSIC.2016.7573474},
  timestamp    = {Thu, 30 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/FransEHIKPSUZAB16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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