BibTeX records: Hung-Chang Yu

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@article{DBLP:journals/jaihc/YuCLH23,
  author       = {Hung{-}Chang Yu and
                  C.{-}J. Chou and
                  Ding{-}Bang Luh and
                  Ming{-}Hsuan Hsieh},
  title        = {User-centered empathy design: a prototype of school-age children learning
                  aids system},
  journal      = {J. Ambient Intell. Humaniz. Comput.},
  volume       = {14},
  number       = {11},
  pages        = {14567--14575},
  year         = {2023},
  url          = {https://doi.org/10.1007/s12652-018-1047-1},
  doi          = {10.1007/S12652-018-1047-1},
  timestamp    = {Mon, 22 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jaihc/YuCLH23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShihLCLLCLYYCCC19,
  author       = {Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Ku{-}Feng Lin and
                  Ta{-}Ching Yeh and
                  Hung{-}Chang Yu and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM
                  With Hybrid-Resistance Reference, Sub- {\textdollar}{\textbackslash}mu{\textdollar}
                  {A} Sensing Resolution, and 17.5-nS Read Access Time},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {4},
  pages        = {1029--1038},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2018.2889106},
  doi          = {10.1109/JSSC.2018.2889106},
  timestamp    = {Wed, 07 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShihLCLLCLYYCCC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/ShihLCLLCLYYCCC18,
  author       = {Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Ku{-}Feng Lin and
                  Ta{-}Ching Yeh and
                  Hung{-}Chang Yu and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with
                  Hybrid-Resistance Reference, Sub-{\(\mu\)}A Sensing Resolution, and
                  17.5NS Read Access Time},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {79--80},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502260},
  doi          = {10.1109/VLSIC.2018.8502260},
  timestamp    = {Wed, 07 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YuLLHCOCNT13,
  author       = {Hung{-}Chang Yu and
                  Kai{-}Chun Lin and
                  Ku{-}Feng Lin and
                  Chin{-}Yi Huang and
                  Yu{-}Der Chih and
                  Tong{-}Chern Ong and
                  Tsung{-}Yung Jonathan Chang and
                  Sreedhar Natarajan and
                  Luan C. Tran},
  title        = {Cycling endurance optimization scheme for 1Mb {STT-MRAM} in 40nm technology},
  booktitle    = {2013 {IEEE} International Solid-State Circuits Conference - Digest
                  of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
                  17-21, 2013},
  pages        = {224--225},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISSCC.2013.6487710},
  doi          = {10.1109/ISSCC.2013.6487710},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YuLLHCOCNT13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi-dat/YuLLCN13,
  author       = {Hung{-}Chang Yu and
                  Ku{-}Feng Lin and
                  Kai{-}Chun Lin and
                  Yu{-}Der Chih and
                  Sreedhar Natarajan},
  title        = {A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology
                  operating under wide range power supply from 2.1V to 3.6V},
  booktitle    = {2013 International Symposium on {VLSI} Design, Automation, and Test,
                  {VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/VLDI-DAT.2013.6533858},
  doi          = {10.1109/VLDI-DAT.2013.6533858},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/YuLLCN13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}