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ORCIDBibTeX records: Ranga Vemuri
@inproceedings{DBLP:conf/vlsid/MekaMV24,
author = {Juneet Kumar Meka and
Satya AmarKant Marupureddy and
Ranga Vemuri},
title = {Pattern Based Synthetic Benchmark Generation for Hardware Security
Applications},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {461--466},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00083},
doi = {10.1109/VLSID60093.2024.00083},
timestamp = {Mon, 08 Apr 2024 20:48:39 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/MekaMV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ChakrabortyV24,
author = {Haimanti Chakraborty and
Ranga Vemuri},
title = {{ROBUST:} {RTL} OBfuscation USing Bi-functional Polymorphic OperaTors},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {499--504},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00089},
doi = {10.1109/VLSID60093.2024.00089},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/ChakrabortyV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SaxenaV24,
author = {Nikhil Saxena and
Ranga Vemuri},
title = {Enhancing Output Corruption Through {GSHE} Switch Based Logic Encryption},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {505--510},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00090},
doi = {10.1109/VLSID60093.2024.00090},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/SaxenaV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SrinivasanV24,
author = {Suriya Srinivasan and
Ranga Vemuri},
title = {Trojan Localization Using Information Flow Tracking Properties in
SoC Designs},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {523--528},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00093},
doi = {10.1109/VLSID60093.2024.00093},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/SrinivasanV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/SaxenaV23,
author = {Nikhil Saxena and
Ranga Vemuri},
title = {Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption},
journal = {{IEEE} Access},
volume = {11},
pages = {128484--128499},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3332543},
doi = {10.1109/ACCESS.2023.3332543},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/SaxenaV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/MekaV23,
author = {Juneet Kumar Meka and
Ranga Vemuri},
title = {Attributed Graph Transformation for Generating Synthetic Benchmarks
for Hardware Security},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129284},
doi = {10.1109/ISQED57927.2023.10129284},
timestamp = {Thu, 01 Jun 2023 22:29:52 +0200},
biburl = {https://dblp.org/rec/conf/isqed/MekaV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/NarayananVPMV23,
author = {Ram Venkat Narayanan and
Aparajithan Nathamuni Venkatesan and
Kishore Pula and
Sundarakumar Muthukumaran and
Ranga Vemuri},
title = {Reverse Engineering Word-Level Models from Look-Up Table Netlists},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129373},
doi = {10.1109/ISQED57927.2023.10129373},
timestamp = {Thu, 01 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/NarayananVPMV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MuthukumaranVPNVE23,
author = {Sundarakumar Muthukumaran and
Aparajithan Nathamuni Venkatesan and
Kishore Pula and
Ram Venkat Narayanan and
Ranga Vemuri and
John Marty Emmert},
title = {Reverse Engineering of {RTL} Controllers from Look-Up Table Netlists},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2023, Foz
do Iguacu, Brazil, June 20-23, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISVLSI59464.2023.10238540},
doi = {10.1109/ISVLSI59464.2023.10238540},
timestamp = {Wed, 13 Sep 2023 08:43:37 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/MuthukumaranVPNVE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/PulaVNMVE23,
author = {Kishore Pula and
Aparajithan Nathamuni Venkatesan and
Ram Venkat Narayanan and
Sundarakumar Muthukumaran and
Ranga Vemuri and
John Marty Emmert},
title = {{RELUT-GNN:} Reverse Engineering Data Path Elements From {LUT} Netlists
Using Graph Neural Networks},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {511--515},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10406081},
doi = {10.1109/MWSCAS57524.2023.10406081},
timestamp = {Sat, 24 Feb 2024 20:42:53 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/PulaVNMVE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ChakrabortyV23,
author = {Haimanti Chakraborty and
Ranga Vemuri},
title = {Split Manufacturing Based Secure Hardware Design by {BEOL} Signal
Selection In High Level Synthesis},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {1083--1087},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10406114},
doi = {10.1109/MWSCAS57524.2023.10406114},
timestamp = {Sat, 24 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/ChakrabortyV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/SaxenaV23,
author = {Nikhil Saxena and
Ranga Vemuri},
title = {Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {1103--1107},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10405970},
doi = {10.1109/MWSCAS57524.2023.10405970},
timestamp = {Sat, 24 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/SaxenaV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BhamidipatiV23,
author = {Padmaja Bhamidipati and
Ranga Vemuri},
title = {{ASPIRE:} An Intermediate Representation for Abstract Security Policies},
booktitle = {36th International Conference on {VLSI} Design and 2023 22nd International
Conference on Embedded Systems, {VLSID} 2023, Hyderabad, India, January
8-12, 2023},
pages = {175--180},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSID57277.2023.00046},
doi = {10.1109/VLSID57277.2023.00046},
timestamp = {Sat, 22 Apr 2023 17:02:07 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/BhamidipatiV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SrinivasanV23,
author = {Suriya Srinivasan and
Ranga Vemuri},
title = {Mutation Analysis and Model Checking Guided Test Generation for SoC
Run-Time Monitors},
booktitle = {36th International Conference on {VLSI} Design and 2023 22nd International
Conference on Embedded Systems, {VLSID} 2023, Hyderabad, India, January
8-12, 2023},
pages = {240--245},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSID57277.2023.00057},
doi = {10.1109/VLSID57277.2023.00057},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/SrinivasanV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VenkatesanNPMV23,
author = {Aparajithan Nathamuni Venkatesan and
Ram Venkat Narayanan and
Kishore Pula and
Sundarakumar Muthukumaran and
Ranga Vemuri},
title = {Word-Level Structure Identification In {FPGA} Designs Using Cell Proximity
Information},
booktitle = {36th International Conference on {VLSI} Design and 2023 22nd International
Conference on Embedded Systems, {VLSID} 2023, Hyderabad, India, January
8-12, 2023},
pages = {389--394},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSID57277.2023.00083},
doi = {10.1109/VLSID57277.2023.00083},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/VenkatesanNPMV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2303-02762,
author = {Ram Venkat Narayanan and
Aparajithan Nathamuni Venkatesan and
Kishore Pula and
Sundarakumar Muthukumaran and
Ranga Vemuri},
title = {Reverse Engineering Word-Level Models from Look-Up Table Netlists},
journal = {CoRR},
volume = {abs/2303.02762},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2303.02762},
doi = {10.48550/ARXIV.2303.02762},
eprinttype = {arXiv},
eprint = {2303.02762},
timestamp = {Tue, 14 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2303-02762.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2303-07405,
author = {Aparajithan Nathamuni Venkatesan and
Ram Venkat Narayanan and
Kishore Pula and
Sundarakumar Muthukumaran and
Ranga Vemuri},
title = {Word-Level Structure Identification In {FPGA} Designs Using Cell Proximity
Information},
journal = {CoRR},
volume = {abs/2303.07405},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2303.07405},
doi = {10.48550/ARXIV.2303.07405},
eprinttype = {arXiv},
eprint = {2303.07405},
timestamp = {Mon, 20 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2303-07405.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AlatounV22,
author = {Khitam M. Alatoun and
Ranga Vemuri},
editor = {Ioannis Savidis and
Avesta Sasan and
Himanshu Thapliyal and
Ronald F. DeMara},
title = {Efficient Method for Timing-based Information Flow Verification in
Hardware Designs},
booktitle = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
June 6 - 8, 2022},
pages = {159--163},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3526241.3530363},
doi = {10.1145/3526241.3530363},
timestamp = {Fri, 03 Jun 2022 08:45:20 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AlatounV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SrinivasanV22,
author = {Suriya Srinivasan and
Ranga Vemuri},
title = {Model Checking Leveraged Error Localization for Complex {RTL} Designs},
booktitle = {{IEEE} 40th International Conference on Computer Design, {ICCD} 2022,
Olympic Valley, CA, USA, October 23-26, 2022},
pages = {585--592},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICCD56317.2022.00092},
doi = {10.1109/ICCD56317.2022.00092},
timestamp = {Tue, 05 Dec 2023 14:45:33 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SrinivasanV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/MekaVV22,
author = {Juneet Kumar Meka and
Shrinidhi Venkatesh and
Ranga Vemuri},
title = {Analysis of the Satisfiability Attack Against Logic Encryption Using
Synthetic Benchmarks},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2022,
Warangal, India, December 18-22, 2022},
pages = {445--450},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/iSES54909.2022.00096},
doi = {10.1109/ISES54909.2022.00096},
timestamp = {Wed, 15 Feb 2023 22:08:03 +0100},
biburl = {https://dblp.org/rec/conf/ises/MekaVV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SaxenaV22,
author = {Nikhil Saxena and
Ranga Vemuri},
title = {ISPLock: {A} Hybrid Internal State Locking Method Using Polymorphic
Gates},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {140--145},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00037},
doi = {10.1109/ISVLSI54635.2022.00037},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SaxenaV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ChuvalasV22,
author = {Christopher Chuvalas and
Ranga Vemuri},
title = {{FPGA} Acceleration of a Stochastic Local Search Portfolio Solver
for Boolean Satisfiability},
booktitle = {65th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2022, Fukuoka, Japan, August 7-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MWSCAS54063.2022.9859479},
doi = {10.1109/MWSCAS54063.2022.9859479},
timestamp = {Mon, 29 Aug 2022 17:33:26 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ChuvalasV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChuvalasV22,
author = {Christopher Chuvalas and
Ranga Vemuri},
title = {FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting
High Bandwidth Memory},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939631},
doi = {10.1109/VLSI-SOC54400.2022.9939631},
timestamp = {Mon, 14 Nov 2022 17:06:23 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChuvalasV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/22/AgrawalV22,
author = {Richa Agrawal and
Ranga Vemuri},
title = {Encoding of Finite-State Controllers for Graded Security and Power},
booktitle = {Behavioral Synthesis for Hardware Security},
pages = {147--175},
year = {2022},
url = {https://doi.org/10.1007/978-3-030-78841-4\_8},
doi = {10.1007/978-3-030-78841-4\_8},
timestamp = {Tue, 05 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/22/AgrawalV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/22/BorowczakV22,
author = {Mike Borowczak and
Ranga Vemuri},
title = {S*FSMs for Reduced Information Leakage: Power Side Channel Protection
Through Secure Encoding},
booktitle = {Behavioral Synthesis for Hardware Security},
pages = {319--342},
year = {2022},
url = {https://doi.org/10.1007/978-3-030-78841-4\_14},
doi = {10.1007/978-3-030-78841-4\_14},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/22/BorowczakV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/LuriaV21,
author = {David M. Luria and
Ranga Vemuri},
title = {Logic Encryption for Resource Constrained Designs},
journal = {{IEEE} Access},
volume = {9},
pages = {29312--29345},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2021.3059163},
doi = {10.1109/ACCESS.2021.3059163},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/LuriaV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/AlatounAV21,
author = {Khitam M. Alatoun and
Shanmukha Murali Achyutha and
Ranga Vemuri},
title = {Efficient Methods for SoC Trust Validation Using Information Flow
Verification},
booktitle = {39th {IEEE} International Conference on Computer Design, {ICCD} 2021,
Storrs, CT, USA, October 24-27, 2021},
pages = {608--616},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCD53106.2021.00098},
doi = {10.1109/ICCD53106.2021.00098},
timestamp = {Tue, 28 Dec 2021 14:09:48 +0100},
biburl = {https://dblp.org/rec/conf/iccd/AlatounAV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/SaxenaNMV21,
author = {Nikhil Saxena and
Ram Venkat Narayanan and
Juneet Kumar Meka and
Ranga Vemuri},
title = {SRTLock: {A} Sensitivity Resilient Two-Tier Logic Encryption Scheme},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2021,
Jaipur, India, December 18-22, 2021},
pages = {389--394},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/iSES52644.2021.00095},
doi = {10.1109/ISES52644.2021.00095},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/SaxenaNMV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/AlatounSAV21,
author = {Khitam Alatoun and
Bharath Shankaranarayanan and
Shanmukha Murali Achyutha and
Ranga Vemuri},
title = {SoC Trust Validation Using Assertion-Based Security Monitors},
booktitle = {22nd International Symposium on Quality Electronic Design, {ISQED}
2021, Santa Clara, CA, USA, April 7-9, 2021},
pages = {496--503},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISQED51717.2021.9424363},
doi = {10.1109/ISQED51717.2021.9424363},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/AlatounSAV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RajaBLV21,
author = {Subashree Raja and
Padmaja Bhamidipati and
Xiaobang Liu and
Ranga Vemuri},
title = {Security Capsules: An Architecture for Post-Silicon Security Assertion
Validation for Systems-on-Chip},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2021, Tampa,
FL, USA, July 7-9, 2021},
pages = {248--253},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISVLSI51109.2021.00053},
doi = {10.1109/ISVLSI51109.2021.00053},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/RajaBLV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/BhamidipatiAV21,
author = {Padmaja Bhamidipati and
Shanmukha Murali Achyutha and
Ranga Vemuri},
title = {Security Analysis of a System-on-Chip Using Assertion-Based Verification},
booktitle = {64th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2021, Lansing, MI, USA, August 9-11, 2021},
pages = {826--831},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MWSCAS47672.2021.9531916},
doi = {10.1109/MWSCAS47672.2021.9531916},
timestamp = {Wed, 22 Sep 2021 16:10:31 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/BhamidipatiAV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/PurdyEJV21,
author = {Carla Purdy and
John Marty Emmert and
Rashmi Jha and
Ranga Vemuri},
title = {Educating the Next Generation of Cybersecurity Defenders at the University
of Cincinnati},
booktitle = {64th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2021, Lansing, MI, USA, August 9-11, 2021},
pages = {836--839},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MWSCAS47672.2021.9531924},
doi = {10.1109/MWSCAS47672.2021.9531924},
timestamp = {Thu, 27 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/PurdyEJV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/TummalaLV20,
author = {Suprajaa Tummala and
Xiaobang Liu and
Ranga Vemuri},
title = {Signal Selection Heuristics for Post-Silicon Validation},
booktitle = {21st International Symposium on Quality Electronic Design, {ISQED}
2020, Santa Clara, CA, USA, March 25-26, 2020},
pages = {401--407},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISQED48828.2020.9137037},
doi = {10.1109/ISQED48828.2020.9137037},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/TummalaLV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/KasarabadaMV20,
author = {Yasaswy Kasarabada and
Vaishali Muralidharan and
Ranga Vemuri},
title = {{SLED:} Sequential Logic Encryption Using Dynamic Keys},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {844--847},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184664},
doi = {10.1109/MWSCAS48704.2020.9184664},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/KasarabadaMV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KasarabadaV20,
author = {Yasaswy Kasarabada and
Ranga Vemuri},
title = {StateLock: State Transition Based Logic Locking for Sequential Circuits},
booktitle = {33rd International Conference on {VLSI} Design and 19th International
Conference on Embedded Systems, {VLSID} 2020, Bangalore, India, January
4-8, 2020},
pages = {171--176},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSID49098.2020.00047},
doi = {10.1109/VLSID49098.2020.00047},
timestamp = {Mon, 14 Nov 2022 15:28:08 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KasarabadaV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/AgrawalVB19,
author = {Richa Agrawal and
Ranga Vemuri and
Mike Borowczak},
title = {A State Machine Encoding Methodology Against Power Analysis Attacks},
journal = {J. Electron. Test.},
volume = {35},
number = {5},
pages = {621--639},
year = {2019},
url = {https://doi.org/10.1007/s10836-019-05821-z},
doi = {10.1007/S10836-019-05821-Z},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/AgrawalVB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/BorowczakV19,
author = {Mike Borowczak and
Ranga Vemuri},
title = {Mitigating information leakage during critical communication using
S*FSM},
journal = {{IET} Comput. Digit. Tech.},
volume = {13},
number = {4},
pages = {292--301},
year = {2019},
url = {https://doi.org/10.1049/iet-cdt.2018.5186},
doi = {10.1049/IET-CDT.2018.5186},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/BorowczakV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/ChenV19,
author = {Suyuan Chen and
Ranga Vemuri},
title = {Exploiting Proximity Information in a Satisfiability Based Attack
Against Split Manufactured Circuits},
booktitle = {{IEEE} International Symposium on Hardware Oriented Security and Trust,
{HOST} 2019, McLean, VA, USA, May 5-10, 2019},
pages = {171--180},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/HST.2019.8740833},
doi = {10.1109/HST.2019.8740833},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/host/ChenV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifipiot/KasarabadaLV19,
author = {Yasaswy Kasarabada and
David M. Luria and
Ranga Vemuri},
editor = {Augusto Casaca and
Srinivas Katkoori and
Sandip Ray and
Leon Strous},
title = {Trust in IoT Devices: {A} Logic Encryption Perspective},
booktitle = {Internet of Things. {A} Confluence of Many Disciplines - Second {IFIP}
International Cross-Domain Conference, IFIPIoT 2019, Tampa, FL, USA,
October 31 - November 1, 2019, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {574},
pages = {123--141},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-43605-6\_8},
doi = {10.1007/978-3-030-43605-6\_8},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ifipiot/KasarabadaLV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KasarabadaCV19,
author = {Yasaswy Kasarabada and
Suyuan Chen and
Ranga Vemuri},
title = {On SAT-Based Attacks On Encrypted Sequential Logic Circuits},
booktitle = {20th International Symposium on Quality Electronic Design, {ISQED}
2019, Santa Clara, CA, USA, March 6-7, 2019},
pages = {204--211},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISQED.2019.8697421},
doi = {10.1109/ISQED.2019.8697421},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/KasarabadaCV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiuV19,
author = {Xiaobang Liu and
Ranga Vemuri},
title = {Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation},
booktitle = {20th International Symposium on Quality Electronic Design, {ISQED}
2019, Santa Clara, CA, USA, March 6-7, 2019},
pages = {271--277},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISQED.2019.8697793},
doi = {10.1109/ISQED.2019.8697793},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LiuV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KasarabadaRV19,
author = {Yasaswy Kasarabada and
Sudheer Ram Thulasi Raman and
Ranga Vemuri},
title = {Deep State Encryption for Sequential Logic Circuits},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {338--343},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00068},
doi = {10.1109/ISVLSI.2019.00068},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/KasarabadaRV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/VamjaAV19,
author = {Harsh Vamja and
Richa Agrawal and
Ranga Vemuri},
editor = {Hoi Lee and
Randall L. Geiger},
title = {Non-Invasive Reverse Engineering of Finite State Machines Using Power
Analysis and Boolean Satisfiability},
booktitle = {62nd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2019, Dallas, TX, USA, August 4-7, 2019},
pages = {452--455},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MWSCAS.2019.8885300},
doi = {10.1109/MWSCAS.2019.8885300},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/VamjaAV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AgrawalBV19,
author = {Richa Agrawal and
Mike Borowczak and
Ranga Vemuri},
title = {A State Encoding Methodology for Side-Channel Security vs. Power Trade-off
Exploration},
booktitle = {32nd International Conference on {VLSI} Design and 18th International
Conference on Embedded Systems, {VLSID} 2019, Delhi, India, January
5-9, 2019},
pages = {70--75},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSID.2019.00031},
doi = {10.1109/VLSID.2019.00031},
timestamp = {Mon, 14 Nov 2022 15:28:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AgrawalBV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1908-01979,
author = {Harsh Vamja and
Richa Agrawal and
Ranga Vemuri},
title = {Non-Invasive Reverse Engineering of Finite State Machines Using Power
Analysis and Boolean Satisfiability},
journal = {CoRR},
volume = {abs/1908.01979},
year = {2019},
url = {http://arxiv.org/abs/1908.01979},
eprinttype = {arXiv},
eprint = {1908.01979},
timestamp = {Fri, 09 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1908-01979.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChenV18,
author = {Suyuan Chen and
Ranga Vemuri},
editor = {Deming Chen and
Houman Homayoun and
Baris Taskin},
title = {Improving the Security of Split Manufacturing Using a Novel {BEOL}
Signal Selection Method},
booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI, {GLSVLSI}
2018, Chicago, IL, USA, May 23-25, 2018},
pages = {135--140},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3194554.3194564},
doi = {10.1145/3194554.3194564},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ChenV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/AgrawalV18,
author = {Richa Agrawal and
Ranga Vemuri},
title = {On state encoding against power analysis attacks for finite state
controllers},
booktitle = {2018 {IEEE} International Symposium on Hardware Oriented Security
and Trust, {HOST} 2018, Washington, DC, USA, April 30 - May 4, 2018},
pages = {181--186},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/HST.2018.8383911},
doi = {10.1109/HST.2018.8383911},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/AgrawalV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ChenV18,
author = {Suyuan Chen and
Ranga Vemuri},
title = {Reverse Engineering of Split Manufactured Sequential Circuits Using
Satisfiability Checking},
booktitle = {36th {IEEE} International Conference on Computer Design, {ICCD} 2018,
Orlando, FL, USA, October 7-10, 2018},
pages = {530--536},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ICCD.2018.00085},
doi = {10.1109/ICCD.2018.00085},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ChenV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/LokareV18,
author = {Renuka Lokare and
Ranga Vemuri},
title = {Progressive and secure performance unlocking for digital integrated
circuits},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2018,
Las Vegas, NV, USA, January 12-14, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICCE.2018.8326339},
doi = {10.1109/ICCE.2018.8326339},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccel/LokareV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccel/NayakV18,
author = {Ankita Manjunath Nayak and
Ranga Vemuri},
title = {A secure tunable-precision architecture for image processing applications},
booktitle = {{IEEE} International Conference on Consumer Electronics, {ICCE} 2018,
Las Vegas, NV, USA, January 12-14, 2018},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICCE.2018.8326340},
doi = {10.1109/ICCE.2018.8326340},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccel/NayakV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiuV18,
author = {Xiaobang Liu and
Ranga Vemuri},
title = {Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon
Validation},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {34--39},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00017},
doi = {10.1109/ISVLSI.2018.00017},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiuV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/DharmadhikariRV18,
author = {Pranav Dharmadhikari and
Akhilesh Raju and
Ranga Vemuri},
title = {Detection of Sequential Trojans in Embedded System Designs Without
Scan Chains},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {678--683},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00128},
doi = {10.1109/ISVLSI.2018.00128},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/DharmadhikariRV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChenV18,
author = {Suyuan Chen and
Ranga Vemuri},
title = {On the Effectiveness of the Satisfiability Attack on Split Manufactured
Circuits},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {83--88},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644963},
doi = {10.1109/VLSI-SOC.2018.8644963},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChenV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/LiuV18,
author = {Xiaobang Liu and
Ranga Vemuri},
title = {Combined Inference and Satisfiability Based Methods for Complete Signal
Restoration in Post-Silicon Validation},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {416--421},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.100},
doi = {10.1109/VLSID.2018.100},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/LiuV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LiuV17,
author = {Xiaobang Liu and
Ranga Vemuri},
title = {Effective Signal Restoration in Post-Silicon Validation},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {169--176},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.34},
doi = {10.1109/ICCD.2017.34},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LiuV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cj/YiTV16,
author = {Haibo Yi and
Shaohua Tang and
Ranga Vemuri},
title = {Fast Inversions in Small Finite Fields by Using Binary Trees},
journal = {Comput. J.},
volume = {59},
number = {7},
pages = {1102--1112},
year = {2016},
url = {https://doi.org/10.1093/comjnl/bxw009},
doi = {10.1093/COMJNL/BXW009},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cj/YiTV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KomariV16,
author = {Prabanjan Komari and
Ranga Vemuri},
title = {A novel simulation based approach for trace signal selection in silicon
debug},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {193--200},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753280},
doi = {10.1109/ICCD.2016.7753280},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KomariV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/BorowczakV14,
author = {Mike Borowczak and
Ranga Vemuri},
title = {Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2014, Tampa,
FL, USA, July 9-11, 2014},
pages = {232--235},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISVLSI.2014.78},
doi = {10.1109/ISVLSI.2014.78},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/BorowczakV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/NairV14,
author = {Ramesh Nair and
Ranga Vemuri},
editor = {Kaijian Shi and
Thomas B{\"{u}}chner and
Danella Zhao and
Ramalingam Sridhar},
title = {MITH-Dyn: {A} multi Vth dynamic logic design style using mixed mode
FinFETs},
booktitle = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
Las Vegas, NV, USA, September 2-5, 2014},
pages = {140--145},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/SOCC.2014.6948915},
doi = {10.1109/SOCC.2014.6948915},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/NairV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/BorowczakV13,
author = {Mike Borowczak and
Ranga Vemuri},
title = {Secure controllers: Requirements of S*FSM},
booktitle = {{IEEE} 56th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2013, Columbus, OH, USA, August 4-7, 2013},
pages = {553--557},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/MWSCAS.2013.6674708},
doi = {10.1109/MWSCAS.2013.6674708},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/BorowczakV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/BalasubramanianXV13,
author = {Venkat Krishnan Balasubramanian and
Hao Xu and
Ranga Vemuri},
editor = {Norbert Schuhmann and
Kaijian Shi and
Nagi Naganathan},
title = {Design automation flow for voltage adaptive optimum granularity {LITHE}
for sequential circuits},
booktitle = {2013 {IEEE} International {SOC} Conference, Erlangen, Germany, September
4-6, 2013},
pages = {355--360},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SOCC.2013.6749715},
doi = {10.1109/SOCC.2013.6749715},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/BalasubramanianXV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/AvakianAV12,
author = {Annie Avakian and
Natwar Agrawal and
Ranga Vemuri},
editor = {Oliver C. S. Choy and
Ray C. C. Cheung and
Peter M. Athanas and
Kentaro Sano},
title = {Reconfigurable Multicore Architecture for Dynamic Processor Reallocation},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
8th International Symposium, {ARC} 2012, Hong Kong, China, March 19-23,
2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7199},
pages = {329--334},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-28365-9\_28},
doi = {10.1007/978-3-642-28365-9\_28},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/AvakianAV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/RamakrishnanCMBV12,
author = {Lakshmi Narasimhan Ramakrishnan and
Manoj Chakkaravarthy and
Antarpreet Singh Manchanda and
Mike Borowczak and
Ranga Vemuri},
title = {SDMLp: On the use of complementary Pass transistor Logic for design
of {DPA} resistant circuits},
booktitle = {2012 {IEEE} International Symposium on Hardware-Oriented Security
and Trust, {HOST} 2012, San Francisco, CA, USA, June 3-4, 2012},
pages = {31--36},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/HST.2012.6224315},
doi = {10.1109/HST.2012.6224315},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/RamakrishnanCMBV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/PattabiramanAV12,
author = {Aishwariya Pattabiraman and
Annie Avakian and
Ranga Vemuri},
title = {A Heterogeneous Cache Distribution with Reconfigurable Interconnect},
booktitle = {26th {IEEE} International Parallel and Distributed Processing Symposium
Workshops {\&} PhD Forum, {IPDPS} 2012, Shanghai, China, May 21-25,
2012},
pages = {271--276},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/IPDPSW.2012.31},
doi = {10.1109/IPDPSW.2012.31},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/PattabiramanAV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuVJ11,
author = {Hao Xu and
Ranga Vemuri and
Wen{-}Ben Jone},
title = {Dynamic Characteristics of Power Gating During Mode Transition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {2},
pages = {237--249},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2033699},
doi = {10.1109/TVLSI.2009.2033699},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuVJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuJV11,
author = {Hao Xu and
Wen{-}Ben Jone and
Ranga Vemuri},
title = {Aggressive Runtime Leakage Control Through Adaptive Light-Weight V\({}_{\mbox{th}}\)
Hopping With Temperature and Process Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {7},
pages = {1319--1323},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2047955},
doi = {10.1109/TVLSI.2010.2047955},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuJV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/PandaAV11,
author = {Amayika Panda and
Annie Avakian and
Ranga Vemuri},
title = {Configurable workload generators for multicore architectures},
booktitle = {{IEEE} 24th International SoC Conference, {SOCC} 2011, Taipei, Taiwan,
September 26-28, 2011},
pages = {179--184},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/SOCC.2011.6085077},
doi = {10.1109/SOCC.2011.6085077},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/PandaAV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/XuJV10,
author = {Hao Xu and
Wen{-}Ben Jone and
Ranga Vemuri},
title = {Tuning \emph{V}th Hopping for Aggressive Runtime Leakage Control},
journal = {J. Low Power Electron.},
volume = {6},
number = {3},
pages = {447--456},
year = {2010},
url = {https://doi.org/10.1166/jolpe.2010.1094},
doi = {10.1166/JOLPE.2010.1094},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/XuJV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XuJV10,
author = {Hao Xu and
Wen{-}Ben Jone and
Ranga Vemuri},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Stretching the limit of microarchitectural level leakage control with
Adaptive Light-Weight Vth Hopping},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {632--636},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654230},
doi = {10.1109/ICCAD.2010.5654230},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/XuJV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XuVJ10,
author = {Hao Xu and
Ranga Vemuri and
Wen{-}Ben Jone},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Current shaping and multi-thread activation for fast and reliable
power mode transition in multicore designs},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {637--641},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654224},
doi = {10.1109/ICCAD.2010.5654224},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/XuVJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/AvakianNPV10,
author = {Annie Avakian and
Jon Nafziger and
Amayika Panda and
Ranga Vemuri},
title = {A reconfigurable architecture for multicore systems},
booktitle = {24th {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings},
pages = {1--8},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/IPDPSW.2010.5470753},
doi = {10.1109/IPDPSW.2010.5470753},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/AvakianNPV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/NafzigerAV10,
author = {Jon Nafziger and
Annie Avakian and
Ranga Vemuri},
editor = {Thomas B{\"{u}}chner and
Ramalingam Sridhar and
Andrew Marshall and
Norbert Schuhmann},
title = {A prediction-based, data Migration Algorithm for hybrid Architecture
NoC systems},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,
2010, Las Vegas, NV, USA, Proceedings},
pages = {435--440},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/SOCC.2010.5784671},
doi = {10.1109/SOCC.2010.5784671},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/NafzigerAV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/XuJV10,
author = {Hao Xu and
Wen{-}Ben Jone and
Ranga Vemuri},
title = {Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {51--56},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.86},
doi = {10.1109/VLSI.DESIGN.2010.86},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/XuJV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/XuVJ09,
author = {Hao Xu and
Ranga Vemuri and
Wen{-}Ben Jone},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Selective light Vth hopping {(SLITH):} Bridging the gap between runtime
dynamic and leakage},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {594--597},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090735},
doi = {10.1109/DATE.2009.5090735},
timestamp = {Fri, 06 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/XuVJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DasV09,
author = {Angan Das and
Ranga Vemuri},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {A graph grammar based approach to automated multi-objective analog
circuit design},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {700--705},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090755},
doi = {10.1109/DATE.2009.5090755},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/DasV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SethuramanV09,
author = {Balasubramanian Sethuraman and
Ranga Vemuri},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {A methodology for application-specific NoC architecture generation
in a dynamic task structure environment},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {149--152},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531580},
doi = {10.1145/1531542.1531580},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SethuramanV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XuVJ09,
author = {Hao Xu and
Ranga Vemuri and
Wen{-}Ben Jone},
editor = {Jaijeet S. Roychowdhury},
title = {Temporal and spatial idleness exploitation for optimal-grained leakage
control},
booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009,
San Jose, CA, USA, November 2-5, 2009},
pages = {468--473},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1687399.1687487},
doi = {10.1145/1687399.1687487},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/XuVJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/FernandesV09,
author = {Romana Fernandes and
Ranga Vemuri},
title = {Accurate estimation of vector dependent leakage power in the presence
of process variations},
booktitle = {27th International Conference on Computer Design, {ICCD} 2009, Lake
Tahoe, CA, USA, October 4-7, 2009},
pages = {451--458},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ICCD.2009.5413116},
doi = {10.1109/ICCD.2009.5413116},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/FernandesV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PradhanV09,
author = {Almitra Pradhan and
Ranga Vemuri},
title = {Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface
for Analog Circuits},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {131--136},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.67},
doi = {10.1109/VLSI.DESIGN.2009.67},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PradhanV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BasuKV09,
author = {Shubhankar Basu and
Balaji Kommineni and
Ranga Vemuri},
title = {Variation-Aware Macromodeling and Synthesis of Analog Circuits Using
Spline Center and Range Method and Dynamically Reduced Design Space},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {433--438},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.51},
doi = {10.1109/VLSI.DESIGN.2009.51},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BasuKV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DasV09,
author = {Angan Das and
Ranga Vemuri},
title = {Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated
Analog Circuit Design},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {445--450},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.79},
doi = {10.1109/VLSI.DESIGN.2009.79},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DasV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DasV08,
author = {Angan Das and
Ranga Vemuri},
editor = {Limor Fix},
title = {Topology synthesis of analog circuits based on adaptively generated
building blocks},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {44--49},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391483},
doi = {10.1145/1391469.1391483},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DasV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PradhanV08,
author = {Almitra Pradhan and
Ranga Vemuri},
editor = {Donatella Sciuto},
title = {Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor
Searches},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {523--526},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484903},
doi = {10.1109/DATE.2008.4484903},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PradhanV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/evoW/DasV08,
author = {Angan Das and
Ranga Vemuri},
editor = {Mario Giacobini and
Anthony Brabazon and
Stefano Cagnoni and
Gianni Di Caro and
Rolf Drechsler and
Anik{\'{o}} Ek{\'{a}}rt and
Anna Esparcia{-}Alc{\'{a}}zar and
Muddassar Farooq and
Andreas Fink and
Jon McCormack and
Michael O'Neill and
Juan Romero and
Franz Rothlauf and
Giovanni Squillero and
Sima Uyar and
Shengxiang Yang},
title = {A Self-learning Optimization Technique for Topology Design of Computer
Networks},
booktitle = {Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET,
EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog,
Naples, Italy, March 26-28, 2008. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4974},
pages = {38--51},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-78761-7\_5},
doi = {10.1007/978-3-540-78761-7\_5},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/DasV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PradhanV08,
author = {Almitra Pradhan and
Ranga Vemuri},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {A layout-aware analog synthesis procedure inclusive of dynamic module
geometry selection},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {159--162},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366150},
doi = {10.1145/1366110.1366150},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/PradhanV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XuJV08,
author = {Hao Xu and
Wen{-}Ben Jone and
Ranga Vemuri},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Accurate energy breakeven time estimation for run-time power gating},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {161--168},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681568},
doi = {10.1109/ICCAD.2008.4681568},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/XuJV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/XuVJ08,
author = {Hao Xu and
Ranga Vemuri and
Wen{-}Ben Jone},
title = {Run-time Active Leakage Reduction by power gating and reverse body
biasing: An eNERGY vIEW},
booktitle = {26th International Conference on Computer Design, {ICCD} 2008, 12-15
October 2008, Lake Tahoe, CA, USA, Proceedings},
pages = {618--625},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCD.2008.4751925},
doi = {10.1109/ICCD.2008.4751925},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/XuVJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DasV08,
author = {Angan Das and
Ranga Vemuri},
title = {{ATLAS:} An adaptively formed hierarchical cell library based analog
synthesis framework},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {2542--2545},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4541974},
doi = {10.1109/ISCAS.2008.4541974},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DasV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/XuVJ08,
author = {Hao Xu and
Ranga Vemuri and
Wen{-}Ben Jone},
editor = {Vijaykrishnan Narayanan and
C. P. Ravikumar and
J{\"{o}}rg Henkel and
Ali Keshavarzi and
Vojin G. Oklobdzija and
Barry M. Pangrle},
title = {Dynamic virtual ground voltage estimation for power gating},
booktitle = {Proceedings of the 2008 International Symposium on Low Power Electronics
and Design, 2008, Bangalore, India, August 11-13, 2008},
pages = {27--32},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1393921.1393934},
doi = {10.1145/1393921.1393934},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/XuVJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/BasuKV08,
author = {Shubhankar Basu and
Balaji Kommineni and
Ranga Vemuri},
title = {Variation Aware Spline Center and Range Modeling for Analog Circuit
Performance},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {162--167},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479719},
doi = {10.1109/ISQED.2008.4479719},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/BasuKV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BasuKV08,
author = {Shubhankar Basu and
Balaji Kommineni and
Ranga Vemuri},
title = {Mismatch Aware Analog Performance Macromodeling Using Spline Center
and Range Regression on Adaptive Samples},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {287--293},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.76},
doi = {10.1109/VLSI.2008.76},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BasuKV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PradhanV08,
author = {Almitra Pradhan and
Ranga Vemuri},
title = {On the Use of Hash Tables for Efficient Analog Circuit Synthesis},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {647--652},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.35},
doi = {10.1109/VLSI.2008.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PradhanV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/RammohanSV08,
author = {Srividhya Rammohan and
Vijay Sundaresan and
Ranga Vemuri},
title = {Reduced Complementary Dynamic and Differential Logic: {A} {CMOS} Logic
Style for DPA-Resistant Secure {IC} Design},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {699--705},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.77},
doi = {10.1109/VLSI.2008.77},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/RammohanSV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SethuramanV07,
author = {Balasubramanian Sethuraman and
Ranga Vemuri},
title = {Power variations of multi-port routers in an application-specific
NoC design : {A} case study},
booktitle = {25th International Conference on Computer Design, {ICCD} 2007, 7-10
October 2007, Lake Tahoe, CA, USA, Proceedings},
pages = {595--600},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ICCD.2007.4601958},
doi = {10.1109/ICCD.2007.4601958},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SethuramanV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icmla/KommineniBV07,
author = {Balaji Kommineni and
Shubhankar Basu and
Ranga Vemuri},
editor = {M. Arif Wani and
Mehmed M. Kantardzic and
Tao Li and
Ying Liu and
Lukasz A. Kurgan and
Jieping Ye and
Mitsunori Ogihara and
Seref Sagiroglu and
Xue{-}wen Chen and
Leif E. Peterson and
Khalid Hafeez},
title = {A spline based regression technique on interval valued noisy data},
booktitle = {The Sixth International Conference on Machine Learning and Applications,
{ICMLA} 2007, Cincinnati, Ohio, USA, 13-15 December 2007},
pages = {241--247},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICMLA.2007.100},
doi = {10.1109/ICMLA.2007.100},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icmla/KommineniBV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DasV07,
author = {Angan Das and
Ranga Vemuri},
title = {{GAPSYS:} {A} GA-based Tool for Automated Passive Analog Circuit Synthesis},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {2702--2705},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378519},
doi = {10.1109/ISCAS.2007.378519},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DasV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SethuramanV07,
author = {Balasubramanian Sethuraman and
Ranga Vemuri},
editor = {Diana Marculescu and
Anand Raghunathan and
Ali Keshavarzi and
Vijaykrishnan Narayanan},
title = {Multicasting based topology generation and core mapping for a power
efficient networks-on-chip},
booktitle = {Proceedings of the 2007 International Symposium on Low Power Electronics
and Design, 2007, Portland, OR, USA, August 27-29, 2007},
pages = {399--402},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1283780.1283868},
doi = {10.1145/1283780.1283868},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/SethuramanV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/BasuTV07,
author = {Shubhankar Basu and
Priyanka Thakore and
Ranga Vemuri},
title = {Process Variation Tolerant Standard Cell Library Development Using
Reduced Dimension Statistical Modeling and Optimization Techniques},
booktitle = {8th International Symposium on Quality of Electronic Design {(ISQED}
2007), 26-28 March 2007, San Jose, CA, {USA}},
pages = {814--820},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISQED.2007.125},
doi = {10.1109/ISQED.2007.125},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/BasuTV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/DasV07,
author = {Angan Das and
Ranga Vemuri},
title = {An Automated Passive Analog Circuit Synthesis Framework using Genetic
Algorithms},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {145--152},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.22},
doi = {10.1109/ISVLSI.2007.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/DasV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/BasuV07,
author = {Shubhankar Basu and
Ranga Vemuri},
title = {Process Variation and {NBTI} Tolerant Standard Cells to Improve Parametric
Yield and Lifetime of ICs},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {291--298},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.85},
doi = {10.1109/ISVLSI.2007.85},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/BasuV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PradhanV07a,
author = {Almitra Pradhan and
Ranga Vemuri},
title = {Accurate Performance Estimation using Circuit Matrix Models in Analog
Circuit Synthesis},
booktitle = {VLSI-SoC: Advanced Topics on Systems on a Chip - {A} Selection of
Extended Versions of the Best Papers of the Fourteenth International
Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007),
October 15-17, 2007, Atlanta, {USA}},
series = {{IFIP}},
volume = {291},
pages = {1--20},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-0-387-89558-1\_8},
doi = {10.1007/978-0-387-89558-1\_8},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PradhanV07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SundaresanRV07,
author = {Vijay Sundaresan and
Srividhya Rammohan and
Ranga Vemuri},
title = {Power invariant secure {IC} design methodology using reduced complementary
dynamic and differential logic},
booktitle = {{IFIP} VLSI-SoC 2007, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA,
15-17 October 2007},
pages = {1--6},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/VLSISOC.2007.4402463},
doi = {10.1109/VLSISOC.2007.4402463},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SundaresanRV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PradhanV07,
author = {Almitra Pradhan and
Ranga Vemuri},
title = {Regression based circuit matrix models for accurate performance estimation
of analog circuits},
booktitle = {{IFIP} VLSI-SoC 2007, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA,
15-17 October 2007},
pages = {48--53},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/VLSISOC.2007.4402471},
doi = {10.1109/VLSISOC.2007.4402471},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PradhanV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/YangV07,
author = {Huiying Yang and
Ranga Vemuri},
title = {Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization
in Layout Aware Analog Circuit Synthesis},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {201--206},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.72},
doi = {10.1109/VLSID.2007.72},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/YangV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SethuramanV07,
author = {Balasubramanian Sethuraman and
Ranga Vemuri},
title = {A Force-directed Approach for Fast Generation of Efficient Multi-Port
NoC Architectures},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {419--426},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.12},
doi = {10.1109/VLSID.2007.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SethuramanV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4717,
author = {Raoul F. Badaoui and
Ranga Vemuri},
title = {Multi-Placement Structures for Fast and Optimized Placement in Analog
Circuit Synthesis},
journal = {CoRR},
volume = {abs/0710.4717},
year = {2007},
url = {http://arxiv.org/abs/0710.4717},
eprinttype = {arXiv},
eprint = {0710.4717},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4717.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4752,
author = {Jawad Khan and
Ranga Vemuri},
title = {An Iterative Algorithm for Battery-Aware Task Scheduling on Portable
Computing Platforms},
journal = {CoRR},
volume = {abs/0710.4752},
year = {2007},
url = {http://arxiv.org/abs/0710.4752},
eprinttype = {arXiv},
eprint = {0710.4752},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4752.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DhanwadaDNV06,
author = {Nagu R. Dhanwada and
Alex Doboli and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {Hierarchical constraint transformation based on genetic optimization
for analog system synthesis},
journal = {Integr.},
volume = {39},
number = {3},
pages = {267--290},
year = {2006},
url = {https://doi.org/10.1016/j.vlsi.2005.07.003},
doi = {10.1016/J.VLSI.2005.07.003},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/DhanwadaDNV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanV06,
author = {Jawad Khan and
Ranga Vemuri},
title = {Energy management for battery-powered reconfigurable computing platforms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {2},
pages = {135--147},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2005.863757},
doi = {10.1109/TVLSI.2005.863757},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YangV06,
author = {Huiying Yang and
Ranga Vemuri},
editor = {Georges G. E. Gielen},
title = {Efficient temperature-dependent symbolic sensitivity analysis and
symbolic performance evaluation in analog circuit synthesis},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {283--284},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244139},
doi = {10.1109/DATE.2006.244139},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/YangV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SethuramanV06,
author = {Balasubramanian Sethuraman and
Ranga Vemuri},
editor = {Georges G. E. Gielen},
title = {optiMap: a tool for automated generation of noc architectures using
multi-port routers for FPGAs},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {947--952},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243837},
doi = {10.1109/DATE.2006.243837},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SethuramanV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SethuramanV06,
author = {Balasubramanian Sethuraman and
Ranga Vemuri},
title = {Multi2 Router: {A} Novel Multi Local Port Router Architecture with
Broadcast Facility for FPGA-Based Networks-on-Chip},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--4},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311316},
doi = {10.1109/FPL.2006.311316},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SethuramanV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HuangV06,
author = {Renqiu Huang and
Ranga Vemuri},
editor = {Gang Qu and
Yehea I. Ismail and
Narayanan Vijaykrishnan and
Hai Zhou},
title = {Transformation synthesis for data intensive applications to FPGAs},
booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006,
Philadelphia, PA, USA, April 30 - May 1, 2006},
pages = {349--352},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1127908.1127988},
doi = {10.1145/1127908.1127988},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HuangV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JiaV06,
author = {Xin Jia and
Ranga Vemuri},
editor = {Soha Hassoun},
title = {Studying a {GALS} {FPGA} architecture using a parameterized automatic
design flow},
booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006,
San Jose, CA, USA, November 5-9, 2006},
pages = {688--693},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1233501.1233644},
doi = {10.1145/1233501.1233644},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/JiaV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/RanjanV06,
author = {Mukesh Ranjan and
Ranga Vemuri},
title = {Exact hierarchical symbolic analysis of large analog networks using
a general interconnection template},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692950},
doi = {10.1109/ISCAS.2006.1692950},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/RanjanV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SundaresanV06,
author = {Vijay Sundaresan and
Ranga Vemuri},
title = {A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning},
booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2006), 2-3 March 2006, Karlsruhe, Germany},
pages = {323--328},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISVLSI.2006.8},
doi = {10.1109/ISVLSI.2006.8},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SundaresanV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BhaduriV06,
author = {Amitava Bhaduri and
Ranga Vemuri},
title = {Parasitic Aware Routing Methodology Based on Higher Order {RLCK} Moment
Metrics},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {141--146},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.129},
doi = {10.1109/VLSID.2006.129},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BhaduriV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/JiaV06,
author = {Xin Jia and
Ranga Vemuri},
title = {{CAD} Tools for a Globally Asynchronous Locally Synchronous {FPGA}
Architecture},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {251--256},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.54},
doi = {10.1109/VLSID.2006.54},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/JiaV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DingV06,
author = {Mengmeng Ding and
Ranga Vemuri},
title = {Efficient Analog Performance Macromodeling via Sequential Design Space
Decomposition},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {553--556},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.77},
doi = {10.1109/VLSID.2006.77},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DingV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ChakrabortyRV06,
author = {Ritochit Chakraborty and
Mukesh Ranjan and
Ranga Vemuri},
title = {Symbolic Time-Domain Behavioral and Performance Modeling of Linear
Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm
for Pole Extraction},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {689--694},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.153},
doi = {10.1109/VLSID.2006.153},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ChakrabortyRV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijes/HandaV05,
author = {Manish Handa and
Ranga Vemuri},
title = {Hardware assisted two dimensional ultra fast online placement},
journal = {Int. J. Embed. Syst.},
volume = {1},
number = {3/4},
pages = {291--299},
year = {2005},
url = {https://doi.org/10.1504/IJES.2005.009957},
doi = {10.1504/IJES.2005.009957},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijes/HandaV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YangRVDVG05,
author = {Huiying Yang and
Mukesh Ranjan and
Wim Verhaegen and
Mengmeng Ding and
Ranga Vemuri and
Georges G. E. Gielen},
editor = {Tingao Tang},
title = {Efficient symbolic sensitivity analysis of analog circuits using element-coefficient
diagrams},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {230--235},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120812},
doi = {10.1145/1120725.1120812},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YangRVDVG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DingWV05,
author = {Mengmeng Ding and
Glenn Wolfe and
Ranga Vemuri},
editor = {Tingao Tang},
title = {An error-driven adaptive grid refinement algorithm for automatic generation
of analog circuit performance macromodels},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {477--482},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120916},
doi = {10.1145/1120725.1120916},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/DingWV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JiaV05,
author = {Xin Jia and
Ranga Vemuri},
editor = {Tingao Tang},
title = {Using {GALS} architecture to reduce the impact of long wire delay
on {FPGA} performance},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {1260--1263},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1121038},
doi = {10.1145/1120725.1121038},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JiaV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DingV05,
author = {Mengmeng Ding and
Ranga Vemuri},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {A combined feasibility and performance macromodel for analog circuits},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {63--68},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065600},
doi = {10.1145/1065579.1065600},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DingV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BadaouiV05,
author = {Raoul F. Badaoui and
Ranga Vemuri},
title = {Multi-Placement Structures for Fast and Optimized Placement in Analog
Circuit Synthesis},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {138--143},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.216},
doi = {10.1109/DATE.2005.216},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BadaouiV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KhanV05,
author = {Jawad Khan and
Ranga Vemuri},
title = {An Iterative Algorithm for Battery-Aware Task Scheduling on Portable
Computing Platforms},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {622--627},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.62},
doi = {10.1109/DATE.2005.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KhanV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BhaduriV05,
author = {Amitava Bhaduri and
Ranga Vemuri},
title = {Inductive and Capacitive Coupling Aware Routing Methodology Driven
by a Higher Order {RLCK} Moment Metric},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {922--923},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.182},
doi = {10.1109/DATE.2005.182},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BhaduriV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DingV05,
author = {Mengmeng Ding and
Ranga Vemuri},
title = {A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {1088--1089},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.43},
doi = {10.1109/DATE.2005.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DingV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/JiaV05,
author = {Xin Jia and
Ranga Vemuri},
title = {The {GAPLA:} {A} Globally Asynchronous Locally Synchronous {FPGA}
Architecture},
booktitle = {13th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} 2005), 17-20 April 2005, Napa, CA, USA, Proceedings},
pages = {291--292},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/FCCM.2005.64},
doi = {10.1109/FCCM.2005.64},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/JiaV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/JiaV05,
author = {Xin Jia and
Ranga Vemuri},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {A Novel Asynchronous {FPGA} Architecture Design and Its Performance
Evaluation},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {287--292},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515736},
doi = {10.1109/FPL.2005.1515736},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/JiaV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KhanV05,
author = {Jawad Khan and
Ranga Vemuri},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {Energy Management in Battery-Powered Sensor Networks with Reconfigurable
Computing Nodes},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {543--546},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515781},
doi = {10.1109/FPL.2005.1515781},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KhanV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HuangV05,
author = {Renqiu Huang and
Ranga Vemuri},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {{PAHLS:} Towards Run-Time Synthesis for FPGAs},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {739--740},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515833},
doi = {10.1109/FPL.2005.1515833},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/HuangV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BhaduriV05,
author = {Amitava Bhaduri and
Ranga Vemuri},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {Moment-driven coupling-aware routing methodology},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {390--395},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057754},
doi = {10.1145/1057661.1057754},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/BhaduriV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SethuramanBKV05,
author = {Balasubramanian Sethuraman and
Prasun Bhattacharya and
Jawad Khan and
Ranga Vemuri},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {LiPaR: {A} light-weight parallel router for FPGA-based networks-on-chip},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {452--457},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057769},
doi = {10.1145/1057661.1057769},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SethuramanBKV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AgarwalWV05,
author = {Anuradha Agarwal and
Glenn Wolfe and
Ranga Vemuri},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {Accuracy driven performance macromodeling of feasible regions during
synthesis of analog circuits},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {482--487},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057777},
doi = {10.1145/1057661.1057777},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AgarwalWV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AgarwalV05,
author = {Anuradha Agarwal and
Ranga Vemuri},
title = {Hierarchical performance macromodels of feasible regions for synthesis
of analog and {RF} circuits},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {430--436},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560106},
doi = {10.1109/ICCAD.2005.1560106},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AgarwalV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/AgarwalV05,
author = {Anuradha Agarwal and
Ranga Vemuri},
title = {Layout-Aware {RF} Circuit Synthesis Driven by Worst Case Parasitic
Corners},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {444--452},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.68},
doi = {10.1109/ICCD.2005.68},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/AgarwalV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/KhanV05,
author = {Jawad Khan and
Ranga Vemuri},
title = {Battery-Efficient Task Execution on Reconfigurable Computing Platforms
with Multiple Processing Units},
booktitle = {19th International Parallel and Distributed Processing Symposium {(IPDPS}
2005), {CD-ROM} / Abstracts Proceedings, 4-8 April 2005, Denver, CO,
{USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/IPDPS.2005.122},
doi = {10.1109/IPDPS.2005.122},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/KhanV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/BadaouiV05,
author = {Raoul F. Badaoui and
Ranga Vemuri},
title = {Analog {VLSI} circuit-level synthesis using multi-placement structures},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {5978--5981},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1466001},
doi = {10.1109/ISCAS.2005.1466001},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/BadaouiV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YangAV05,
author = {Huiying Yang and
Anuradha Agarwal and
Ranga Vemuri},
title = {Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis
Based on Element-Coefficient Diagrams},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {71--76},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.33},
doi = {10.1109/ISVLSI.2005.33},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YangAV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HuangV05,
author = {Renqiu Huang and
Ranga Vemuri},
title = {Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {250--251},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.68},
doi = {10.1109/ISVLSI.2005.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HuangV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DingV05,
author = {Mengmeng Ding and
Ranga Vemuri},
title = {An Active Learning Scheme Using Support Vector Machines for Analog
Circuit Feasibility Classification},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {528--534},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.47},
doi = {10.1109/ICVD.2005.47},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DingV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MukherjeeV05,
author = {Madhubanti Mukherjee and
Ranga Vemuri},
title = {On Physical-Aware Synthesis of Vertically Integrated 3D Systems},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {647--652},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.129},
doi = {10.1109/ICVD.2005.129},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/MukherjeeV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/HuangV05,
author = {Renqiu Huang and
Ranga Vemuri},
title = {On-Line Synthesis for Partially Reconfigurable FPGAs},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {663--668},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.131},
doi = {10.1109/ICVD.2005.131},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/HuangV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DoboliDNV04,
author = {Alex Doboli and
Nagu R. Dhanwada and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {A two-layer library-based approach to synthesis of analog systems
from {VHDL-AMS} specifications},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {9},
number = {2},
pages = {238--271},
year = {2004},
url = {https://doi.org/10.1145/989995.990000},
doi = {10.1145/989995.990000},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/DoboliDNV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/JiaV04,
author = {Xin Jia and
Ranga Vemuri},
editor = {Hamid R. Arabnia and
Minyi Guo and
Laurence Tianruo Yang},
title = {A Design Methodology for Self-Timed Event Logic Pipelines},
booktitle = {Proceedings of the International Conference on Embedded Systems and
Applications, {ESA} '04 {\&} Proceedings of the International
Conference on VLSI, {VLSI} '04, June 21-24, 2004, Las Vegas, Nevada,
{USA}},
pages = {475--479},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Fri, 04 Mar 2005 11:26:21 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/JiaV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AgarwalSYV04,
author = {Anuradha Agarwal and
Hemanth Sampath and
Veena Yelamanchili and
Ranga Vemuri},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Fast and accurate parasitic capacitance models for layout-aware},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {145--150},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996610},
doi = {10.1145/996566.996610},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AgarwalSYV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HandaV04,
author = {Manish Handa and
Ranga Vemuri},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {An efficient algorithm for finding empty space for online {FPGA} placement},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {960--965},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996820},
doi = {10.1145/996566.996820},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HandaV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RanjanVASVG04,
author = {Mukesh Ranjan and
Wim Verhaegen and
Anuradha Agarwal and
Hemanth Sampath and
Ranga Vemuri and
Georges G. E. Gielen},
title = {Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled
Parasitic-Aware Symbolic Performance Models},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {604--609},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268911},
doi = {10.1109/DATE.2004.1268911},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RanjanVASVG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HandaV04,
author = {Manish Handa and
Ranga Vemuri},
title = {A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic
{FPGA} Placement},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {744--745},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268958},
doi = {10.1109/DATE.2004.1268958},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HandaV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AgarwalSYV04,
author = {Anuradha Agarwal and
Hemanth Sampath and
Veena Yelamanchili and
Ranga Vemuri},
title = {Accurate Estimation of Parasitic Capacitances in Analog Circuits},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {1364--1365},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1269090},
doi = {10.1109/DATE.2004.1269090},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/AgarwalSYV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/KhanSV04,
author = {Jawad Khan and
Balasubramanian Sethuraman and
Ranga Vemuri},
editor = {Toomas P. Plaks},
title = {A Power-Performance Trade-off Methodology for Portable Reconfigurable
Platforms},
booktitle = {Proceedings of the International Conference on Engineering of Reconfigurable
Systems and Algorithms, ERSA'04, June 21-24, 2004, Las Vegas, Nevada,
{USA}},
pages = {33--37},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Fri, 19 Nov 2004 09:19:54 +0100},
biburl = {https://dblp.org/rec/conf/ersa/KhanSV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/HandaV04,
author = {Manish Handa and
Ranga Vemuri},
editor = {Toomas P. Plaks},
title = {Area Fragmentation in Reconfigurable Operating Systems},
booktitle = {Proceedings of the International Conference on Engineering of Reconfigurable
Systems and Algorithms, ERSA'04, June 21-24, 2004, Las Vegas, Nevada,
{USA}},
pages = {77--83},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Fri, 19 Nov 2004 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/HandaV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/KhanRHV04,
author = {Jawad Khan and
Jayanthi Rajagopalan and
Renqiu Huang and
Ranga Vemuri},
editor = {Toomas P. Plaks},
title = {A Portable Face Recognition System Using Reconfigurable Hardware},
booktitle = {Proceedings of the International Conference on Engineering of Reconfigurable
Systems and Algorithms, ERSA'04, June 21-24, 2004, Las Vegas, Nevada,
{USA}},
pages = {213--217},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Fri, 19 Nov 2004 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/KhanRHV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HandaV04,
author = {Manish Handa and
Ranga Vemuri},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {An Integrated Online Scheduling and Placement Methodology},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {444--453},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_46},
doi = {10.1007/978-3-540-30117-2\_46},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/HandaV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KhanV04,
author = {Jawad Khan and
Ranga Vemuri},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {An Efficient Battery-Aware Task Scheduling Methodology for Portable
{RC} Platforms},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {669--678},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_68},
doi = {10.1007/978-3-540-30117-2\_68},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KhanV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/JiaRV04,
author = {Xin Jia and
Jayanthi Rajagopalan and
Ranga Vemuri},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {A Dynamically Reconfigurable Asynchronous {FPGA} Architecture},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {836--841},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_85},
doi = {10.1007/978-3-540-30117-2\_85},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/JiaRV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HuangHV04,
author = {Renqiu Huang and
Manish Handa and
Ranga Vemuri},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable
FPGAs},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {900--905},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_96},
doi = {10.1007/978-3-540-30117-2\_96},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/HuangHV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BadaouiSAV04,
author = {Raoul F. Badaoui and
Hemanth Sampath and
Anuradha Agarwal and
Ranga Vemuri},
editor = {David Garrett and
John C. Lach and
Charles A. Zukowski},
title = {A high level language for pre-layout extraction in parasite-aware
analog circuit synthesis},
booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
Boston, MA, USA, April 26-28, 2004},
pages = {271--276},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/988952.989018},
doi = {10.1145/988952.989018},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/BadaouiSAV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuangV04,
author = {Renqiu Huang and
Ranga Vemuri},
title = {Analysis and evaluation of a hybrid interconnect structure for FPGAs},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {595--601},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382646},
doi = {10.1109/ICCAD.2004.1382646},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HuangV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/VemuriW04,
author = {Ranga Vemuri and
Glenn Wolfe},
title = {Adaptive sampling and modeling of analog circuit performance parameters
with pseudo-cubic splines},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {931--938},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382709},
doi = {10.1109/ICCAD.2004.1382709},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/VemuriW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MukherjeeV04,
author = {Madhubanti Mukherjee and
Ranga Vemuri},
title = {Simultaneous Scheduling, Binding and Layer Assignment for Synthesis
of Vertically Integrated 3D Systems},
booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
Jose, CA, USA, Proceedings},
pages = {222--227},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICCD.2004.1347926},
doi = {10.1109/ICCD.2004.1347926},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MukherjeeV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/HandaV04,
author = {Manish Handa and
Ranga Vemuri},
title = {Hardware Assisted Two Dimensional Ultra Fast Placement},
booktitle = {18th International Parallel and Distributed Processing Symposium {(IPDPS}
2004), {CD-ROM} / Abstracts Proceedings, 26-30 April 2004, Santa Fe,
New Mexico, {USA}},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/IPDPS.2004.1303117},
doi = {10.1109/IPDPS.2004.1303117},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/HandaV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/HuangV04,
author = {Renqiu Huang and
Ranga Vemuri},
title = {Forward-Looking Macro Generation and Relational Placement During High
Level Synthesis to FPGAs},
booktitle = {18th International Parallel and Distributed Processing Symposium {(IPDPS}
2004), {CD-ROM} / Abstracts Proceedings, 26-30 April 2004, Santa Fe,
New Mexico, {USA}},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/IPDPS.2004.1303114},
doi = {10.1109/IPDPS.2004.1303114},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/HuangV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/SethuramanKV04,
author = {Balasubramanian Sethuraman and
Jawad Khan and
Ranga Vemuri},
title = {Battery-efficient task execution on portable reconfigurable computing},
booktitle = {Proceedings 2004 {IEEE} International {SOC} Conference, September
12-15, 2004, Hilton Santa Clara, CA, {USA}},
pages = {237--240},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/SOCC.2004.1362420},
doi = {10.1109/SOCC.2004.1362420},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/SethuramanKV04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WolfeV03,
author = {Glenn Wolfe and
Ranga Vemuri},
title = {Extraction and use of neural network models in automated synthesis
of operational amplifiers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {2},
pages = {198--212},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2002.806600},
doi = {10.1109/TCAD.2002.806600},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WolfeV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DoboliV03,
author = {Alex Doboli and
Ranga Vemuri},
title = {Behavioral modeling for high-level synthesis of analog and mixed-signal
systems from {VHDL-AMS}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {11},
pages = {1504--1520},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.818302},
doi = {10.1109/TCAD.2003.818302},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DoboliV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DoboliV03a,
author = {Alex Doboli and
Ranga Vemuri},
title = {Exploration-based high-level synthesis of linear analog systems operating
at low/medium frequencies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {11},
pages = {1556--1568},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.818374},
doi = {10.1109/TCAD.2003.818374},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DoboliV03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MukherjeeV03,
author = {Madhubanti Mukherjee and
Ranga Vemuri},
title = {A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit
Reduction for Application Specific {DSP} Circuits},
booktitle = {21st International Conference on Computer Design {(ICCD} 2003),VLSI
in Computers and Processors, 13-15 October 2003, San Jose, CA, USA,
Proceedings},
pages = {436--440},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICCD.2003.1240936},
doi = {10.1109/ICCD.2003.1240936},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MukherjeeV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WolfeDV03,
author = {Glenn Wolfe and
Mengmeng Ding and
Ranga Vemuri},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {Adaptive Sampling and Modeling of Analog Circuit Performance Parameters},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {142},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Thu, 07 Oct 2004 09:29:26 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WolfeDV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SampathV03,
author = {Hemanth Sampath and
Ranga Vemuri},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {{MSL:} {A} High-Level Language for Parameterized Analog and Mixed
Signal Layout Generators},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {416--421},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Thu, 22 Jan 2004 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SampathV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/HandaRMV03,
author = {Manish Handa and
Rajesh Radhakrishnan and
Madhubanti Mukherjee and
Ranga Vemuri},
title = {A Fast Macro Based Compilation Methodology for Partially Reconfigurable
{FPGA} Designs},
booktitle = {16th International Conference on {VLSI} Design {(VLSI} Design 2003),
4-8 January 2003, New Delhi, India},
pages = {91},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICVD.2003.1183120},
doi = {10.1109/ICVD.2003.1183120},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/HandaRMV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/VemuriKKR02,
author = {Ranga Vemuri and
Srinivas Katkoori and
Meenakshi Kaul and
Jay Roy},
title = {An efficient register optimization algorithm for high-level synthesis
from hierarchical behavioral specifications},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {7},
number = {1},
pages = {189--216},
year = {2002},
url = {https://doi.org/10.1145/504914.504923},
doi = {10.1145/504914.504923},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/VemuriKKR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChathaV02,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {Hardware-software partitioning and pipelined scheduling of transformative
applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {193--208},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043323},
doi = {10.1109/TVLSI.2002.1043323},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChathaV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DoboliV02,
author = {Alex Doboli and
Ranga Vemuri},
title = {A Functional Specification Notation for Co-Design of Mixed Analog-Digital
Systems},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {760--767},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998384},
doi = {10.1109/DATE.2002.998384},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DoboliV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KhanHV02,
author = {Jawad Khan and
Manish Handa and
Ranga Vemuri},
editor = {Manfred Glesner and
Peter Zipf and
Michel Renovell},
title = {iPACE-V1: {A} Portable Adaptive Computing Engine for Real Time Applications},
booktitle = {Field-Programmable Logic and Applications, Reconfigurable Computing
Is Going Mainstream, 12th International Conference, {FPL} 2002, Montpellier,
France, September 2-4, 2002, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2438},
pages = {69--78},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-46117-5\_9},
doi = {10.1007/3-540-46117-5\_9},
timestamp = {Sat, 30 Sep 2023 09:41:27 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KhanHV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DasasathyanRV02,
author = {Srinivasan Dasasathyan and
Rajesh Radhakrishnan and
Ranga Vemuri},
title = {Framework for Synthesis of Virtual Pipelines},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {326--331},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.994943},
doi = {10.1109/ASPDAC.2002.994943},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DasasathyanRV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/NarasimhanTRGV01,
author = {Naren Narasimhan and
Elena Teica and
Rajesh Radhakrishnan and
Sriram Govindarajan and
Ranga Vemuri},
title = {Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained
Scheduler for High-Level Synthesis},
journal = {Formal Methods Syst. Des.},
volume = {19},
number = {3},
pages = {237--273},
year = {2001},
url = {https://doi.org/10.1023/A:1011250531814},
doi = {10.1023/A:1011250531814},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/fmsd/NarasimhanTRGV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VemuriG01,
author = {Ranga Vemuri and
Rajesh K. Gupta},
title = {Guest editorial reconfigurable and adaptive {VLSI} systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {1},
pages = {107--108},
year = {2001},
url = {https://doi.org/10.1109/TVLSI.2001.920825},
doi = {10.1109/TVLSI.2001.920825},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VemuriG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrinivasanGV01,
author = {V. Srinivasan and
Sriram Govindarajan and
Ranga Vemuri},
title = {Fine-grained and coarse-grained behavioral partitioning with effective
utilization of memory and design space exploration for multi-FPGA
architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {1},
pages = {140--158},
year = {2001},
url = {https://doi.org/10.1109/92.920829},
doi = {10.1109/92.920829},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SrinivasanGV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arvlsi/GanesanV01,
author = {Sree Ganesan and
Ranga Vemuri},
title = {Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems},
booktitle = {19th Conference on Advanced Research in {VLSI} {(ARVLSI} 2001), 14-16
March 2001, Salt Lake City, UT, {USA}},
pages = {172--187},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ARVLSI.2001.915559},
doi = {10.1109/ARVLSI.2001.915559},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arvlsi/GanesanV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/charme/RadhakrishnanTV01,
author = {Rajesh Radhakrishnan and
Elena Teica and
Ranga Vemuri},
editor = {Tiziana Margaria and
Thomas F. Melham},
title = {Verification of Basic Block Schedules Using {RTL} Transformations},
booktitle = {Correct Hardware Design and Verification Methods, 11th {IFIP} {WG}
10.5 Advanced Research Working Conference, {CHARME} 2001, Livingston,
Scotland, UK, September 4-7, 2001, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2144},
pages = {173--178},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/3-540-44798-9\_16},
doi = {10.1007/3-540-44798-9\_16},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/charme/RadhakrishnanTV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ChathaV01,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Jan Madsen and
J{\"{o}}rg Henkel and
Xiaobo Sharon Hu},
title = {{MAGELLAN:} multiway hardware-software partitioning and scheduling
for latency minimization of hierarchical control-dataflow task graphs},
booktitle = {Proceedings of the Ninth International Symposium on Hardware/Software
Codesign, {CODES} 2001, Copenhagen, Denmark, 2001},
pages = {42--47},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/371636.371671},
doi = {10.1145/371636.371671},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/ChathaV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GanesanV01,
author = {Sree Ganesan and
Ranga Vemuri},
title = {Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {133--138},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378373},
doi = {10.1145/378239.378373},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/GanesanV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DoboliV01,
author = {Alex Doboli and
Ranga Vemuri},
title = {Integrated High-Level Synthesis and Power-Net Routing for Digital
Design under Switching Noise Constraints},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {629--634},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.379037},
doi = {10.1145/378239.379037},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DoboliV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/OuaissV01,
author = {Iyad Ouaiss and
Ranga Vemuri},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {Hierarchical memory mapping during synthesis in FPGA-based reconfigurable
computers},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {650--657},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915092},
doi = {10.1109/DATE.2001.915092},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/OuaissV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TeicaRV01,
author = {Elena Teica and
Rajesh Radhakrishnan and
Ranga Vemuri},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {On the verification of synthesized designs using automatically generated
transformational witnesses},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {798},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915123},
doi = {10.1109/DATE.2001.915123},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/TeicaRV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DoboliV01,
author = {Alex Doboli and
Ranga Vemuri},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {A regularity-based hierarchical symbolic analysis method for large-scale
analog networks},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {806},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915132},
doi = {10.1109/DATE.2001.915132},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DoboliV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KasatOV01,
author = {Amit Kasat and
Iyad Ouaiss and
Ranga Vemuri},
editor = {Gordon J. Brebner and
Roger F. Woods},
title = {Memory Synthesis for FPGA-Based Reconfigurable Computers},
booktitle = {Field-Programmable Logic and Applications, 11th International Conference,
{FPL} 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2147},
pages = {70--80},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/3-540-44687-7\_8},
doi = {10.1007/3-540-44687-7\_8},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KasatOV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/PanLV01,
author = {Yi Pan and
Jie Li and
Ranga Vemuri},
title = {Continous Wavelet Transform on Reconfigurable Meshes},
booktitle = {Proceedings of the 15th International Parallel {\&} Distributed
Processing Symposium (IPDPS-01), San Francisco, CA, USA, April 23-27,
2001},
pages = {114},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/IPDPS.2001.925087},
doi = {10.1109/IPDPS.2001.925087},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/PanLV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/OuaissV01,
author = {Iyad Ouaiss and
Ranga Vemuri},
title = {Global memory mapping for FPGA-based reconfigurable systems},
booktitle = {Proceedings of the 15th International Parallel {\&} Distributed
Processing Symposium (IPDPS-01), San Francisco, CA, USA, April 23-27,
2001},
pages = {144},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/IPDPS.2001.925131},
doi = {10.1109/IPDPS.2001.925131},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/OuaissV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DoboliV01,
author = {Alex Doboli and
Ranga Vemuri},
title = {Hierarchical performance optimization for synthesis of linear analog
systems},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {431--434},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.922077},
doi = {10.1109/ISCAS.2001.922077},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DoboliV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GanesanV01,
author = {Sree Ganesan and
Ranga Vemuri},
title = {Library Binding for High-Level Synthesis of Analog Systems},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {261--268},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902671},
doi = {10.1109/ICVD.2001.902671},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GanesanV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SundararamanGV01,
author = {Sujatha Sundararaman and
Sriram Govindarajan and
Ranga Vemuri},
title = {Application Specific Macro Based Synthesis},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {317},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902679},
doi = {10.1109/ICVD.2001.902679},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SundararamanGV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/VemuriH00,
author = {Ranga Vemuri and
Randolph E. Harr},
title = {Configurable Computing: Technology and Applications - Guest Editors'
Introduction},
journal = {Computer},
volume = {33},
number = {4},
pages = {39--40},
year = {2000},
url = {https://doi.org/10.1109/MC.2000.839319},
doi = {10.1109/MC.2000.839319},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/VemuriH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/ChathaV00,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {An Iterative Algorithm for Hardware-Software Partitioning, Hardware
Design Space Exploration and Scheduling},
journal = {Des. Autom. Embed. Syst.},
volume = {5},
number = {3-4},
pages = {281--293},
year = {2000},
url = {https://doi.org/10.1023/A:1008954218909},
doi = {10.1023/A:1008954218909},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/ChathaV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/MansouriV00,
author = {Nazanin Mansouri and
Ranga Vemuri},
title = {Automated Correctness Condition Generation for Formal Verification
of Synthesized {RTL} Designs},
journal = {Formal Methods Syst. Des.},
volume = {16},
number = {1},
pages = {59--91},
year = {2000},
url = {https://doi.org/10.1023/A:1008777509016},
doi = {10.1023/A:1008777509016},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/fmsd/MansouriV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KaulV00,
author = {Meenakshi Kaul and
Ranga Vemuri},
title = {Design-Space Exploration for Block-Processing Based Temporal Partitioning
of Run-Time Reconfigurable Systems},
journal = {J. {VLSI} Signal Process.},
volume = {24},
number = {2-3},
pages = {181--209},
year = {2000},
url = {https://doi.org/10.1023/A:1008193422345},
doi = {10.1023/A:1008193422345},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/KaulV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bmas/DoboliV00,
author = {Alex Doboli and
Ranga Vemuri},
title = {Towards a Specification Notation for High-Level Synthesis of Mixed-Signal
and Analog Systems},
booktitle = {2000 {IEEE/ACM} International Workshop on Behavioral Modeling and
Simulation, {BMAS} 2000, Orlando, Florida, USA, 18-20 October 2000},
pages = {109--116},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/BMAS.2000.888373},
doi = {10.1109/BMAS.2000.888373},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/bmas/DoboliV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GanesanV00,
author = {Sree Ganesan and
Ranga Vemuri},
editor = {Ivo Bolsens},
title = {Technology Mapping and Retargeting for Field-Programmable Analog Arrays},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {58--64},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840016},
doi = {10.1109/DATE.2000.840016},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GanesanV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GanesanV00a,
author = {Satish Ganesan and
Ranga Vemuri},
editor = {Ivo Bolsens},
title = {An Integrated Temporal Partitioning and Partial Reconfiguration Technique
for Design Latency Improvement},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {320--325},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840290},
doi = {10.1109/DATE.2000.840290},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GanesanV00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/OuaissV00,
author = {Iyad Ouaiss and
Ranga Vemuri},
editor = {Ivo Bolsens},
title = {Efficient Resource Arbitration in Reconfigurable Computing Environments},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {560--566},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840841},
doi = {10.1109/DATE.2000.840841},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/OuaissV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GovindarajanV00,
author = {Sriram Govindarajan and
Ranga Vemuri},
editor = {Ivo Bolsens},
title = {Improving the Schedule Quality of Static-List Time-Constrained Scheduling},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {749},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840882},
doi = {10.1109/DATE.2000.840882},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GovindarajanV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/GovindarajanV00,
author = {Sriram Govindarajan and
Ranga Vemuri},
editor = {Reiner W. Hartenstein and
Herbert Gr{\"{u}}nbacher},
title = {Tightly Integrated Design Space Exploration with Spatial and Temporal
Partitioning in {SPARCS}},
booktitle = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable
Computing, 10th International Workshop, {FPL} 2000, Villach, Austria,
August 27-30, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1896},
pages = {7--18},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-44614-1\_2},
doi = {10.1007/3-540-44614-1\_2},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/GovindarajanV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/RadhakrishnanTV00,
author = {Rajesh Radhakrishnan and
Elena Teica and
Ranga Vemuri},
title = {An approach to high-level synthesis system validation using formally
verified transformations},
booktitle = {Proceedings of the {IEEE} International High-Level Design Validation
and Test Workshop 2000, Berkeley, California, USA, November 8-10,
2000},
pages = {80--85},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/HLDVT.2000.889564},
doi = {10.1109/HLDVT.2000.889564},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/RadhakrishnanTV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/LakshmikanthanGSV00,
author = {Preetham Lakshmikanthan and
Sriram Govindarajan and
Vinoo Srinivasan and
Ranga Vemuri},
editor = {Jos{\'{e}} D. P. Rolim},
title = {Behavioral Partitioning with Synthesis for Multi-FPGA Architectures
under Interconnect, Area, and Latency Constraints},
booktitle = {Parallel and Distributed Processing, 15 {IPDPS} 2000 Workshops, Cancun,
Mexico, May 1-5, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1800},
pages = {924--931},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45591-4\_127},
doi = {10.1007/3-540-45591-4\_127},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/LakshmikanthanGSV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KatkooriV00,
author = {Srinivas Katkoori and
Ranga Vemuri},
title = {Scheduling for low power under resource and latency constraints},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {53--56},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.856256},
doi = {10.1109/ISCAS.2000.856256},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/KatkooriV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DoboliDV00,
author = {Alex Doboli and
Nagu R. Dhanwada and
Ranga Vemuri},
title = {A heuristic technique for system-level architecture generation from
signal-flow graph representations of analog systems},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {181--184},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.856026},
doi = {10.1109/ISCAS.2000.856026},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DoboliDV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GhoshV00,
author = {Abhijit Ghosh and
Ranga Vemuri},
title = {Formal Verification of Synthesized Mixed Signal Designs Using *BMDs},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {84},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812589},
doi = {10.1109/ICVD.2000.812589},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GhoshV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GovindarajanSLV00,
author = {Sriram Govindarajan and
Vinoo Srinivasan and
Preetham Lakshmikanthan and
Ranga Vemuri},
title = {A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning
for Multi-Device Architectures},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {212--219},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812611},
doi = {10.1109/ICVD.2000.812611},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GovindarajanSLV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DhanwadaNV99,
author = {Nagu R. Dhanwada and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {Automatic Constraint Transformation with Integrated Parameter Space
Exploration in Analog System Synthesis},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
Wanchai, Hong Kong, China, January 18-21, 1999},
pages = {153--156},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASPDAC.1999.759983},
doi = {10.1109/ASPDAC.1999.759983},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/DhanwadaNV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KaulVGO99,
author = {Meenakshi Kaul and
Ranga Vemuri and
Sriram Govindarajan and
Iyad Ouaiss},
editor = {Mary Jane Irwin},
title = {An Automated Temporal Partitioning and Loop Fission Approach for {FPGA}
Based Reconfigurable Synthesis of {DSP} Applications},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {616--622},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.310010},
doi = {10.1145/309847.310010},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/KaulVGO99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DoboliNDGV99,
author = {Alex Doboli and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Nagu R. Dhanwada and
Sree Ganesan and
Ranga Vemuri},
editor = {Mary Jane Irwin},
title = {Behavioral Synthesis of Analog Systems Using Two-layered Design Space
Exploration},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {951--957},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.310105},
doi = {10.1145/309847.310105},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/DoboliNDGV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KaulV99,
author = {Meenakshi Kaul and
Ranga Vemuri},
title = {Temporal Partitioning combined with Design Space Exploration for Latency
Minimization of Run-Time Reconfigured Designs},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {202--209},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761123},
doi = {10.1109/DATE.1999.761123},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KaulV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MansouriV99,
author = {Nazanin Mansouri and
Ranga Vemuri},
title = {Accounting for Various Register Allocation Schemes During Post-Synthesis
Verification of {RTL} Designs},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {223},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761126},
doi = {10.1109/DATE.1999.761126},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/MansouriV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DhanwadaNV99,
author = {Nagu R. Dhanwada and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {Hierarchical Constraint Transformation Using Directed Interval Search
for Analog System Synthesis},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {328},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761142},
doi = {10.1109/DATE.1999.761142},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DhanwadaNV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DoboliV99,
author = {Alex Doboli and
Ranga Vemuri},
title = {A {VHDL-AMS} Compiler and Architecture Generator for Behavioral Synthesis
of Analog Systems},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {338--345},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761143},
doi = {10.1109/DATE.1999.761143},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DoboliV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Nunez-AldanaV99,
author = {Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {An Analog Performance Estimator for Improving the Effectiveness of
{CMOS} Analog Systems Circuit Synthesis},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {406--411},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761156},
doi = {10.1109/DATE.1999.761156},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/Nunez-AldanaV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/SrinivasanV99,
author = {Vinoo Srinivasan and
Ranga Vemuri},
title = {Task-Level Partitioning and {RTL} Design Space Exploration for Multi-FPGA
Architectures},
booktitle = {7th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} '99), 21-23 April 1999, Napa, CA, {USA}},
pages = {272},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/FPGA.1999.803694},
doi = {10.1109/FPGA.1999.803694},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/SrinivasanV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SrinivasanV99,
author = {Vinoo Srinivasan and
Ranga Vemuri},
editor = {Sinan Kaptanoglu and
Steve Trimberger},
title = {Throughput Optimization with Design Space Exploration During Partitioning
for Multi-FPGA Architectures},
booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium
on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA,
February 21-23, 1999},
pages = {253},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/296399.296527},
doi = {10.1145/296399.296527},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SrinivasanV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ChathaV99,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Patrick Lysaght and
James Irvine and
Reiner W. Hartenstein},
title = {Hardware-Software Codesign for Dynamically Reconfigurable Architectures},
booktitle = {Field-Programmable Logic and Applications, 9th International Workshop,
FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1673},
pages = {175--184},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/978-3-540-48302-1\_18},
doi = {10.1007/978-3-540-48302-1\_18},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ChathaV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GhoshLV99,
author = {Abhijit Ghosh and
Sandeep K. Lodha and
Ranga Vemuri},
title = {Hierarchical Scheduling in High Level Synthesis Using Resource Sharing
Across Nested Loops},
booktitle = {9th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '99), 4-6 March 1999,
Ann Arbor, MI, {USA}},
pages = {140--143},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/GLSV.1999.757396},
doi = {10.1109/GLSV.1999.757396},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GhoshLV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KatkooriV99,
author = {Srinivas Katkoori and
Ranga Vemuri},
title = {Accurate Resource Estimation Algorithms for Behavioral Synthesis},
booktitle = {9th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '99), 4-6 March 1999,
Ann Arbor, MI, {USA}},
pages = {338--339},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/GLSV.1999.757449},
doi = {10.1109/GLSV.1999.757449},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KatkooriV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GhoshV99,
author = {Abhijit Ghosh and
Ranga Vemuri},
title = {Formal Verification of Synthesized Analog Designs},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
{VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
October 10-13, 1999},
pages = {40--45},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCD.1999.808362},
doi = {10.1109/ICCD.1999.808362},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GhoshV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GanesanV99,
author = {Sree Ganesan and
Ranga Vemuri},
title = {A Methodology for Rapid Prototyping of Analog Systems},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
{VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
October 10-13, 1999},
pages = {482--488},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCD.1999.808584},
doi = {10.1109/ICCD.1999.808584},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GanesanV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/DoboliV99,
author = {Alex Doboli and
Ranga Vemuri},
editor = {L. Miguel Silveira and
Srinivas Devadas and
Ricardo Augusto da Luz Reis},
title = {A Decomposition-based Symbolic Analysis Method for Analog Synthesis
from Behavioral Specifications},
booktitle = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International
Conference on Very Large Scale Integration {(VLSI} '99), December
1-4, 1999, Lisbon, Portugal},
series = {{IFIP} Conference Proceedings},
volume = {162},
pages = {305--317},
publisher = {Kluwer},
year = {1999},
timestamp = {Mon, 14 Oct 2002 13:30:59 +0200},
biburl = {https://dblp.org/rec/conf/ifip10-5/DoboliV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/Nunez-AldanaV99,
author = {Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
editor = {L. Miguel Silveira and
Srinivas Devadas and
Ricardo Augusto da Luz Reis},
title = {A Linear Programming Approach for Synthesis of Mixed-Signal Interface
Elements},
booktitle = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International
Conference on Very Large Scale Integration {(VLSI} '99), December
1-4, 1999, Lisbon, Portugal},
series = {{IFIP} Conference Proceedings},
volume = {162},
pages = {318--32},
publisher = {Kluwer},
year = {1999},
timestamp = {Mon, 14 Oct 2002 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ifip10-5/Nunez-AldanaV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/SrinivasanRVW99,
author = {Vinoo Srinivasan and
Shankar Radhakrishnan and
Ranga Vemuri and
Jeffrey Walrath},
editor = {Jos{\'{e}} D. P. Rolim and
Frank Mueller and
Albert Y. Zomaya and
Fikret Er{\c{c}}al and
Stephan Olariu and
Binoy Ravindran and
Jan Gustafsson and
Hiroaki Takada and
Ronald A. Olsson and
Laxmikant V. Kal{\'{e}} and
Peter H. Beckman and
Matthew Haines and
Hossam A. ElGindy and
Denis Caromel and
Serge Chaumette and
Geoffrey C. Fox and
Yi Pan and
Keqin Li and
Tao Yang and
G. Ghiola and
Gianni Conte and
Luigi V. Mancini and
Dominique M{\'{e}}ry and
Beverly A. Sanders and
Devesh Bhatt and
Viktor K. Prasanna},
title = {Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures},
booktitle = {Parallel and Distributed Processing, 11 IPPS/SPDP'99 Workshops Held
in Conjunction with the 13th International Parallel Processing Symposium
and 10th Symposium on Parallel and Distributed Processing, San Juan,
Puerto Rico, USA, April 12-16, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1586},
pages = {588--596},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/BFb0097943},
doi = {10.1007/BFB0097943},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/SrinivasanRVW99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/KaulV99,
author = {Meenakshi Kaul and
Ranga Vemuri},
editor = {Jos{\'{e}} D. P. Rolim and
Frank Mueller and
Albert Y. Zomaya and
Fikret Er{\c{c}}al and
Stephan Olariu and
Binoy Ravindran and
Jan Gustafsson and
Hiroaki Takada and
Ronald A. Olsson and
Laxmikant V. Kal{\'{e}} and
Peter H. Beckman and
Matthew Haines and
Hossam A. ElGindy and
Denis Caromel and
Serge Chaumette and
Geoffrey C. Fox and
Yi Pan and
Keqin Li and
Tao Yang and
G. Ghiola and
Gianni Conte and
Luigi V. Mancini and
Dominique M{\'{e}}ry and
Beverly A. Sanders and
Devesh Bhatt and
Viktor K. Prasanna},
title = {Integrated Block-Processing and Design-Space Exploration in Temporal
Partitioning for {RTR} Architectures},
booktitle = {Parallel and Distributed Processing, 11 IPPS/SPDP'99 Workshops Held
in Conjunction with the 13th International Parallel Processing Symposium
and 10th Symposium on Parallel and Distributed Processing, San Juan,
Puerto Rico, USA, April 12-16, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1586},
pages = {606--615},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/BFb0097945},
doi = {10.1007/BFB0097945},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/KaulV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DhanwadaNV99,
author = {Nagu R. Dhanwada and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {A genetic approach to simultaneous parameter space exploration and
constraint transformation in analog synthesis},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {362--365},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780170},
doi = {10.1109/ISCAS.1999.780170},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DhanwadaNV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/ChathaV99,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {An Iterative Algorithm for Partitioning and Scheduling of Area Constrained
{HW-SW} Systems},
booktitle = {Proceedings of the Tenth {IEEE} International Workshop on Rapid System
Prototyping {(RSP} 1999), Clearwater, Florida, USA, June 16-18, 1999},
pages = {134--139},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/IWRSP.1999.779043},
doi = {10.1109/IWRSP.1999.779043},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/ChathaV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GanesanV99,
author = {Sree Ganesan and
Ranga Vemuri},
title = {{FAAR:} {A} Router for Field-Programmable Analog Arrays},
booktitle = {12th International Conference on {VLSI} Design {(VLSI} Design 1999),
10-13 January 1999, Goa, India},
pages = {556--563},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICVD.1999.745213},
doi = {10.1109/ICVD.1999.745213},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GanesanV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DhanwadaNV99,
author = {Nagu R. Dhanwada and
Adri{\'{a}}n N{\'{u}}{\~{n}}ez{-}Aldana and
Ranga Vemuri},
title = {Component Characterization and Constraint Transformation Based on
Directed Intervals for Analog Synthesis},
booktitle = {12th International Conference on {VLSI} Design {(VLSI} Design 1999),
10-13 January 1999, Goa, India},
pages = {589--596},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICVD.1999.745219},
doi = {10.1109/ICVD.1999.745219},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DhanwadaNV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/KatkooriV98,
author = {Srinivas Katkoori and
Ranga Vemuri},
title = {Architectural Power Estimation Based on Behavior Level Profiling},
journal = {{VLSI} Design},
volume = {7},
number = {3},
pages = {255--270},
year = {1998},
url = {https://doi.org/10.1155/1998/93106},
doi = {10.1155/1998/93106},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/KatkooriV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ChathaV98,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Gaetano Borriello and
Ahmed Amine Jerraya and
Luciano Lavagno},
title = {{RECOD:} a retiming heuristic to optimize resource and memory utilization
in {HW/SW} codesigns},
booktitle = {Proceedings of the Sixth International Workshop on Hardware/Software
Codesign, {CODES} 1998, Seattle, Washington, USA, March 15-18, 1998},
pages = {139--143},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/278241.278324},
doi = {10.1145/278241.278324},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/ChathaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SrinivasanRV98,
author = {Vinoo Srinivasan and
Shankar Radhakrishnan and
Ranga Vemuri},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Hardware Software Partitioning with Integrated Hardware Design Space
Exploration},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {28--35},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655833},
doi = {10.1109/DATE.1998.655833},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SrinivasanRV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KaulV98,
author = {Meenakshi Kaul and
Ranga Vemuri},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {389--396},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655887},
doi = {10.1109/DATE.1998.655887},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KaulV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/GovindarajanOKSV98,
author = {Sriram Govindarajan and
Iyad Ouaiss and
Meenakshi Kaul and
Vinoo Srinivasan and
Ranga Vemuri},
title = {An Effective Design System for Dynamically Reconfigurable Architectures},
booktitle = {6th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} '98), 15-17 April 1998, Napa Valley, CA, {USA}},
pages = {312--313},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/FPGA.1998.707932},
doi = {10.1109/FPGA.1998.707932},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/GovindarajanOKSV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/MansouriV98,
author = {Nazanin Mansouri and
Ranga Vemuri},
editor = {Ganesh Gopalakrishnan and
Phillip J. Windley},
title = {A Methodology for Automated Verification of Synthesized {RTL} Designs
and Its Integration with a High-Level Synthesis Tool},
booktitle = {Formal Methods in Computer-Aided Design, Second International Conference,
{FMCAD} '98, Palo Alto, California, USA, November 4-6, 1998, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1522},
pages = {204--221},
publisher = {Springer},
year = {1998},
url = {https://doi.org/10.1007/3-540-49519-3\_15},
doi = {10.1007/3-540-49519-3\_15},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/MansouriV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ParuthiMV98,
author = {Viresh Paruthi and
Nazanin Mansouri and
Ranga Vemuri},
title = {Automatic data path abstraction for verification of large scale designs},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {192--194},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727044},
doi = {10.1109/ICCD.1998.727044},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ParuthiMV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/NarasimhanTRGV98,
author = {Naren Narasimhan and
Elena Teica and
Rajesh Radhakrishnan and
Sriram Govindarajan and
Ranga Vemuri},
title = {Theorem proving guided development of formal assertions in a resource-constrained
scheduler for high-level synthesis},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {392--399},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727079},
doi = {10.1109/ICCD.1998.727079},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/NarasimhanTRGV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/WalrathV98,
author = {Jeffrey Walrath and
Ranga Vemuri},
editor = {Jos{\'{e}} D. P. Rolim},
title = {A Performance Modeling and Analysis Environment for Reconfigurable
Computers},
booktitle = {Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held
in Conjunction with the 12th International Parallel Processing Symposium
and 9th Symposium on Parallel and Distributed Processing, Orlando,
Florida, USA, March 30 - April 3, 1998, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1388},
pages = {19--24},
publisher = {Springer},
year = {1998},
url = {https://doi.org/10.1007/3-540-64359-1\_667},
doi = {10.1007/3-540-64359-1\_667},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/WalrathV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/OuaissGSKV98,
author = {Iyad Ouaiss and
Sriram Govindarajan and
Vinoo Srinivasan and
Meenakshi Kaul and
Ranga Vemuri},
editor = {Jos{\'{e}} D. P. Rolim},
title = {An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable
Multi-FPGA Architectures},
booktitle = {Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held
in Conjunction with the 12th International Parallel Processing Symposium
and 9th Symposium on Parallel and Distributed Processing, Orlando,
Florida, USA, March 30 - April 3, 1998, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1388},
pages = {31--36},
publisher = {Springer},
year = {1998},
url = {https://doi.org/10.1007/3-540-64359-1\_669},
doi = {10.1007/3-540-64359-1\_669},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ipps/OuaissGSKV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/ChathaV98,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Francky Catthoor},
title = {A Tool for Partitioning and Pipelined Scheduling of Hardware-Software
Systems},
booktitle = {Proceedings of the 11th International Symposium on System Synthesis,
{ISSS} '98, Hsinchu, Taiwan, December 2-4, 1998},
pages = {145--151},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISSS.1998.730616},
doi = {10.1109/ISSS.1998.730616},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/ChathaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/ChathaV98,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {Performance Evaluation Tool for Rapid Prototyping of Hardware-Software
Codesigns},
booktitle = {Proceedings of the Ninth {IEEE} International Workshop on Rapid System
Prototyping {(RSP} 1998), Leuven, Belgium, June 3-5, 1998},
pages = {218--224},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/IWRSP.1998.676695},
doi = {10.1109/IWRSP.1998.676695},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/ChathaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tphol/NarasimhanV98,
author = {Naren Narasimhan and
Ranga Vemuri},
editor = {Jim Grundy and
Malcolm C. Newey},
title = {On the Effectiveness of Theorem Proving Guided Discovery of Formal
Assertions for a Register Allocator in a High-Level Synthesis System},
booktitle = {Theorem Proving in Higher Order Logics, 11th International Conference,
TPHOLs'98, Canberra, Australia, September 27 - October 1, 1998, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1479},
pages = {367--386},
publisher = {Springer},
year = {1998},
url = {https://doi.org/10.1007/BFb0055147},
doi = {10.1007/BFB0055147},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/tphol/NarasimhanV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DhanwadaV98,
author = {Nagu R. Dhanwada and
Ranga Vemuri},
title = {Constraint Allocation in Analog System Synthesis},
booktitle = {11th International Conference on {VLSI} Design {(VLSI} Design 1991),
4-7 January 1998, Chennai, India},
pages = {253--258},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICVD.1998.646613},
doi = {10.1109/ICVD.1998.646613},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DhanwadaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SrinivasanV98,
author = {Vinoo Srinivasan and
Ranga Vemuri},
title = {A Retiming Based Relaxation Heuristic for Resource-Constrained Loop
Pipelining},
booktitle = {11th International Conference on {VLSI} Design {(VLSI} Design 1991),
4-7 January 1998, Chennai, India},
pages = {435--441},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICVD.1998.646646},
doi = {10.1109/ICVD.1998.646646},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SrinivasanV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/VenkateswaranGKBV97,
author = {Natesan Venkateswaran and
Anurag Gupta and
Srinivas Katkoori and
Dinesh Bhatia and
Ranga Vemuri},
title = {A constructive method for data path area estimation during high-level
{VLSI} synthesis},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {509--515},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600319},
doi = {10.1109/ASPDAC.1997.600319},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/VenkateswaranGKBV97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WalrathV97,
author = {Jeffrey Walrath and
Ranga Vemuri},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {Symbolic Evaluation of Performance Models for Tradeoff Visualization},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {359--364},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266168},
doi = {10.1145/266021.266168},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WalrathV97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GovindarajanV97,
author = {Sriram Govindarajan and
Ranga Vemuri},
title = {Cone-based clustering heuristic for list-scheduling algorithms},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {456--462},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582400},
doi = {10.1109/EDTC.1997.582400},
timestamp = {Fri, 20 May 2022 15:59:03 +0200},
biburl = {https://dblp.org/rec/conf/date/GovindarajanV97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WalrathVB97,
author = {Jeffrey Walrath and
Ranga Vemuri and
W. Bradley},
title = {Performance verification using partial evaluation and interval analysis},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {622},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582435},
doi = {10.1109/EDTC.1997.582435},
timestamp = {Fri, 20 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/WalrathVB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GovindarajanV97,
author = {Sriram Govindarajan and
Ranga Vemuri},
title = {Dynamic Bounding of Successor Force Computations in the Force Directed
List Scheduling Algorithms},
booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
October 12-15, 1997},
pages = {752--757},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICCD.1997.628949},
doi = {10.1109/ICCD.1997.628949},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GovindarajanV97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VootukuruVK97,
author = {Madhavi Vootukuru and
Ranga Vemuri and
Nand Kumar},
title = {Resource Constrained {RTL} Partitioning for Synthesis of Multi-FPGA
Designs},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {140--145},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.568066},
doi = {10.1109/ICVD.1997.568066},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VootukuruVK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/VemuriMM96,
author = {Ranga Vemuri and
Ram Manday and
Vijay Meduri},
title = {Performance Modeling Using {PDL}},
journal = {Computer},
volume = {29},
number = {4},
pages = {44--53},
year = {1996},
url = {https://doi.org/10.1109/2.488300},
doi = {10.1109/2.488300},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/VemuriMM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/NarasimhanSVWGV96,
author = {Naren Narasimhan and
Vinoo Srinivasan and
Madhavi Vootukuru and
Jeffrey Walrath and
Sriram Govindarajan and
Ranga Vemuri},
title = {Rapid Prototyping of Reconfigurable Coprocessors},
booktitle = {1996 International Conference on Application-Specific Systems, Architectures,
and Processors {(ASAP} '96), August 19-23, 1996, Chicago, {IL} , {USA}},
pages = {303--312},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ASAP.1996.542825},
doi = {10.1109/ASAP.1996.542825},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/NarasimhanSVWGV96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/SrinivasanKV96,
author = {Vinoo Srinivasan and
Nand Kumar and
Ranga Vemuri},
editor = {Graham Symonds and
Wolfgang Nebel},
title = {Hierarchical behavioral partitioning for multicomponent synthesis},
booktitle = {Proceedings of the conference on European design automation, {EURO-DAC}
'96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996},
pages = {212--217},
publisher = {{IEEE} Computer Society Press},
year = {1996},
url = {https://doi.org/10.1109/EURDAC.1996.558207},
doi = {10.1109/EURDAC.1996.558207},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eurodac/SrinivasanKV96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/NarasimhanV96,
author = {Naren Narasimhan and
Ranga Vemuri},
editor = {Mandayam K. Srivas and
Albert John Camilleri},
title = {Specification of Control Flow Properties for Verification of Synthesized
{VHDL} Designs},
booktitle = {Formal Methods in Computer-Aided Design, First International Conference,
{FMCAD} '96, Palo Alto, California, USA, November 6-8, 1996, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1166},
pages = {327--345},
publisher = {Springer},
year = {1996},
url = {https://doi.org/10.1007/BFb0031819},
doi = {10.1007/BFB0031819},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/NarasimhanV96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KatkooriV96,
author = {Srinivas Katkoori and
Ranga Vemuri},
editor = {Mark Horowitz and
Jan M. Rabaey and
Brock Barton and
Massoud Pedram},
title = {Simulation based architectural power estimation for PLA-based controllers},
booktitle = {Proceedings of the 1996 International Symposium on Low Power Electronics
and Design, 1996, Monterey, California, USA, August 12-14, 1996},
pages = {121--124},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/LPE.1996.547492},
doi = {10.1109/LPE.1996.547492},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KatkooriV96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KatkooriVR96,
author = {Srinivas Katkoori and
Ranga Vemuri and
Jay Roy},
title = {A Hierarchical Register Optimization Algorithm for Behavioral Synthesis},
booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996),
3-6 January 1996, Bangalore, India},
pages = {126--132},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICVD.1996.489471},
doi = {10.1109/ICVD.1996.489471},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KatkooriVR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/NarasimhanVR96,
author = {Naren Narasimhan and
Ranga Vemuri and
Jay Roy},
title = {Synchronous Controller Models for Synthesis from Communicating {VHDL}
Processes},
booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996),
3-6 January 1996, Bangalore, India},
pages = {198--204},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICVD.1996.489484},
doi = {10.1109/ICVD.1996.489484},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/NarasimhanVR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/KumarKRV95,
author = {Nand Kumar and
Srinivas Katkoori and
Leo Rader and
Ranga Vemuri},
title = {Profile-Driven Behavioral Synthesis for Low-Power {VLSI} Systems},
journal = {{IEEE} Des. Test Comput.},
volume = {12},
number = {3},
pages = {70--84},
year = {1995},
url = {https://doi.org/10.1109/MDT.1995.466383},
doi = {10.1109/MDT.1995.466383},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/KumarKRV95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VemuriK95,
author = {Ranga Vemuri and
R. Kalyanaraman},
title = {Generation of design verification tests from behavioral {VHDL} programs
using path enumeration and constraint programming},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {3},
number = {2},
pages = {201--214},
year = {1995},
url = {https://doi.org/10.1109/92.386221},
doi = {10.1109/92.386221},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VemuriK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KatkooriKV95,
author = {Srinivas Katkoori and
Nand Kumar and
Ranga Vemuri},
title = {High level profiling based low power synthesis technique},
booktitle = {1995 International Conference on Computer Design {(ICCD} '95), {VLSI}
in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings},
pages = {446--453},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICCD.1995.528906},
doi = {10.1109/ICCD.1995.528906},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KatkooriKV95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BradleyV95,
author = {William L. Bradley and
Ranga Vemuri},
title = {Transformations for functional verification of synthesized designs},
booktitle = {8th International Conference on {VLSI} Design {(VLSI} Design 1995),
4-7 January 1995, New Delhi, India},
pages = {243--248},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICVD.1995.512117},
doi = {10.1109/ICVD.1995.512117},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BradleyV95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/VemuriKVRSRMMVR93,
author = {Ranga Vemuri and
Nand Kumar and
Raghu Vutukuru and
Prasad Subba Rao and
Praveen Sinha and
Ning Ren and
Paddy Mamtora and
Ram Mandayam and
Ram Vemuri and
Jayanta Roy},
title = {An Integrated Multicomponent Synthesis for MCMs},
journal = {Computer},
volume = {26},
number = {4},
pages = {62--74},
year = {1993},
url = {https://doi.org/10.1109/2.206517},
doi = {10.1109/2.206517},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/VemuriKVRSRMMVR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/chdl/MandayamV93,
author = {Ram Mandayam and
Ranga Vemuri},
editor = {David Agnew and
Luc J. M. Claesen and
Raul Camposano},
title = {Performance Specification and Measurement},
booktitle = {Computer Hardware Description Languages and their Applications, Proceedings
of the 11th {IFIP} {WG10.2} International Conference on Computer Hardware
Description Languages and their Applications - {CHDL} '93, sponsored
by {IFIP} {WG10.2} and in cooperation with {IEEE} COMPSOC, Ottawa,
Ontario, Canada, 26-28 April, 1993},
series = {{IFIP} Transactions},
volume = {{A-32}},
pages = {281--298},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 11:54:34 +0100},
biburl = {https://dblp.org/rec/conf/chdl/MandayamV93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/VemuriMSKRV93,
author = {Ranga Vemuri and
Paddy Mamtora and
Praveen Sinha and
Nand Kumar and
Jayanta Roy and
Raghu Vutukuru},
editor = {Alfred E. Dunlop},
title = {Experiences in Functional Validation of a High Level Synthesis System},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {194--201},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.164667},
doi = {10.1145/157485.164667},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/VemuriMSKRV93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MandayamV93,
author = {Ram Mandayam and
Ranga Vemuri},
editor = {Alfred E. Dunlop},
title = {Performance Specification Using Attributed Grammars},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {661--667},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.165085},
doi = {10.1145/157485.165085},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MandayamV93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/RoyKDV92,
author = {Jayanta Roy and
Nand Kumar and
Rajiv Dutta and
Ranga Vemuri},
title = {{DSS:} {A} Distributed High-Level Synthesis System},
journal = {{IEEE} Des. Test Comput.},
volume = {9},
number = {2},
pages = {18--32},
year = {1992},
url = {https://doi.org/10.1109/54.143143},
doi = {10.1109/54.143143},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/RoyKDV92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DuttaRV92,
author = {Rajiv Dutta and
Jayanta Roy and
Ranga Vemuri},
editor = {Daniel G. Schweikert},
title = {Distributed Design-Space Exploration for High-Level Synthesis Systems},
booktitle = {Proceedings of the 29th Design Automation Conference, Anaheim, California,
USA, June 8-12, 1992},
pages = {644--650},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {http://portal.acm.org/citation.cfm?id=113938.149651},
timestamp = {Thu, 16 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DuttaRV92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/KumarV92,
author = {Nand Kumar and
Ranga Vemuri},
editor = {Gerald Musgrave},
title = {Finite state machine verification on {MIMD} machines},
booktitle = {Proceedings of the conference on European design automation, {EURO-DAC}
'92, Hamburg, Germany, September 7-10, 1992},
pages = {514--520},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {https://doi.org/10.1109/EURDAC.1992.246312},
doi = {10.1109/EURDAC.1992.246312},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/KumarV92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cav/VemuriS91,
author = {Ranga Vemuri and
Anuradha Sridhar},
editor = {Kim Guldstrand Larsen and
Arne Skou},
title = {Temporal Precondition Verification of Design Transformations},
booktitle = {Computer Aided Verification, 3rd International Workshop, {CAV} '91,
Aalborg, Denmark, July, 1-4, 1991, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {575},
pages = {125--135},
publisher = {Springer},
year = {1991},
url = {https://doi.org/10.1007/3-540-55179-4\_13},
doi = {10.1007/3-540-55179-4\_13},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cav/VemuriS91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VemuriV91,
author = {Ram Vemuri and
Ranga Vemuri},
title = {Genetic synthesis: performance-driven logic synthesis using genetic
evolution},
booktitle = {First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March
1-2, 1991},
pages = {312--317},
publisher = {{IEEE}},
year = {1991},
url = {https://doi.org/10.1109/GLSV.1991.143985},
doi = {10.1109/GLSV.1991.143985},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/VemuriV91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/Vemuri90,
author = {Ranga Vemuri},
editor = {Gordon Adshead and
Jochen A. G. Jess},
title = {On the notion of the normal form register-level structures and its
applications in design-space exploration},
booktitle = {European Design Automation Conference, {EURO-DAC} 1990, Glasgow, Scotland,
UK, March 12-15, 1990},
pages = {46--51},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/EDAC.1990.136618},
doi = {10.1109/EDAC.1990.136618},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/Vemuri90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/KoutsougerasPV86,
author = {Cris Koutsougeras and
Christos A. Papachristou and
Ranga Vemuri},
editor = {Stanley Habib},
title = {Data flow graph partitioning to reduce communication cost},
booktitle = {Proceedings of the 19th annual workshop on Microprogramming, New York,
NY, USA, October 15-17, 1986},
pages = {82--91},
publisher = {{ACM/IEEE}},
year = {1986},
url = {https://doi.org/10.1145/19551.19540},
doi = {10.1145/19551.19540},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/KoutsougerasPV86.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/compsac/VemuriC78,
author = {Ranga Vemuri and
J. V. Cornacchio},
title = {Continuing education in microprocessors: Use of software simulators},
booktitle = {The {IEEE} Computer Society's Second International Computer Software
and Applications Conference, {COMPSAC} 1978, 13-16 November, 1978,
Chicago, Illinois, {USA}},
pages = {803--806},
publisher = {{IEEE}},
year = {1978},
url = {https://doi.org/10.1109/CMPSAC.1978.810570},
doi = {10.1109/CMPSAC.1978.810570},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/compsac/VemuriC78.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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