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ORCIDBibTeX records: Valerio Tenace
@inproceedings{DBLP:conf/asap/BrownTG21,
author = {Grant Brown and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon},
title = {{NEMO-CNN:} An Efficient Near-Memory Accelerator for Convolutional
Neural Networks},
booktitle = {32nd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2021, Virtual Conference, USA,
July 7-9, 2021},
pages = {57--60},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASAP52443.2021.00016},
doi = {10.1109/ASAP52443.2021.00016},
timestamp = {Mon, 30 Aug 2021 15:22:57 +0200},
biburl = {https://dblp.org/rec/conf/asap/BrownTG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RaiNMZYYFMPRABC21,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1026--1031},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9473972},
doi = {10.23919/DATE51398.2021.9473972},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/RaiNMZYYFMPRABC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TenaceCMP20,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar
Technologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {2},
pages = {397--410},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2018.2889770},
doi = {10.1109/TCAD.2018.2889770},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TenaceCMP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2012-02530,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa Jr. and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
journal = {CoRR},
volume = {abs/2012.02530},
year = {2020},
url = {https://arxiv.org/abs/2012.02530},
eprinttype = {arXiv},
eprint = {2012.02530},
timestamp = {Thu, 04 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2012-02530.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fi/GrimaldiTC19,
author = {Matteo Grimaldi and
Valerio Tenace and
Andrea Calimera},
title = {Layer-Wise Compressive Training for Convolutional Neural Networks},
journal = {Future Internet},
volume = {11},
number = {1},
pages = {7},
year = {2019},
url = {https://doi.org/10.3390/fi11010007},
doi = {10.3390/FI11010007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/fi/GrimaldiTC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TenaceRBCC19,
author = {Valerio Tenace and
Roberto Giorgio Rizzo and
Debjyoti Bhattacharjee and
Anupam Chattopadhyay and
Andrea Calimera},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {{SAID:} {A} Supergate-Aided Logic Synthesis Flow for Memristive Crossbars},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {372--377},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714939},
doi = {10.23919/DATE.2019.8714939},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/TenaceRBCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MocerinoTC19,
author = {Luca Mocerino and
Valerio Tenace and
Andrea Calimera},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Energy-Efficient Convolutional Neural Networks via Recurrent Data
Reuse},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {848--853},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714880},
doi = {10.23919/DATE.2019.8714880},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MocerinoTC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/TenaceC18,
author = {Valerio Tenace and
Andrea Calimera},
title = {Quasi-exact logic functions through classification trees},
journal = {Integr.},
volume = {63},
pages = {248--255},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.06.007},
doi = {10.1016/J.VLSI.2018.06.007},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/TenaceC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esweek/GrimaldiPTC18,
author = {Matteo Grimaldi and
Federico Pugliese and
Valerio Tenace and
Andrea Calimera},
editor = {Maurizio Martina and
William Fornaciari},
title = {A compression-driven training framework for embedded deep neural networks},
booktitle = {Proceedings of the Workshop on INTelligent Embedded Systems Architectures
and Applications, INTESA@ESWEEK 2018, Turin, Italy, October 04-04,
2018},
pages = {45--50},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3285017.3285021},
doi = {10.1145/3285017.3285021},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esweek/GrimaldiPTC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/RizzoTC18,
author = {Roberto Giorgio Rizzo and
Valerio Tenace and
Andrea Calimera},
title = {Multiplication by Inference using Classification Trees: {A} Case-Study
Analysis},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351206},
doi = {10.1109/ISCAS.2018.8351206},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/RizzoTC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TenaceC18,
author = {Valerio Tenace and
Andrea Calimera},
title = {Inferential Logic: a Machine Learning Inspired Paradigm for Combinational
Circuits},
booktitle = {{IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2018, Verona, Italy, October 8-10, 2018},
pages = {149--154},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSI-SoC.2018.8644808},
doi = {10.1109/VLSI-SOC.2018.8644808},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TenaceC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/TenaceC17,
author = {Valerio Tenace and
Andrea Calimera},
title = {Activation-Kernel Extraction through Machine Learning},
booktitle = {New Generation of CAS, {NGCAS} 2017, Genova, Italy, September 6-9,
2017},
pages = {5--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NGCAS.2017.29},
doi = {10.1109/NGCAS.2017.29},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ngcas/TenaceC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/it/Tenace16,
author = {Valerio Tenace},
title = {{CAD} Tools for Graphene-Based Electronic Circuits},
school = {Polytechnic University of Turin, Italy},
year = {2016},
url = {https://opac.bncf.firenze.sbn.it/bncf-prod/resource?uri=BVE0745680},
timestamp = {Mon, 22 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/it/Tenace16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/TenaceCMP16,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient
ICs},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {63-II},
number = {12},
pages = {1111--1115},
year = {2016},
url = {https://doi.org/10.1109/TCSII.2016.2624145},
doi = {10.1109/TCSII.2016.2624145},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/TenaceCMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TenaceCMP16,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
editor = {Ayse K. Coskun and
Martin Margala and
Laleh Behjat and
Jie Han},
title = {Graphene-PLA {(GPLA):} a Compact and Ultra-Low Power Logic Array Architecture},
booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI,
{GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016},
pages = {145--150},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2902961.2902970},
doi = {10.1145/2902961.2902970},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/TenaceCMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TenaceCMP16,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon
technologies},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {2897},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7539200},
doi = {10.1109/ISCAS.2016.7539200},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/TenaceCMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TenaceCMP16,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {Multi-function logic synthesis of silicon and beyond-silicon ultra-low
power pass-gates circuits},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753575},
doi = {10.1109/VLSI-SOC.2016.7753575},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TenaceCMP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TenaceCMP16a,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
editor = {Thomas Hollstein and
Jaan Raik and
Sergei Kostin and
Anton Tsertov and
Ian O'Connor and
Ricardo Reis},
title = {Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic
Circuits},
booktitle = {VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification
and Reliability - 24th {IFIP} {WG} 10.5/IEEE International Conference
on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia,
September 26-28, 2016, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {508},
pages = {60--82},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-67104-8\_4},
doi = {10.1007/978-3-319-67104-8\_4},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/TenaceCMP16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/MiryalaTCMP15,
author = {Sandeep Miryala and
Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {Ultra-low power circuits using graphene p-n junctions and adiabatic
computing},
journal = {Microprocess. Microsystems},
volume = {39},
number = {8},
pages = {962--972},
year = {2015},
url = {https://doi.org/10.1016/j.micpro.2015.05.018},
doi = {10.1016/J.MICPRO.2015.05.018},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/MiryalaTCMP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TenaceCMP15,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {One-pass logic synthesis for graphene-based Pass-XNOR logic circuits},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {128:1--128:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744880},
doi = {10.1145/2744769.2744880},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/TenaceCMP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MiryalaTCMPAMG15,
author = {Sandeep Miryala and
Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino and
Luca Gaetano Amar{\`{u}} and
Giovanni De Micheli and
Pierre{-}Emmanuel Gaillardon},
editor = {Alex K. Jones and
Hai (Helen) Li and
Ayse K. Coskun and
Martin Margala},
title = {Exploiting the Expressive Power of Graphene Reconfigurable Gates via
Post-Synthesis Optimization},
booktitle = {Proceedings of the 25th edition on Great Lakes Symposium on VLSI,
{GLVLSI} 2015, Pittsburgh, PA, USA, May 20 - 22, 2015},
pages = {39--44},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2742060.2742098},
doi = {10.1145/2742060.2742098},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MiryalaTCMPAMG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/TenaceMCMMP14,
author = {Valerio Tenace and
Sandeep Miryala and
Andrea Calimera and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Row-based body-bias assignment for dynamic thermal clock-skew compensation},
journal = {Microelectron. J.},
volume = {45},
number = {5},
pages = {530--538},
year = {2014},
url = {https://doi.org/10.1016/j.mejo.2013.11.013},
doi = {10.1016/J.MEJO.2013.11.013},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/TenaceMCMMP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TenaceCMP14,
author = {Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Pass-XNOR logic: {A} new logic style for {P-N} junction based graphene
circuits},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.275},
doi = {10.7873/DATE.2014.275},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/TenaceCMP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiuMTCMP12,
author = {Wei Liu and
Sandeep Miryala and
Valerio Tenace and
Andrea Calimera and
Enrico Macii and
Massimo Poncino},
editor = {Erik Brunvard and
Ken Stevens and
Joseph R. Cavallaro and
Tong Zhang},
title = {{NBTI} effects on tree-like clock distribution networks},
booktitle = {Great Lakes Symposium on {VLSI} 2012, GLSVLSI'12, Salt Lake City,
UT, USA, May 3-4, 2012},
pages = {279--282},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2206781.2206849},
doi = {10.1145/2206781.2206849},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/LiuMTCMP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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