BibTeX records: Sharad Sinha

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@article{DBLP:journals/tcad/LinSZ19,
  author    = {Zhe Lin and
               Sharad Sinha and
               Wei Zhang},
  title     = {An Ensemble Learning Approach for In-Situ Monitoring of {FPGA} Dynamic
               Power},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {38},
  number    = {9},
  pages     = {1661--1674},
  year      = {2019},
  url       = {https://doi.org/10.1109/TCAD.2018.2859248},
  doi       = {10.1109/TCAD.2018.2859248},
  timestamp = {Thu, 05 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/LinSZ19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FengZLSZ19,
  author    = {Liang Feng and
               Jieru Zhao and
               Tingyuan Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {{LAMA:} Link-Aware Hybrid Management for Memory Accesses in Emerging
               {CPU-FPGA} Platforms},
  booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
               {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
  pages     = {1},
  year      = {2019},
  crossref  = {DBLP:conf/dac/2019},
  url       = {https://doi.org/10.1145/3316781.3317846},
  doi       = {10.1145/3316781.3317846},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dac/FengZLSZ19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZhaoLSZ19,
  author    = {Jieru Zhao and
               Tingyuan Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {Machine Learning Based Routing Congestion Prediction in {FPGA} High-Level
               Synthesis},
  booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
               {DATE} 2019, Florence, Italy, March 25-29, 2019},
  pages     = {1130--1135},
  year      = {2019},
  crossref  = {DBLP:conf/date/2019},
  url       = {https://doi.org/10.23919/DATE.2019.8714724},
  doi       = {10.23919/DATE.2019.8714724},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/date/ZhaoLSZ19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/0007SZ19,
  author    = {Zhe Lin and
               Sharad Sinha and
               Wei Zhang},
  title     = {Towards Efficient and Scalable Acceleration of Online Decision Tree
               Learning on {FPGA}},
  booktitle = {27th {IEEE} Annual International Symposium on Field-Programmable Custom
               Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May
               1, 2019},
  pages     = {172--180},
  year      = {2019},
  crossref  = {DBLP:conf/fccm/2019},
  url       = {https://doi.org/10.1109/FCCM.2019.00032},
  doi       = {10.1109/FCCM.2019.00032},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fccm/0007SZ19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FengZLSZ19,
  author    = {Liang Feng and
               Jieru Zhao and
               Tingyuan Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {A Hybrid Data-Consistent Framework for Link-Aware AccessManagement
               in Emerging {CPU-FPGA} Platforms},
  booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
               Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
  pages     = {188},
  year      = {2019},
  crossref  = {DBLP:conf/fpga/2019},
  url       = {https://doi.org/10.1145/3289602.3293973},
  doi       = {10.1145/3289602.3293973},
  timestamp = {Fri, 30 Aug 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpga/FengZLSZ19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SSG19,
  author    = {Arish S and
               Sharad Sinha and
               Smitha K. G},
  title     = {Optimization of Convolutional Neural Networks on Resource Constrained
               Devices},
  booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
               Miami, FL, USA, July 15-17, 2019},
  pages     = {19--24},
  year      = {2019},
  crossref  = {DBLP:conf/isvlsi/2019},
  url       = {https://doi.org/10.1109/ISVLSI.2019.00013},
  doi       = {10.1109/ISVLSI.2019.00013},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/SSG19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1905-03852,
  author    = {Jieru Zhao and
               Tingyuan Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {Machine Learning Based Routing Congestion Prediction in {FPGA} High-Level
               Synthesis},
  journal   = {CoRR},
  volume    = {abs/1905.03852},
  year      = {2019},
  url       = {http://arxiv.org/abs/1905.03852},
  archivePrefix = {arXiv},
  eprint    = {1905.03852},
  timestamp = {Fri, 30 Aug 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/corr/abs-1905-03852},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangSZ18,
  author    = {Hao Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {Parallelizing Hardware Tasks on Multicontext {FPGA} With Efficient
               Placement and Scheduling Algorithms},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {37},
  number    = {2},
  pages     = {350--363},
  year      = {2018},
  url       = {https://doi.org/10.1109/TCAD.2017.2697952},
  doi       = {10.1109/TCAD.2017.2697952},
  timestamp = {Sat, 01 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/LiangSZ18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangZFSZ18,
  author    = {Tingyuan Liang and
               Jieru Zhao and
               Liang Feng and
               Sharad Sinha and
               Wei Zhang},
  title     = {Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {37},
  number    = {11},
  pages     = {2555--2566},
  year      = {2018},
  url       = {https://doi.org/10.1109/TCAD.2018.2857040},
  doi       = {10.1109/TCAD.2018.2857040},
  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/LiangZFSZ18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmscs/LinSLFZ18,
  author    = {Zhe Lin and
               Sharad Sinha and
               Hao Liang and
               Liang Feng and
               Wei Zhang},
  title     = {Scalable Light-Weight Integration of {FPGA} Based Accelerators with
               Chip Multi-Processors},
  journal   = {{IEEE} Trans. Multi-Scale Computing Systems},
  volume    = {4},
  number    = {2},
  pages     = {152--162},
  year      = {2018},
  url       = {https://doi.org/10.1109/TMSCS.2017.2754378},
  doi       = {10.1109/TMSCS.2017.2754378},
  timestamp = {Sat, 01 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tmscs/LinSLFZ18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/FengSZ018,
  author    = {Liang Feng and
               Sharad Sinha and
               Wei Zhang and
               Yun Liang},
  title     = {{CAMAS:} Static and Dynamic Hybrid Cache Management for {CPU-FPGA}
               Platforms},
  booktitle = {26th {IEEE} Annual International Symposium on Field-Programmable Custom
               Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May
               1, 2018},
  pages     = {165--172},
  year      = {2018},
  crossref  = {DBLP:conf/fccm/2018},
  url       = {https://doi.org/10.1109/FCCM.2018.00034},
  doi       = {10.1109/FCCM.2018.00034},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fccm/FengSZ018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MuZLS18,
  author    = {Jiandong Mu and
               Wei Zhang and
               Hao Liang and
               Sharad Sinha},
  title     = {A Collaborative Framework for FPGA-based {CNN} Design Modeling and
               Optimization},
  booktitle = {28th International Conference on Field Programmable Logic and Applications,
               {FPL} 2018, Dublin, Ireland, August 27-31, 2018},
  pages     = {139--146},
  year      = {2018},
  crossref  = {DBLP:conf/fpl/2018},
  url       = {https://doi.org/10.1109/FPL.2018.00032},
  doi       = {10.1109/FPL.2018.00032},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/MuZLS18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/FengLS017,
  author    = {Liang Feng and
               Hao Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {HeteroSim: {A} Heterogeneous {CPU-FPGA} Simulator},
  journal   = {Computer Architecture Letters},
  volume    = {16},
  number    = {1},
  pages     = {38--41},
  year      = {2017},
  url       = {https://doi.org/10.1109/LCA.2016.2615617},
  doi       = {10.1109/LCA.2016.2615617},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/cal/FengLS017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LiangFSZ17,
  author    = {Tingyuan Liang and
               Liang Feng and
               Sharad Sinha and
               Wei Zhang},
  title     = {{PAAS:} {A} system level simulator for heterogeneous computing architectures},
  booktitle = {27th International Conference on Field Programmable Logic and Applications,
               {FPL} 2017, Ghent, Belgium, September 4-8, 2017},
  pages     = {1--8},
  year      = {2017},
  crossref  = {DBLP:conf/fpl/2017},
  url       = {https://doi.org/10.23919/FPL.2017.8056775},
  doi       = {10.23919/FPL.2017.8056775},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/LiangFSZ17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LinZS17,
  author    = {Zhe Lin and
               Wei Zhang and
               Sharad Sinha},
  title     = {Decision tree based hardware power monitoring for run time dynamic
               power management in {FPGA}},
  booktitle = {27th International Conference on Field Programmable Logic and Applications,
               {FPL} 2017, Ghent, Belgium, September 4-8, 2017},
  pages     = {1--8},
  year      = {2017},
  crossref  = {DBLP:conf/fpl/2017},
  url       = {https://doi.org/10.23919/FPL.2017.8056832},
  doi       = {10.23919/FPL.2017.8056832},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/LinZS17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhaoFSZLH17,
  author    = {Jieru Zhao and
               Liang Feng and
               Sharad Sinha and
               Wei Zhang and
               Yun Liang and
               Bingsheng He},
  title     = {{COMBA:} {A} comprehensive model-based analysis framework for high
               level synthesis of real applications},
  booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
               {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
  pages     = {430--437},
  year      = {2017},
  crossref  = {DBLP:conf/iccad/2017},
  url       = {https://doi.org/10.1109/ICCAD.2017.8203809},
  doi       = {10.1109/ICCAD.2017.8203809},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/ZhaoFSZLH17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/FengSZL17,
  author    = {Liang Feng and
               Sharad Sinha and
               Wei Zhang and
               Yun Liang},
  title     = {A hybrid approach to cache management in heterogeneous {CPU-FPGA}
               platforms},
  booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
               {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
  pages     = {937--944},
  year      = {2017},
  crossref  = {DBLP:conf/iccad/2017},
  url       = {https://doi.org/10.1109/ICCAD.2017.8203881},
  doi       = {10.1109/ICCAD.2017.8203881},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/FengSZL17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinhaZ16,
  author    = {Sharad Sinha and
               Wei Zhang},
  title     = {Low-Power {FPGA} Design Using Memoization-Based Approximate Computing},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {24},
  number    = {8},
  pages     = {2665--2678},
  year      = {2016},
  url       = {https://doi.org/10.1109/TVLSI.2016.2520979},
  doi       = {10.1109/TVLSI.2016.2520979},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tvlsi/SinhaZ16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/TahghighiSZ16,
  author    = {Mohammad Tahghighi and
               Sharad Sinha and
               Wei Zhang},
  title     = {Analytical Delay Model for {CPU-FPGA} Data Paths in Programmable System-on-Chip
               {FPGA}},
  booktitle = {Applied Reconfigurable Computing - 12th International Symposium, {ARC}
               2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings},
  pages     = {159--170},
  year      = {2016},
  crossref  = {DBLP:conf/arc/2016},
  url       = {https://doi.org/10.1007/978-3-319-30481-6\_13},
  doi       = {10.1007/978-3-319-30481-6\_13},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/arc/TahghighiSZ16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/FengLSZ16,
  author    = {Liang Feng and
               Hao Liang and
               Sharad Sinha and
               Wei Zhang},
  title     = {HeteroSim: {A} heterogeneous {CPU-FPGA} simulator},
  booktitle = {26th International Conference on Field Programmable Logic and Applications,
               {FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
  pages     = {1},
  year      = {2016},
  crossref  = {DBLP:conf/fpl/2016},
  url       = {https://doi.org/10.1109/FPL.2016.7577386},
  doi       = {10.1109/FPL.2016.7577386},
  timestamp = {Fri, 17 Jan 2020 17:11:15 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/FengLSZ16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/TahghighiZS16,
  author    = {Mohammad Tahghighi and
               Wei Zhang and
               Sharad Sinha},
  title     = {Area Efficient Hardware Architecture for Implicitly-Defined Complex
               Events Processing},
  booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
               PA, USA, July 11-13, 2016},
  pages     = {667--672},
  year      = {2016},
  crossref  = {DBLP:conf/isvlsi/2016},
  url       = {https://doi.org/10.1109/ISVLSI.2016.130},
  doi       = {10.1109/ISVLSI.2016.130},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/TahghighiZS16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LiangSWZ15,
  author    = {Hao Liang and
               Sharad Sinha and
               Rakesh Warrier and
               Wei Zhang},
  title     = {Static hardware task placement on multi-context {FPGA} using hybrid
               genetic algorithm},
  booktitle = {25th International Conference on Field Programmable Logic and Applications,
               {FPL} 2015, London, United Kingdom, September 2-4, 2015},
  pages     = {1--8},
  year      = {2015},
  crossref  = {DBLP:conf/fpl/2015},
  url       = {https://doi.org/10.1109/FPL.2015.7293954},
  doi       = {10.1109/FPL.2015.7293954},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/LiangSWZ15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LiangZSCL15,
  author    = {Hao Liang and
               Wei Zhang and
               Sharad Sinha and
               Yi{-}Chung Chen and
               Hai Li},
  title     = {Hierarchical library based power estimator for versatile FPGAs},
  booktitle = {25th International Conference on Field Programmable Logic and Applications,
               {FPL} 2015, London, United Kingdom, September 2-4, 2015},
  pages     = {1},
  year      = {2015},
  crossref  = {DBLP:conf/fpl/2015},
  url       = {https://doi.org/10.1109/FPL.2015.7293969},
  doi       = {10.1109/FPL.2015.7293969},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/LiangZSCL15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/SinhaS14,
  author    = {Sharad Sinha and
               Thambipillai Srikanthan},
  title     = {IP-Enabled {C/C++} Based High Level Synthesis: {A} Step towards Better
               Designer Productivity and Design Performance},
  journal   = {Int. J. Reconfig. Comp.},
  volume    = {2014},
  pages     = {418750:1--418750:17},
  year      = {2014},
  url       = {https://doi.org/10.1155/2014/418750},
  doi       = {10.1155/2014/418750},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ijrc/SinhaS14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/SinhaS14a,
  author    = {Sharad Sinha and
               Thambipillai Srikanthan},
  title     = {Architecture and Application-Aware Management of Complexity of Mapping
               Multiplication to {FPGA} {DSP} Blocks in High Level Synthesis},
  journal   = {Int. J. Reconfig. Comp.},
  volume    = {2014},
  pages     = {564924:1--564924:14},
  year      = {2014},
  url       = {https://doi.org/10.1155/2014/564924},
  doi       = {10.1155/2014/564924},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ijrc/SinhaS14a},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/SinhaDS14,
  author    = {Sharad Sinha and
               Udit Dhawan and
               Thambipillai Srikanthan},
  title     = {Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm
               for High Level synthesis of Area-Time Efficient Designs},
  journal   = {Journal of Circuits, Systems, and Computers},
  volume    = {23},
  number    = {9},
  year      = {2014},
  url       = {https://doi.org/10.1142/S021812661450131X},
  doi       = {10.1142/S021812661450131X},
  timestamp = {Sun, 28 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jcsc/SinhaDS14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SinhaS14,
  author    = {Sharad Sinha and
               Thambipillai Srikanthan},
  title     = {Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis
               with Systems Perspective},
  journal   = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume    = {20},
  number    = {1},
  pages     = {5:1--5:18},
  year      = {2014},
  url       = {https://doi.org/10.1145/2660769},
  doi       = {10.1145/2660769},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/todaes/SinhaS14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ficta/BhowmikDS14,
  author    = {Dipanjan Bhowmik and
               Avijit Datta and
               Sharad Sinha},
  title     = {A Bit-Level Block Cipher Diffusion Analysis Test - {BLDAT}},
  booktitle = {Proceedings of the 3rd International Conference on Frontiers of Intelligent
               Computing: Theory and Applications {(FICTA)} 2014 - Volume 1, Bhubaneswar,
               Odisa, India, 14-15 November 2014},
  pages     = {667--674},
  year      = {2014},
  crossref  = {DBLP:conf/ficta/2014-1},
  url       = {https://doi.org/10.1007/978-3-319-11933-5\_75},
  doi       = {10.1007/978-3-319-11933-5\_75},
  timestamp = {Sat, 19 Oct 2019 20:24:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ficta/BhowmikDS14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SinhaS12,
  author    = {Sharad Sinha and
               Thambipillai Srikanthan},
  title     = {Dataflow graph partitioning for high level synthesis},
  booktitle = {22nd International Conference on Field Programmable Logic and Applications
               (FPL), Oslo, Norway, August 29-31, 2012},
  pages     = {503--506},
  year      = {2012},
  crossref  = {DBLP:conf/fpl/2012},
  url       = {https://doi.org/10.1109/FPL.2012.6339265},
  doi       = {10.1109/FPL.2012.6339265},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/SinhaS12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SinhaDLS11,
  author    = {Sharad Sinha and
               Udit Dhawan and
               Siew Kei Lam and
               Thambipillai Srikanthan},
  title     = {A Novel Binding Algorithm to Reduce Critical Path Delay During High
               Level Synthesis},
  booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
               July 2011, Chennai, India},
  pages     = {278--283},
  year      = {2011},
  crossref  = {DBLP:conf/isvlsi/2011},
  url       = {https://doi.org/10.1109/ISVLSI.2011.18},
  doi       = {10.1109/ISVLSI.2011.18},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/SinhaDLS11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dac/2019,
  title     = {Proceedings of the 56th Annual Design Automation Conference 2019,
               {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3316781},
  doi       = {10.1145/3316781},
  isbn      = {978-1-4503-6725-7},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dac/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/date/2019,
  editor    = {J{\"{u}}rgen Teich and
               Franco Fummi},
  title     = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
               {DATE} 2019, Florence, Italy, March 25-29, 2019},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8704855/proceeding},
  isbn      = {978-3-9819263-2-3},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/date/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fccm/2019,
  title     = {27th {IEEE} Annual International Symposium on Field-Programmable Custom
               Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May
               1, 2019},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8727045/proceeding},
  isbn      = {978-1-7281-1131-5},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fccm/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/2019,
  editor    = {Kia Bazargan and
               Stephen Neuendorffer},
  title     = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
               Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3289602},
  doi       = {10.1145/3289602},
  isbn      = {978-1-4503-6137-8},
  timestamp = {Tue, 05 Mar 2019 07:04:43 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fpga/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2019,
  title     = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
               Miami, FL, USA, July 15-17, 2019},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8826391/proceeding},
  isbn      = {978-1-7281-3391-1},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fccm/2018,
  title     = {26th {IEEE} Annual International Symposium on Field-Programmable Custom
               Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May
               1, 2018},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8457441/proceeding},
  isbn      = {978-1-5386-5522-1},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fccm/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpl/2018,
  title     = {28th International Conference on Field Programmable Logic and Applications,
               {FPL} 2018, Dublin, Ireland, August 27-31, 2018},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8529150/proceeding},
  isbn      = {978-1-5386-8517-4},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpl/2017,
  editor    = {Marco D. Santambrogio and
               Diana G{\"{o}}hringer and
               Dirk Stroobandt and
               Nele Mentens and
               Jari Nurmi},
  title     = {27th International Conference on Field Programmable Logic and Applications,
               {FPL} 2017, Ghent, Belgium, September 4-8, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8049195/proceeding},
  isbn      = {978-9-0903-0428-1},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/2017,
  editor    = {Sri Parameswaran},
  title     = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
               {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8167715/proceeding},
  isbn      = {978-1-5386-3093-8},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/arc/2016,
  editor    = {Vanderlei Bonato and
               Christos Bouganis and
               Marek Gorgon},
  title     = {Applied Reconfigurable Computing - 12th International Symposium, {ARC}
               2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {9625},
  publisher = {Springer},
  year      = {2016},
  url       = {https://doi.org/10.1007/978-3-319-30481-6},
  doi       = {10.1007/978-3-319-30481-6},
  isbn      = {978-3-319-30480-9},
  timestamp = {Tue, 14 May 2019 10:00:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/arc/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpl/2016,
  editor    = {Paolo Ienne and
               Walid A. Najjar and
               Jason Helge Anderson and
               Philip Brisk and
               Walter Stechele},
  title     = {26th International Conference on Field Programmable Logic and Applications,
               {FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7573873/proceeding},
  isbn      = {978-2-8399-1844-2},
  timestamp = {Fri, 17 Jan 2020 17:11:15 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2016,
  title     = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
               PA, USA, July 11-13, 2016},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7558446/proceeding},
  isbn      = {978-1-4673-9039-2},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpl/2015,
  title     = {25th International Conference on Field Programmable Logic and Applications,
               {FPL} 2015, London, United Kingdom, September 2-4, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7284611/proceeding},
  isbn      = {978-0-9934-2800-5},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ficta/2014-1,
  editor    = {Suresh Chandra Satapathy and
               Bhabendra Narayan Biswal and
               Siba K. Udgata and
               J. K. Mandal},
  title     = {Proceedings of the 3rd International Conference on Frontiers of Intelligent
               Computing: Theory and Applications {(FICTA)} 2014 - Volume 1, Bhubaneswar,
               Odisa, India, 14-15 November 2014},
  series    = {Advances in Intelligent Systems and Computing},
  volume    = {327},
  publisher = {Springer},
  year      = {2015},
  url       = {https://doi.org/10.1007/978-3-319-11933-5},
  doi       = {10.1007/978-3-319-11933-5},
  isbn      = {978-3-319-11932-8},
  timestamp = {Sat, 19 Oct 2019 20:24:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ficta/2014-1},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpl/2012,
  editor    = {Dirk Koch and
               Satnam Singh and
               Jim T{\o}rresen},
  title     = {22nd International Conference on Field Programmable Logic and Applications
               (FPL), Oslo, Norway, August 29-31, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6330714/proceeding},
  isbn      = {978-1-4673-2257-7},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/fpl/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2011,
  title     = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
               July 2011, Chennai, India},
  publisher = {{IEEE} Computer Society},
  year      = {2011},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/5992458/proceeding},
  isbn      = {978-0-7695-4447-2},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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