BibTeX records: Amitabha Sinha

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@article{DBLP:journals/ijsinnov/SanyalS22,
  author       = {Atri Sanyal and
                  Amitabha Sinha},
  title        = {Trans{\_}Proc: {A} Reconfigurable Processor to Implement The Linear
                  Transformations},
  journal      = {Int. J. Softw. Innov.},
  volume       = {10},
  number       = {1},
  pages        = {1--16},
  year         = {2022},
  url          = {https://doi.org/10.4018/ijsi.303575},
  doi          = {10.4018/IJSI.303575},
  timestamp    = {Wed, 17 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijsinnov/SanyalS22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/MukherjeeSC15,
  author       = {Atin Mukherjee and
                  Amitabha Sinha and
                  Debesh Choudhury},
  title        = {A Novel Architecture of Area Efficient {FFT} Algorithm for {FPGA}
                  Implementation},
  journal      = {CoRR},
  volume       = {abs/1502.07055},
  year         = {2015},
  url          = {http://arxiv.org/abs/1502.07055},
  eprinttype    = {arXiv},
  eprint       = {1502.07055},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/MukherjeeSC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MukherjeeSC14,
  author       = {Atin Mukherjee and
                  Amitabha Sinha and
                  Debesh Choudhury},
  title        = {A Novel Architecture of Area Efficient {FFT} Algorithm for {FPGA}
                  Implementation},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {42},
  number       = {5},
  pages        = {1--6},
  year         = {2014},
  url          = {https://doi.org/10.1145/2935687.2935689},
  doi          = {10.1145/2935687.2935689},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MukherjeeSC14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SinhaSAC13,
  author       = {Amitabha Sinha and
                  Mitrava Sarkar and
                  Soumojit Acharyya and
                  Suranjan Chakraborty},
  title        = {A novel reconfigurable architecture of a {DSP} processor for efficient
                  mapping of {DSP} functions using field programmable {DSP} arrays},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {2},
  pages        = {1--8},
  year         = {2013},
  url          = {https://doi.org/10.1145/2490302.2490304},
  doi          = {10.1145/2490302.2490304},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/SinhaSAC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SahaMDSS13,
  author       = {Amrita Saha and
                  Manideepa Mukherjee and
                  Debanjana Datta and
                  Sangita Saha and
                  Amitabha Sinha},
  title        = {Performance analysis of a {FPGA} based novel binary and {DBNS} multiplier},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {2},
  pages        = {9--16},
  year         = {2013},
  url          = {https://doi.org/10.1145/2490302.2490305},
  doi          = {10.1145/2490302.2490305},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/SahaMDSS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SahaBS13,
  author       = {Amrita Saha and
                  Pijush Biswas and
                  Amitabha Sinha},
  title        = {An integrated development platform of a reconfigurable radio processor
                  for software defined radio},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {2},
  pages        = {30--35},
  year         = {2013},
  url          = {https://doi.org/10.1145/2490302.2490308},
  doi          = {10.1145/2490302.2490308},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/SahaBS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/PalSB13,
  author       = {Santanu Pal and
                  Amitabha Sinha and
                  Pijush Biswas},
  title        = {{FPGA} implementation of a novel {DCT} architecture reducing constant
                  cosine terms},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {2},
  pages        = {36--40},
  year         = {2013},
  url          = {https://doi.org/10.1145/2490302.2490309},
  doi          = {10.1145/2490302.2490309},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/PalSB13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MaitraS13,
  author       = {Subhashis Maitra and
                  Amitabha Sinha},
  title        = {High performance {MAC} unit for {DSP} and cryptographic applications},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {2},
  pages        = {47--55},
  year         = {2013},
  url          = {https://doi.org/10.1145/2490302.2490311},
  doi          = {10.1145/2490302.2490311},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MaitraS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MaitraS13a,
  author       = {Subhashis Maitra and
                  Amitabha Sinha},
  title        = {High efficiency {MAC} unit used in digital signal processing and elliptic
                  curve cryptography},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {4},
  pages        = {1--7},
  year         = {2013},
  url          = {https://doi.org/10.1145/2560488.2560490},
  doi          = {10.1145/2560488.2560490},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MaitraS13a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MaitraS13b,
  author       = {Subhashis Maitra and
                  Amitabha Sinha},
  title        = {Design and simulation of {MAC} unit using combinational circuit and
                  adder},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {41},
  number       = {5},
  pages        = {25--33},
  year         = {2013},
  url          = {https://doi.org/10.1145/2641361.2641365},
  doi          = {10.1145/2641361.2641365},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MaitraS13b.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/abs-1305-3251,
  author       = {Amitabha Sinha and
                  Soumojit Acharyya and
                  Suranjan Chakraborty and
                  Mitrava Sarkar},
  title        = {Field Programmable {DSP} Arrays - {A}},
  journal      = {CoRR},
  volume       = {abs/1305.3251},
  year         = {2013},
  url          = {http://arxiv.org/abs/1305.3251},
  eprinttype    = {arXiv},
  eprint       = {1305.3251},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1305-3251.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/SinhaSAC13,
  author       = {Amitabha Sinha and
                  Mitrava Sarkar and
                  Soumojit Acharyya and
                  Suranjan Chakraborty},
  title        = {A Novel Reconfigurable Architecture of a {DSP} Processor for Efficient
                  Mapping of {DSP} Functions using Field Programmable {DSP} Arrays},
  journal      = {CoRR},
  volume       = {abs/1306.0089},
  year         = {2013},
  url          = {http://arxiv.org/abs/1306.0089},
  eprinttype    = {arXiv},
  eprint       = {1306.0089},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/SinhaSAC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/GiriS12,
  author       = {Nishant Kumar Giri and
                  Amitabha Sinha},
  title        = {{FPGA} implementation of a novel architecture for performance enhancement
                  of Radix-2 {FFT}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {40},
  number       = {2},
  pages        = {28--32},
  year         = {2012},
  url          = {https://doi.org/10.1145/2234336.2234341},
  doi          = {10.1145/2234336.2234341},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/GiriS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/GhoshSS12,
  author       = {Aniruddha Ghosh and
                  Satrughna Singha and
                  Amitabha Sinha},
  title        = {A new architecture for {FPGA} implementation of a {MAC} unit for digital
                  signal processors using mixed number system},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {40},
  number       = {2},
  pages        = {33--38},
  year         = {2012},
  url          = {https://doi.org/10.1145/2234336.2234342},
  doi          = {10.1145/2234336.2234342},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/sigarch/GhoshSS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/GhoshSS12a,
  author       = {Aniruddha Ghosh and
                  Satrughna Singha and
                  Amitabha Sinha},
  title        = {"Floating point RNS": a new concept for designing the {MAC}
                  unit of digital signal processor},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {40},
  number       = {2},
  pages        = {39--43},
  year         = {2012},
  url          = {https://doi.org/10.1145/2234336.2234343},
  doi          = {10.1145/2234336.2234343},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/sigarch/GhoshSS12a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MaitraS12,
  author       = {Subhashis Maitra and
                  Amitabha Sinha},
  title        = {A new algorithm for computing triple-base number system},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {40},
  number       = {4},
  pages        = {3--9},
  year         = {2012},
  url          = {https://doi.org/10.1145/2411116.2411119},
  doi          = {10.1145/2411116.2411119},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MaitraS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/acity/DuttaGS12,
  author       = {Chaitali Biswas Dutta and
                  Partha Garai and
                  Amitabha Sinha},
  editor       = {Natarajan Meghanathan and
                  Dhinaharan Nagamalai and
                  Nabendu Chaki},
  title        = {A Scheme for Improving Bit Efficiency for Residue Number System},
  booktitle    = {Advances in Computing and Information Technology - Proceedings of
                  the Second International Conference on Advances in Computing and Information
                  Technology {(ACITY)} July 13-15, 2012, Chennai, India - Volume 3},
  series       = {Advances in Intelligent Systems and Computing},
  volume       = {178},
  pages        = {649--656},
  publisher    = {Springer},
  year         = {2012},
  url          = {https://doi.org/10.1007/978-3-642-31600-5\_63},
  doi          = {10.1007/978-3-642-31600-5\_63},
  timestamp    = {Thu, 25 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/acity/DuttaGS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/abs-1211-5248,
  author       = {Chaitali Biswas Dutta and
                  Partha Garai and
                  Amitabha Sinha},
  title        = {Design Of {A} Reconfigurable {DSP} Processor With Bit Efficient Residue
                  Number System},
  journal      = {CoRR},
  volume       = {abs/1211.5248},
  year         = {2012},
  url          = {http://arxiv.org/abs/1211.5248},
  eprinttype    = {arXiv},
  eprint       = {1211.5248},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1211-5248.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/DasSG11,
  author       = {Malay Das and
                  Amitabha Sinha and
                  Nishant Kumar Giri},
  title        = {High speed residue number system {(RNS)} based {FIR} filter using
                  distributed arithmetic {(DA)}},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {39},
  number       = {5},
  pages        = {1--4},
  year         = {2011},
  url          = {https://doi.org/10.1145/2093339.2093341},
  doi          = {10.1145/2093339.2093341},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/DasSG11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/ChakrabortyS11,
  author       = {Anindita Chakraborty and
                  Amitabha Sinha},
  title        = {Conversion of binary to single-term triple base numbers for {DSP}
                  applications},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {39},
  number       = {5},
  pages        = {5--11},
  year         = {2011},
  url          = {https://doi.org/10.1145/2093339.2093342},
  doi          = {10.1145/2093339.2093342},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/ChakrabortyS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SinghaGS11,
  author       = {Satrughna Singha and
                  Aniruddha Ghosh and
                  Amitabha Sinha},
  title        = {A new architecture for {FPGA} based implementation of conversion of
                  binary to double base number system {(DBNS)} using parallel search
                  technique},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {39},
  number       = {5},
  pages        = {12--18},
  year         = {2011},
  url          = {https://doi.org/10.1145/2093339.2093343},
  doi          = {10.1145/2093339.2093343},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/sigarch/SinghaGS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MukherjeeS10,
  author       = {Manideepa Mukherjee and
                  Amitabha Sinha},
  title        = {A novel architecture for conversion of binary to single digit double
                  base numbers},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {38},
  number       = {5},
  pages        = {1--6},
  year         = {2010},
  url          = {https://doi.org/10.1145/1978907.1978909},
  doi          = {10.1145/1978907.1978909},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MukherjeeS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isspa/BanerjeeS10,
  author       = {Sharbari Banerjee and
                  Amitabha Sinha},
  title        = {A reconfigurable Digital Signal Processor using residue number system},
  booktitle    = {10th International Conference on Information Sciences, Signal Processing
                  and their Applications, {ISSPA} 2010, Kuala Lumpur, Malaysia, 10-13
                  May, 2010},
  pages        = {405--408},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSPA.2010.5605457},
  doi          = {10.1109/ISSPA.2010.5605457},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isspa/BanerjeeS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icetc/SahaS09,
  author       = {Amrita Saha and
                  Amitabha Sinha},
  title        = {An {FPGA} Based Architecture of a Novel Reconfigurable Radio Processor
                  for Software Defined Radio},
  booktitle    = {2009 International Conference on Education Technology and Computer,
                  {ICETC} 2009, Singapore, 17-20 April 2009},
  pages        = {45--49},
  publisher    = {{IEEE} Computer Society},
  year         = {2009},
  url          = {https://doi.org/10.1109/ICETC.2009.45},
  doi          = {10.1109/ICETC.2009.45},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/icetc/SahaS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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