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ORCIDBibTeX records: Chang-Ho Shin
@article{DBLP:journals/candie/BaeKSKSSLK23,
author = {Young{-}Mok Bae and
Young{-}Gwan Kim and
Jeong{-}Woo Seo and
Hyun{-}A Kim and
Chang{-}Ho Shin and
Jeong{-}Hwan Son and
Gyu{-}Ho Lee and
Kwang{-}Jae Kim},
title = {Detecting abnormal behavior of automatic test equipment using autoencoder
with event log data},
journal = {Comput. Ind. Eng.},
volume = {183},
pages = {109547},
year = {2023},
url = {https://doi.org/10.1016/j.cie.2023.109547},
doi = {10.1016/J.CIE.2023.109547},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/candie/BaeKSKSSLK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChiLPHJLKPKKPCL20,
author = {Hyung{-}Joon Chi and
Chang{-}Kyo Lee and
Junghwan Park and
Jin{-}Seok Heo and
Jaehoon Jung and
Dongkeon Lee and
Dae{-}Hyun Kim and
Dukha Park and
Kihan Kim and
Sang{-}Yun Kim and
Jinsol Park and
Hyunyoon Cho and
Sukhyun Lim and
YeonKyu Choi and
Youngil Lim and
Daesik Moon and
Geuntae Park and
Jin{-}Hun Jang and
Kyungho Lee and
Isak Hwang and
Cheol Kim and
Younghoon Son and
Gil{-}Young Kang and
Kiwon Park and
Seungjun Lee and
Su{-}Yeon Doo and
Chang{-}Ho Shin and
Byongwook Na and
Ji{-}Suk Kwon and
Kyung Ryun Kim and
Hye{-}In Choi and
Seouk{-}Kyu Choi and
Soobong Chang and
Wonil Bae and
Hyuck{-}Joon Kwon and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Kwang{-}Il Park and
Jung{-}Bae Lee},
title = {22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 {SDRAM} with a Hybrid-Bank Architecture
using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a
2nd generation 10nm {DRAM} Process},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {382--384},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062914},
doi = {10.1109/ISSCC19947.2020.9062914},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChiLPHJLKPKKPCL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimKDAKLKDLCPKP19,
author = {Young{-}Ju Kim and
Hye{-}Jung Kwon and
Su{-}Yeon Doo and
Min{-}Su Ahn and
Yong{-}Hun Kim and
Yong Jae Lee and
Dong{-}Seok Kang and
Sung{-}Geun Do and
Chang{-}Yong Lee and
Gun{-}hee Cho and
Jae{-}Koo Park and
Jae{-}Sung Kim and
Kyung{-}Bae Park and
Seung{-}Hoon Oh and
Sang{-}Yong Lee and
Ji{-}Hak Yu and
Ki{-}Hun Yu and
Chul{-}Hee Jeon and
Sang{-}Sun Kim and
Hyun{-}Soo Park and
Jeong{-}Woo Lee and
Seung{-}Hyun Cho and
Keon{-}Woo Park and
Yong{-}Jun Kim and
Young{-}Hun Seo and
Chang{-}Ho Shin and
ChanYong Lee and
Sam{-}Young Bang and
Youn{-}Sik Park and
Seouk{-}Kyu Choi and
Byung{-}Cheol Kim and
Gong{-}Heum Han and
Seung{-}Jun Bae and
Hyuk{-}Jun Kwon and
Jung{-}Hwan Choi and
Young{-}Soo Sohn and
Kwang{-}Il Park and
Seong{-}Jin Jang and
Gyo{-}Young Jin},
title = {A 16-Gb, 18-Gb/s/pin {GDDR6} {DRAM} With Per-Bit Trainable Single-Ended
{DFE} and PLL-Less Clocking},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {1},
pages = {197--209},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2883395},
doi = {10.1109/JSSC.2018.2883395},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimKDAKLKDLCPKP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimKDEKAKJDLKKP18,
author = {Young{-}Ju Kim and
Hye{-}Jung Kwon and
Su{-}Yeon Doo and
Yoon{-}Joo Eom and
Young{-}Sik Kim and
Min{-}Su Ahn and
Yong{-}Hun Kim and
Sang{-}Hoon Jung and
Sung{-}Geun Do and
Chang{-}Yong Lee and
Jae{-}Sung Kim and
Dong{-}Seok Kang and
Kyung{-}Bae Park and
Jung{-}Bum Shin and
Jong{-}Ho Lee and
Seung{-}Hoon Oh and
Sang{-}Yong Lee and
Ji{-}Hak Yu and
Ji{-}Suk Kwon and
Ki{-}Hun Yu and
Chul{-}Hee Jeon and
Sang{-}Sun Kim and
Min{-}Woo Won and
Gun{-}hee Cho and
Hyun{-}Soo Park and
Hyung{-}Kyu Kim and
Jeong{-}Woo Lee and
Seung{-}Hyun Cho and
Keon{-}Woo Park and
Jae{-}Koo Park and
Yong Jae Lee and
Yong{-}Jun Kim and
Young{-}Hun Seo and
Beob{-}Rae Cho and
Chang{-}Ho Shin and
ChanYong Lee and
YoungSeok Lee and
Yoon{-}Gue Song and
Sam{-}Young Bang and
Youn{-}Sik Park and
Seouk{-}Kyu Choi and
Byeong{-}Cheol Kim and
Gong{-}Heum Han and
Seung{-}Jun Bae and
Hyuk{-}Jun Kwon and
Jung{-}Hwan Choi and
Young{-}Soo Sohn and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {A 16Gb 18Gb/S/pin {GDDR6} {DRAM} with per-bit trainable single-ended
{DFE} and PLL-less clocking},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {204--206},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310255},
doi = {10.1109/ISSCC.2018.8310255},
timestamp = {Wed, 12 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimKDEKAKJDLKKP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChunCHKKYKLKYSC18,
author = {Ki Chul Chun and
Yonggyu Chu and
Jin{-}Seok Heo and
Tae{-}Sung Kim and
Soohwan Kim and
Hui{-}Kap Yang and
Mi{-}Jo Kim and
Chang{-}Kyo Lee and
Ju{-}Hwan Kim and
Hyunchul Yoon and
Chang{-}Ho Shin and
Sang{-}uhn Cha and
Hyung{-}Jin Kim and
Young{-}Sik Kim and
Kyungryun Kim and
Young{-}Ju Kim and
Won{-}Jun Choi and
Daesik Yim and
Inkyu Moon and
Young{-}Ju Kim and
Junha Lee and
Young Choi and
Yongmin Kwon and
Sung{-}Won Choi and
Jung{-}Wook Kim and
Yoon{-}Suk Park and
Woongdae Kang and
Jinil Chung and
Seunghyun Kim and
Yesin Ryu and
Seong{-}Jin Cho and
Hoon Shin and
Hangyun Jung and
Sanghyuk Kwon and
Kyuchang Kang and
Jongmyung Lee and
Yujung Song and
Youngjae Kim and
Eun{-}Ah Kim and
Kyung{-}Soo Ha and
Kyoung{-}Ho Kim and
Seok{-}Hun Hyun and
Seung{-}Bum Ko and
Jung{-}Hwan Choi and
Young{-}Soo Sohn and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {A 16Gb {LPDDR4X} {SDRAM} with an NBTI-tolerant circuit solution, an
{SWD} {PMOS} {GIDL} reduction technique, an adaptive gear-down scheme
and a metastable-free {DQS} aligner in a 10nm class {DRAM} process},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {206--208},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310256},
doi = {10.1109/ISSCC.2018.8310256},
timestamp = {Tue, 09 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChunCHKKYKLKYSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/JooBSKHA0KKKCSK16,
author = {Hye{-}Yoon Joo and
Seung{-}Jun Bae and
Young{-}Soo Sohn and
Young{-}Sik Kim and
Kyung{-}Soo Ha and
Min{-}Su Ahn and
Young{-}Ju Kim and
Yong{-}Jun Kim and
Ju{-}Hwan Kim and
Won{-}Jun Choi and
Chang{-}Ho Shin and
Soo Hwan Kim and
Byeong{-}Cheol Kim and
Seung{-}Bum Ko and
Kwang{-}Il Park and
Seong{-}Jin Jang and
Gyo{-}Young Jin},
title = {18.1 {A} 20nm 9Gb/s/pin 8Gb {GDDR5} {DRAM} with an {NBTI} monitor,
jitter reduction techniques and improved power distribution},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {314--315},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7418033},
doi = {10.1109/ISSCC.2016.7418033},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/JooBSKHA0KKKCSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/OhCCRLLLKJHKMBP14,
author = {Tae{-}Young Oh and
Hoeju Chung and
Young{-}Chul Cho and
Jang{-}Woo Ryu and
Kiwon Lee and
Changyoung Lee and
Jin{-}Il Lee and
Hyoung{-}Joo Kim and
Min{-}Soo Jang and
Gong{-}Heum Han and
Kihan Kim and
Daesik Moon and
Seung{-}Jun Bae and
Joon{-}Young Park and
Kyung{-}Soo Ha and
Jaewoong Lee and
Su{-}Yeon Doo and
Jung{-}Bum Shin and
Chang{-}Ho Shin and
Kiseok Oh and
Doo{-}Hee Hwang and
Taeseong Jang and
Chulsung Park and
Kwang{-}Il Park and
Jung{-}Bae Lee and
Joo{-}Sun Choi},
title = {25.1 {A} 3.2Gb/s/pin 8Gb 1.0V {LPDDR4} {SDRAM} with integrated {ECC}
engine for sub-1V {DRAM} core operation},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {430--431},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757500},
doi = {10.1109/ISSCC.2014.6757500},
timestamp = {Wed, 05 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/OhCCRLLLKJHKMBP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/OhSBPLCKKKKKKKKKLLSYCBYCMPHLPCJ11,
author = {Tae{-}Young Oh and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Min{-}Sang Park and
Ji{-}Hoon Lim and
Yong{-}Ki Cho and
Dae{-}Hyun Kim and
Dong{-}Min Kim and
Hye{-}Ran Kim and
Hyun{-}Joong Kim and
Jin{-}Hyun Kim and
Jin{-}Kook Kim and
Young{-}Sik Kim and
Byeong{-}Cheol Kim and
Sang{-}Hyup Kwak and
Jae{-}Hyung Lee and
Jae{-}Young Lee and
Chang{-}Ho Shin and
Yun{-}Seok Yang and
Beom{-}Sig Cho and
Sam{-}Young Bang and
Hyang{-}Ja Yang and
Young{-}Ryeol Choi and
Gil{-}Shin Moon and
Cheol{-}Goo Park and
Seokwon Hwang and
Jeong{-}Don Lim and
Kwang{-}Il Park and
Joo{-}Sun Choi and
Young{-}Hyun Jun},
title = {A 7 Gb/s/pin 1 Gbit {GDDR5} {SDRAM} With 2.5 ns Bank to Bank Active
Time and No Bank Group Restriction},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {107--118},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2085991},
doi = {10.1109/JSSC.2010.2085991},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/OhSBPLCKKKKKKKKKLLSYCBYCMPHLPCJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BaeSOKYKKSSPHKCKDKKCBPSMPKYLPCJ11,
author = {Seung{-}Jun Bae and
Young{-}Soo Sohn and
Tae{-}Young Oh and
Si{-}Hong Kim and
Yun{-}Seok Yang and
Dae{-}Hyun Kim and
Sang{-}Hyup Kwak and
Ho{-}Seok Seol and
Chang{-}Ho Shin and
Min{-}Sang Park and
Gong{-}Heom Han and
Byeong{-}Cheol Kim and
Yong{-}Ki Cho and
Hye{-}Ran Kim and
Su{-}Yeon Doo and
Young{-}Sik Kim and
Dong{-}Seok Kang and
Young{-}Ryeol Choi and
Sam{-}Young Bang and
Sun{-}Young Park and
Yong{-}Jae Shin and
Gil{-}Shin Moon and
Cheol{-}Goo Park and
Woo{-}Seop Kim and
Hyang{-}Ja Yang and
Jeong{-}Don Lim and
Kwang{-}Il Park and
Joo{-}Sun Choi and
Young{-}Hyun Jun},
title = {A 40nm 2Gb 7Gb/s/pin {GDDR5} {SDRAM} with a programmable {DQ} ordering
crosstalk equalizer and adjustable clock-tracking {BW}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {498--500},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746414},
doi = {10.1109/ISSCC.2011.5746414},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BaeSOKYKKSSPHKCKDKKCBPSMPKYLPCJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/OhSBPLCKKKKKKKKKLLSYCBYCMPHLPCJ10,
author = {Tae{-}Young Oh and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Min{-}Sang Park and
Ji{-}Hoon Lim and
Yong{-}Ki Cho and
Dae{-}Hyun Kim and
Dong{-}Min Kim and
Hye{-}Ran Kim and
Hyun{-}Joong Kim and
Jin{-}Hyun Kim and
Jin{-}Kook Kim and
Young{-}Sik Kim and
Byeong{-}Cheol Kim and
Sang{-}Hyup Kwak and
Jae{-}Hyung Lee and
Jae{-}Young Lee and
Chang{-}Ho Shin and
Yun{-}Seok Yang and
Beom{-}Sig Cho and
Sam{-}Young Bang and
Hyang{-}Ja Yang and
Young{-}Ryeol Choi and
Gil{-}Shin Moon and
Cheol{-}Goo Park and
Seokwon Hwang and
Jeong{-}Don Lim and
Kwang{-}Il Park and
Joo{-}Sun Choi and
Young{-}Hyun Jun},
title = {A 7Gb/s/pin {GDDR5} {SDRAM} with 2.5ns bank-to-bank active time and
no bank-group restriction},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {434--435},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433889},
doi = {10.1109/ISSCC.2010.5433889},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/OhSBPLCKKKKKKKKKLLSYCBYCMPHLPCJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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