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ORCIDBibTeX records: Ki-Tae Park
@article{DBLP:journals/jssc/KimKJKPPLPALKYY18,
author = {Chulbum Kim and
Doo{-}Hyun Kim and
Woopyo Jeong and
Hyun{-}Jin Kim and
Il{-}Han Park and
Hyun Wook Park and
Jong{-}Hoon Lee and
Jiyoon Park and
Yang{-}Lo Ahn and
Ji Young Lee and
Seungbum Kim and
Hyun{-}Jun Yoon and
Jaedoeg Yu and
Nayoung Choi and
Nahyun Kim and
Hwajun Jang and
Jonghoon Park and
Seunghwan Song and
Yongha Park and
Jinbae Bang and
Sanggi Hong and
Youngdon Choi and
Moosung Kim and
Hyunggon Kim and
Pansuk Kwak and
Jeong{-}Don Ihm and
Dae{-}Seok Byeon and
Jin{-}Yub Lee and
Ki{-}Tae Park and
Kyehyun Kyung},
title = {A 512-Gb 3-b/Cell 64-Stacked {WL} 3-D-NAND Flash Memory},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {124--133},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2731813},
doi = {10.1109/JSSC.2017.2731813},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimKJKPPLPALKYY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/NaSKP18,
author = {Wongi S. Na and
Dong{-}Woo Seo and
Byeong{-}Cheol Kim and
Ki{-}Tae Park},
title = {Effects of Applying Different Resonance Amplitude on the Performance
of the Impedance-Based Health Monitoring Technique Subjected to Damage},
journal = {Sensors},
volume = {18},
number = {7},
pages = {2267},
year = {2018},
url = {https://doi.org/10.3390/s18072267},
doi = {10.3390/S18072267},
timestamp = {Sat, 30 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/NaSKP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ParkLC18,
author = {Ki{-}Tae Park and
Yan Li and
Leland Chang},
title = {Session 20 overview: Flash-memory solutions: Memory subcommittee},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {334--335},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310320},
doi = {10.1109/ISSCC.2018.8310320},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ParkLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/CheongYWHKLCKKY18,
author = {Wooseong Cheong and
Chanho Yoon and
Seonghoon Woo and
Kyuwook Han and
Daehyun Kim and
Chulseung Lee and
Youra Choi and
Shine Kim and
Dongku Kang and
Geunyeong Yu and
Jaehong Kim and
Jaechun Park and
Ki{-}Whan Song and
Ki{-}Tae Park and
Sangyeun Cho and
Hwaseok Oh and
Daniel D. G. Lee and
Jin{-}Hyeok Choi and
Jaeheon Jeong},
title = {A flash memory controller for 15{\(\mu\)}s ultra-low-latency {SSD}
using high-speed 3D {NAND} flash with 3{\(\mu\)}s read time},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {338--340},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310322},
doi = {10.1109/ISSCC.2018.8310322},
timestamp = {Thu, 15 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/CheongYWHKLCKKY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeKKJJKLKPLKLL18,
author = {Seungjae Lee and
Chulbum Kim and
Minsu Kim and
Sung{-}Min Joe and
Joonsuc Jang and
Seungbum Kim and
Kangbin Lee and
Jisu Kim and
Jiyoon Park and
Hanjun Lee and
Min{-}Seok Kim and
Seonyong Lee and
SeonGeon Lee and
Jinbae Bang and
Dongjin Shin and
Hwajun Jang and
Deokwoo Lee and
Nahyun Kim and
Jonghoo Jo and
Jonghoon Park and
Sohyun Park and
Youngsik Rho and
Yongha Park and
Hojoon Kim and
Cheon An Lee and
Chungho Yu and
Young{-}Sun Min and
Moosung Kim and
Kyungmin Kim and
Seunghyun Moon and
Hyun{-}Jin Kim and
Youngdon Choi and
YoungHwan Ryu and
Jinwon Choi and
Minyeong Lee and
Jungkwan Kim and
Gyo Soo Choo and
Jeong{-}Don Lim and
Dae{-}Seok Byeon and
Ki{-}Whan Song and
Ki{-}Tae Park and
Kyehyun Kyung},
title = {A 1Tb 4b/cell 64-stacked-WL 3D {NAND} flash memory with 12MB/s program
throughput},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {340--342},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310323},
doi = {10.1109/ISSCC.2018.8310323},
timestamp = {Wed, 04 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LeeKKJJKLKPLKLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimP18,
author = {Jaeha Kim and
Ki{-}Tae Park},
title = {{EE6:} Can artificial intelligence replace my job? The dawn of a new
{IC} industry with {AI}},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {531--533},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310414},
doi = {10.1109/ISSCC.2018.8310414},
timestamp = {Wed, 14 Mar 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KimP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KangJKKCKRKLKLY17,
author = {Dongku Kang and
Woopyo Jeong and
Chulbum Kim and
Doo{-}Hyun Kim and
Yong{-}Sung Cho and
Kyung{-}Tae Kang and
Jinho Ryu and
Kyung{-}Min Kang and
Sungyeon Lee and
Wandong Kim and
Hanjun Lee and
Jaedoeg Yu and
Nayoung Choi and
Dong{-}Su Jang and
Cheon An Lee and
Young{-}Sun Min and
Moosung Kim and
Ansoo Park and
Jae{-}Ick Son and
In{-}Mo Kim and
Pansuk Kwak and
Bong{-}Kil Jung and
Doosub Lee and
Hyunggon Kim and
Jeong{-}Don Ihm and
Dae{-}Seok Byeon and
Jin{-}Yup Lee and
Ki{-}Tae Park and
Kyehyun Kyung},
title = {256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked {WL} Layers},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {210--217},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2604297},
doi = {10.1109/JSSC.2016.2604297},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KangJKKCKRKLKLY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KonoPC17,
author = {Takashi Kono and
Ki{-}Tae Park and
Leland Chang},
title = {Session 11 overview: Nonvolatile memory solutions},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {194--195},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870327},
doi = {10.1109/ISSCC.2017.7870327},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KonoPC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimCJPPKKLLKPAL17,
author = {Chulbum Kim and
Ji{-}Ho Cho and
Woopyo Jeong and
Il{-}Han Park and
Hyun Wook Park and
Doo{-}Hyun Kim and
Daewoon Kang and
Sunghoon Lee and
Ji{-}Sang Lee and
Wontae Kim and
Jiyoon Park and
Yang{-}Lo Ahn and
Jiyoung Lee and
Jong{-}Hoon Lee and
Seungbum Kim and
Hyun{-}Jun Yoon and
Jaedoeg Yu and
Nayoung Choi and
Yelim Kwon and
Nahyun Kim and
Hwajun Jang and
Jonghoon Park and
Seunghwan Song and
Yongha Park and
Jinbae Bang and
Sangki Hong and
Byunghoon Jeong and
Hyun{-}Jin Kim and
Chunan Lee and
Young{-}Sun Min and
Inryul Lee and
In{-}Mo Kim and
Sunghoon Kim and
Dongkyu Yoon and
Ki{-}Sung Kim and
Youngdon Choi and
Moosung Kim and
Hyunggon Kim and
Pansuk Kwak and
Jeong{-}Don Ihm and
Dae{-}Seok Byeon and
Jin{-}Yub Lee and
Ki{-}Tae Park and
Kyehyun Kyung},
title = {11.4 {A} 512Gb 3b/cell 64-stacked {WL} 3D {V-NAND} flash memory},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {202--203},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870331},
doi = {10.1109/ISSCC.2017.7870331},
timestamp = {Thu, 23 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KimCJPPKKLLKPAL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JeongIKNSCYKKPK16,
author = {Woopyo Jeong and
Jae{-}Woo Im and
Doo{-}Hyun Kim and
Sangwan Nam and
Dong{-}Kyo Shim and
Myung{-}Hoon Choi and
Hyun{-}Jun Yoon and
Dae{-}Han Kim and
Youse Kim and
Hyun Wook Park and
Dong{-}Hun Kwak and
Sang{-}Won Park and
Seok{-}Min Yoon and
Wook{-}Ghee Hahn and
Jinho Ryu and
Sang{-}Won Shim and
Kyung{-}Tae Kang and
Jeong{-}Don Ihm and
In{-}Mo Kim and
Doosub Lee and
Ji{-}Ho Cho and
Moosung Kim and
Jae{-}hoon Jang and
Sang{-}Won Hwang and
Dae{-}Seok Byeon and
Hyang{-}Ja Yang and
Ki{-}Tae Park and
Kyehyun Kyung and
Jeong{-}Hyuk Choi},
title = {A 128 Gb 3b/cell {V-NAND} Flash Memory With 1 Gb/s {I/O} Rate},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {204--212},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2474117},
doi = {10.1109/JSSC.2015.2474117},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JeongIKNSCYKKPK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KangJKKCKRKLKLY16,
author = {Dongku Kang and
Woopyo Jeong and
Chulbum Kim and
Doo{-}Hyun Kim and
Yong{-}Sung Cho and
Kyung{-}Tae Kang and
Jinho Ryu and
Kyung{-}Min Kang and
Sungyeon Lee and
Wandong Kim and
Hanjun Lee and
Jaedoeg Yu and
Nayoung Choi and
Dong{-}Su Jang and
Jeong{-}Don Ihm and
Doo{-}Gon Kim and
Young{-}Sun Min and
Moosung Kim and
Ansoo Park and
Jae{-}Ick Son and
In{-}Mo Kim and
Pansuk Kwak and
Bong{-}Kil Jung and
Doosub Lee and
Hyunggon Kim and
Hyang{-}Ja Yang and
Dae{-}Seok Byeon and
Ki{-}Tae Park and
Kyehyun Kyung and
Jeong{-}Hyuk Choi},
title = {7.1 256Gb 3b/cell {V-NAND} flash memory with 48 stacked {WL} layers},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {130--131},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417941},
doi = {10.1109/ISSCC.2016.7417941},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KangJKKCKRKLKLY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeLPPYKLKLKCCY16,
author = {Seungjae Lee and
Jin{-}Yub Lee and
Il{-}Han Park and
Jong{-}Yeol Park and
Sung{-}Won Yun and
Minsu Kim and
Jong{-}Hoon Lee and
Min{-}Seok Kim and
Kangbin Lee and
Taeeun Kim and
Byungkyu Cho and
Dooho Cho and
Sangbum Yun and
Jung{-}No Im and
Hyejin Yim and
Kyung{-}Hwa Kang and
Suchang Jeon and
Sungkyu Jo and
Yang{-}Lo Ahn and
Sung{-}Min Joe and
Suyong Kim and
Deok{-}kyun Woo and
Jiyoon Park and
Hyun Wook Park and
Youngmin Kim and
Jonghoon Park and
Yongsu Choi and
Makoto Hirano and
Jeong{-}Don Ihm and
Byunghoon Jeong and
Seon{-}Kyoo Lee and
Moosung Kim and
Hokil Lee and
Sungwhan Seo and
Hongsoo Jeon and
Chan{-}ho Kim and
Hyunggon Kim and
Jintae Kim and
Yongsik Yim and
Hoosung Kim and
Dae{-}Seok Byeon and
Hyang{-}Ja Yang and
Ki{-}Tae Park and
Kyehyun Kyung and
Jeong{-}Hyuk Choi},
title = {7.5 {A} 128Gb 2b/cell {NAND} flash memory in 14nm technology with
tPROG=640{\(\mathrm{\mu}\)}s and 800MB/s {I/O} rate},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {138--139},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417945},
doi = {10.1109/ISSCC.2016.7417945},
timestamp = {Wed, 04 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LeeLPPYKLKLKCCY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jccee/YunSJKP15,
author = {Hae{-}Bum Yun and
Ganesh Sundaresan and
Youngwoo Jung and
Jong{-}Woo Kim and
Ki{-}Tae Park},
title = {Novel Pattern Detection Algorithm for Monitoring Phase Change of Moisture
on Concrete Pavement Using Surface Temperature Data},
journal = {J. Comput. Civ. Eng.},
volume = {29},
number = {2},
year = {2015},
url = {https://doi.org/10.1061/(asce)cp.1943-5487.0000330},
doi = {10.1061/(ASCE)CP.1943-5487.0000330},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jccee/YunSJKP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ParkNKKLCCKKKPSKPLYKSARKYKSBCHKCK15,
author = {Ki{-}Tae Park and
Sangwan Nam and
Dae{-}Han Kim and
Pansuk Kwak and
Doosub Lee and
Yoon{-}Hee Choi and
Myung{-}Hoon Choi and
Dong{-}Hun Kwak and
Doo{-}Hyun Kim and
Minsu Kim and
Hyun Wook Park and
Sang{-}Won Shim and
Kyung{-}Min Kang and
Sang{-}Won Park and
Kangbin Lee and
Hyun{-}Jun Yoon and
Kuihan Ko and
Dong{-}Kyo Shim and
Yang{-}Lo Ahn and
Jinho Ryu and
Donghyun Kim and
Kyunghwa Yun and
Joonsoo Kwon and
Seunghoon Shin and
Dae{-}Seok Byeon and
Kihwan Choi and
Jin{-}Man Han and
Kyehyun Kyung and
Jeong{-}Hyuk Choi and
Kinam Kim},
title = {Three-Dimensional 128 Gb {MLC} Vertical nand Flash Memory With 24-WL
Stacked Layers and 50 MB/s High-Speed Programming},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {204--213},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2352293},
doi = {10.1109/JSSC.2014.2352293},
timestamp = {Tue, 13 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ParkNKKLCCKKKPSKPLYKSARKYKSBCHKCK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ImJKNSCYKKPKPYH15,
author = {Jae{-}Woo Im and
Woopyo Jeong and
Doo{-}Hyun Kim and
Sangwan Nam and
Dong{-}Kyo Shim and
Myung{-}Hoon Choi and
Hyun{-}Jun Yoon and
Dae{-}Han Kim and
Youse Kim and
Hyun Wook Park and
Dong{-}Hun Kwak and
Sang{-}Won Park and
Seok{-}Min Yoon and
Wook{-}Ghee Hahn and
Jinho Ryu and
Sang{-}Won Shim and
Kyung{-}Tae Kang and
Sung{-}Ho Choi and
Jeong{-}Don Ihm and
Young{-}Sun Min and
In{-}Mo Kim and
Doosub Lee and
Ji{-}Ho Cho and
Ohsuk Kwon and
Ji{-}Sang Lee and
Moosung Kim and
Sang{-}Hyun Joo and
Jae{-}hoon Jang and
Sang{-}Won Hwang and
Dae{-}Seok Byeon and
Hyang{-}Ja Yang and
Ki{-}Tae Park and
Kyehyun Kyung and
Jeong{-}Hyuk Choi},
title = {7.2 {A} 128Gb 3b/cell {V-NAND} flash memory with 1Gb/s {I/O} rate},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062960},
doi = {10.1109/ISSCC.2015.7062960},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ImJKNSCYKKPKPYH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimLLNSKYSLRKKP15,
author = {Hyun{-}Jin Kim and
Jeong{-}Don Lim and
Jang{-}Woo Lee and
Dae{-}Hoon Na and
Joon{-}Ho Shin and
Chae{-}Hoon Kim and
Seungwoo Yu and
Ji{-}Yeon Shin and
Seon{-}Kyoo Lee and
Devraj Rajagopal and
Sang{-}Tae Kim and
Kyeong{-}Tae Kang and
Jeong{-}Joon Park and
Yongjin Kwon and
Min{-}Jae Lee and
Sunghoon Kim and
Seunghoon Shin and
Hyunggon Kim and
Jin{-}Tae Kim and
Ki{-}Sung Kim and
Han{-}Sung Joo and
Chanjin Park and
Jae{-}Hwan Kim and
Man{-}Joong Lee and
Do{-}Kook Kim and
Hyang{-}Ja Yang and
Dae{-}Seok Byeon and
Ki{-}Tae Park and
Kyehyun Kyung and
Jeong{-}Hyuk Choi},
title = {7.6 1GB/s 2Tb {NAND} flash multi-chip package with frequency-boosting
interface chip},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062964},
doi = {10.1109/ISSCC.2015.7062964},
timestamp = {Sun, 30 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimLLNSKYSLRKKP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ParkHKNCKKLCKCK14,
author = {Ki{-}Tae Park and
Jin{-}Man Han and
Dae{-}Han Kim and
Sangwan Nam and
Kihwan Choi and
Minsu Kim and
Pansuk Kwak and
Doosub Lee and
Yoon{-}Hee Choi and
Kyung{-}Min Kang and
Myung{-}Hoon Choi and
Dong{-}Hun Kwak and
Hyun Wook Park and
Sang{-}Won Shim and
Hyun{-}Jun Yoon and
Doo{-}Hyun Kim and
Sang{-}Won Park and
Kangbin Lee and
Kuihan Ko and
Dong{-}Kyo Shim and
Yang{-}Lo Ahn and
Jeunghwan Park and
Jinho Ryu and
Donghyun Kim and
Kyunghwa Yun and
Joonsoo Kwon and
Seunghoon Shin and
Dongkyu Youn and
Won{-}Tae Kim and
Taehyun Kim and
Sung{-}Jun Kim and
Sungwhan Seo and
Hyunggon Kim and
Dae{-}Seok Byeon and
Hyang{-}Ja Yang and
Moosung Kim and
Myong{-}Seok Kim and
Jinseon Yeon and
Jae{-}hoon Jang and
Han{-}Soo Kim and
Woonkyung Lee and
Duheon Song and
Sungsoo Lee and
Kyehyun Kyung and
Jeong{-}Hyuk Choi},
title = {19.5 Three-dimensional 128Gb {MLC} vertical {NAND} Flash-memory with
24-WL stacked layers and 50MB/s high-speed programming},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {334--335},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757458},
doi = {10.1109/ISSCC.2014.6757458},
timestamp = {Wed, 14 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ParkHKNCKKLCKCK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShinSJKYCKPYSCS12,
author = {Seung{-}Hwan Shin and
Dong{-}Kyo Shim and
Jaeyong Jeong and
Ohsuk Kwon and
Sangyong Yoon and
Myung{-}Hoon Choi and
Tae{-}Young Kim and
Hyun Wook Park and
Hyun{-}Jun Yoon and
Youngsun Song and
Yoon{-}Hee Choi and
Sang{-}Won Shim and
Yang{-}Lo Ahn and
Ki{-}Tae Park and
Jin{-}Man Han and
Kyehyun Kyung and
Young{-}Hyun Jun},
title = {A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s
high performance {TLC} {NAND} flash memory},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {132--133},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243825},
doi = {10.1109/VLSIC.2012.6243825},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShinSJKYCKPYSCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ParkKYCKKKCSSPLELKLKKYKSSSKHKLLJ11,
author = {Ki{-}Tae Park and
Ohsuk Kwon and
Sangyong Yoon and
Myung{-}Hoon Choi and
In{-}Mo Kim and
Bo{-}Geun Kim and
Min{-}Seok Kim and
Yoon{-}Hee Choi and
Seung{-}Hwan Shin and
Youngson Song and
Joo{-}Yong Park and
Jae{-}Eun Lee and
Chang{-}Gyu Eun and
Ho{-}Chul Lee and
Hyeong{-}Jun Kim and
Jun{-}Hee Lee and
Jong{-}Young Kim and
Tae{-}Min Kweon and
Hyun{-}Jun Yoon and
Taehyun Kim and
Dong{-}Kyo Shim and
Jongsun Sel and
Ji{-}Yeon Shin and
Pansuk Kwak and
Jin{-}Man Han and
Keon{-}Soo Kim and
Sungsoo Lee and
Youngho Lim and
Tae{-}Sung Jung},
title = {A 7MB/s 64Gb 3-bit/cell {DDR} {NAND} flash memory in 20nm-node technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {212--213},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746287},
doi = {10.1109/ISSCC.2011.5746287},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ParkKYCKKKCSSPLELKLKKYKSSSKHKLLJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KangPSLSL10,
author = {Myounggon Kang and
Ki{-}Tae Park and
Youngsun Song and
Sungsoo Lee and
Yunheub Song and
Youngho Lim},
title = {A Low Power and Area Scalable High Voltage Switch Technique for Low
Operation Voltage in {MLC} {NAND} Flash Memory},
journal = {{IEICE} Trans. Electron.},
volume = {93-C},
number = {2},
pages = {182--186},
year = {2010},
url = {https://doi.org/10.1587/transele.E93.C.182},
doi = {10.1587/TRANSELE.E93.C.182},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KangPSLSL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/SongPKSLLS10,
author = {Youngsun Song and
Ki{-}Tae Park and
Myounggon Kang and
Yunheub Song and
Sungsoo Lee and
Youngho Lim and
Kang{-}Deog Suh},
title = {Boosted Bit Line Program Scheme for Low Operating Voltage {MLC} {NAND}
Flash Memory},
journal = {{IEICE} Trans. Electron.},
volume = {93-C},
number = {3},
pages = {423--425},
year = {2010},
url = {https://doi.org/10.1587/transele.E93.C.423},
doi = {10.1587/TRANSELE.E93.C.423},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/SongPKSLLS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ParkSKLLSC10,
author = {Ki{-}Tae Park and
Youngsun Song and
Myounggon Kang and
Sungsoo Lee and
Youngho Lim and
Kang{-}Deog Suh and
Chilhee Chung},
title = {Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control
for High Program Inhibition in {MLC} {NAND} Flash Memories},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {10},
pages = {2165--2172},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2062311},
doi = {10.1109/JSSC.2010.2062311},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ParkSKLLSC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimPPKKKLPKCLSLYKYKLKLC10,
author = {Hyunggon Kim and
Jung{-}Hoon Park and
Ki{-}Tae Park and
Pansuk Kwak and
Ohsuk Kwon and
Chulbum Kim and
Younyeol Lee and
Sangsoo Park and
Kyungmin Kim and
Doohyun Cho and
Juseok Lee and
Jungho Song and
Soowoong Lee and
Hyukjun Yoo and
Sanglok Kim and
Seungwoo Yu and
Sungjun Kim and
Sungsoo Lee and
Kyehyun Kyung and
Yong{-}Ho Lim and
Chilhee Chung},
title = {A 159mm\({}^{\mbox{2}}\) 32nm 32Gb {MLC} NAND-flash memory with 200MB/s
asynchronous {DDR} interface},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {442--443},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433912},
doi = {10.1109/ISSCC.2010.5433912},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KimPPKKKLPKCLSLYKYKLKLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ParkKHKCJSJKLJK09,
author = {Ki{-}Tae Park and
Myounggon Kang and
Soonwook Hwang and
Doo{-}Gon Kim and
Hoosung Cho and
Youngwook Jeong and
Yong{-}Il Seo and
Jae{-}hoon Jang and
Hansoo Kim and
Yeong{-}Taek Lee and
Soon{-}Moon Jung and
Changhyun Kim},
title = {A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked
Multi-Level {NAND} Flash Memory With Shared Bit-Line Structure},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {208--216},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2006437},
doi = {10.1109/JSSC.2008.2006437},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ParkKHKCJSJKLJK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ParkKKHCLKK08,
author = {Ki{-}Tae Park and
Myounggon Kang and
Doogon Kim and
Soonwook Hwang and
Byung Yong Choi and
Yeong{-}Taek Lee and
Changhyun Kim and
Kinam Kim},
title = {A Zeroing Cell-to-Cell Interference Page Architecture With Temporary
{LSB} Storing and Parallel {MSB} Program Scheme for {MLC} {NAND} Flash
Memories},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {4},
pages = {919--928},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2008.917558},
doi = {10.1109/JSSC.2008.917558},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ParkKKHCLKK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ParkKHKCJSJKJLKL08,
author = {Ki{-}Tae Park and
Doo{-}Gon Kim and
Soonwook Hwang and
Myounggon Kang and
Hoosung Cho and
Youngwook Jeong and
Yong{-}Il Seo and
Jae{-}hoon Jang and
Hansoo Kim and
Soon{-}Moon Jung and
Yeong{-}Taek Lee and
Changhyun Kim and
Won{-}Seong Lee},
title = {A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level {NAND} Flash Memory
with Shared Bitline Structure},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {510--511},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523281},
doi = {10.1109/ISSCC.2008.4523281},
timestamp = {Mon, 22 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ParkKHKCJSJKJLKL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/WonKJPCK03,
author = {Hyo{-}Sig Won and
Kyo{-}Sun Kim and
Kwang{-}Ok Jeong and
Ki{-}Tae Park and
Kyu{-}Myung Choi and
Jeong{-}Taek Kong},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {An {MTCMOS} design methodology and its application to mobile computing},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {110--115},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871536},
doi = {10.1145/871506.871536},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/WonKJPCK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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