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ORCIDBibTeX records: Vassilis Paliouras
@article{DBLP:journals/tetc/PapachatzopoulosP23,
author = {Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Path-Based Delay Variation Models for Parallel-Prefix Adders},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {11},
number = {3},
pages = {689--705},
year = {2023},
url = {https://doi.org/10.1109/TETC.2023.3242555},
doi = {10.1109/TETC.2023.3242555},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tetc/PapachatzopoulosP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/PapachatzopoulosP23a,
author = {Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {11},
number = {4},
pages = {1002--1017},
year = {2023},
url = {https://doi.org/10.1109/TETC.2023.3299516},
doi = {10.1109/TETC.2023.3299516},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tetc/PapachatzopoulosP23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/KouretasPS23,
author = {Ioannis Kouretas and
Vassilis Paliouras and
Thanos Stouraitis},
title = {Modified Logarithmic Multiplication Approximation for Machine Learning},
booktitle = {5th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2023, Hangzhou, China, June 11-13, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/AICAS57966.2023.10168664},
doi = {10.1109/AICAS57966.2023.10168664},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aicas/KouretasPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/SakellariouPKSS23,
author = {Vasilis Sakellariou and
Vassilis Paliouras and
Ioannis Kouretas and
Hani H. Saleh and
Thanos Stouraitis},
title = {A multiplier-Free RNS-Based {CNN} accelerator exploiting bit-Level
sparsity},
booktitle = {30th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2023, Portland,
OR, USA, September 4-6, 2023},
pages = {101},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ARITH58626.2023.00037},
doi = {10.1109/ARITH58626.2023.00037},
timestamp = {Mon, 08 Apr 2024 20:48:38 +0200},
biburl = {https://dblp.org/rec/conf/arith/SakellariouPKSS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/KavvousanosSKPS23,
author = {Emmanouil Kavvousanos and
Vasilis Sakellariou and
Ioannis Kouretas and
Vassilis Paliouras and
Thanos Stouraitis},
title = {Improving Residue-Level Sparsity in RNS-based Neural Network Hardware
Accelerators via Regularization},
booktitle = {30th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2023, Portland,
OR, USA, September 4-6, 2023},
pages = {102--109},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ARITH58626.2023.00020},
doi = {10.1109/ARITH58626.2023.00020},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arith/KavvousanosSKPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/KompostiotisVP23,
author = {Dimitris Kompostiotis and
Dimitris Vordonis and
Vassilis Paliouras},
title = {Received Power Maximization with Practical Phase-Dependent Amplitude
Response in RIS-Aided {OFDM} Wireless Communications},
booktitle = {{IEEE} International Conference on Acoustics, Speech and Signal Processing
{ICASSP} 2023, Rhodes Island, Greece, June 4-10, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICASSP49357.2023.10095408},
doi = {10.1109/ICASSP49357.2023.10095408},
timestamp = {Fri, 10 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icassp/KompostiotisVP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icc/KompostiotisVPA23,
author = {Dimitris Kompostiotis and
Dimitris Vordonis and
Vassilis Paliouras and
George C. Alexandropoulos},
title = {Secrecy Rate Maximization in RIS-Enabled {OFDM} Wireless Communications:
The Circuit-Based Reflection Model Case},
booktitle = {{IEEE} International Conference on Communications, {ICC} 2023 - Workshops,
Rome, Italy, May 28 - June 1, 2023},
pages = {1529--1534},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCWorkshops57953.2023.10283801},
doi = {10.1109/ICCWORKSHOPS57953.2023.10283801},
timestamp = {Thu, 02 Nov 2023 17:09:45 +0100},
biburl = {https://dblp.org/rec/conf/icc/KompostiotisVPA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ElKadyFP23,
author = {Alexander El{-}Kady and
Apostolos P. Fournaris and
Vassilis Paliouras},
title = {Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based
High-Level Synthesis},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323770},
doi = {10.1109/ICCAD57390.2023.10323770},
timestamp = {Wed, 03 Jan 2024 08:34:26 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ElKadyFP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KavvousanosKPS23,
author = {Emmanouil Kavvousanos and
Ioannis Kouretas and
Vassilis Paliouras and
Thanos Stouraitis},
title = {A Regularization Approach to Maximize Common Sub-Expressions in Neural
Network Weights},
booktitle = {30th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2023, Istanbul, Turkey, December 4-7, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICECS58634.2023.10382719},
doi = {10.1109/ICECS58634.2023.10382719},
timestamp = {Thu, 18 Jan 2024 08:27:11 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/KavvousanosKPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Papachatzopoulos22,
author = {Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Sensitivity to Threshold Voltage Variations of Exact and Incomplete
Prefix Addition Trees},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {924--928},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937629},
doi = {10.1109/ISCAS48785.2022.9937629},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/Papachatzopoulos22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SakellariouPKSS22,
author = {Vasilis Sakellariou and
Vassilis Paliouras and
Ioannis Kouretas and
Hani H. Saleh and
Thanos Stouraitis},
title = {A High-performance {RNS} {LSTM} block},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {1264--1268},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937633},
doi = {10.1109/ISCAS48785.2022.9937633},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SakellariouPKSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KavvousanosP22,
author = {Emmanouil Kavvousanos and
Vassilis Paliouras},
title = {A Low-Latency Syndrome-based Deep Learning Decoder Architecture and
its {FPGA} Implementation},
booktitle = {11th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2022, Bremen, Germany, June 8-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MOCAST54814.2022.9837752},
doi = {10.1109/MOCAST54814.2022.9837752},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/KavvousanosP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/SpanosP22,
author = {Thodoris Spanos and
Vassilis Paliouras},
title = {Hardware Aspects of Iterative Receivers for {V2X} Applications},
booktitle = {11th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2022, Bremen, Germany, June 8-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MOCAST54814.2022.9837705},
doi = {10.1109/MOCAST54814.2022.9837705},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/SpanosP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/VordonisKP22,
author = {Dimitris Vordonis and
Dimitris Kompostiotis and
Vassilis Paliouras},
title = {Reconfigurable Intelligent Surface-Aided {OFDM} Wireless Communications:
Hardware Aspects of Reflection Optimization Methods},
booktitle = {11th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2022, Bremen, Germany, June 8-10, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MOCAST54814.2022.9837634},
doi = {10.1109/MOCAST54814.2022.9837634},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/VordonisKP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/El-KadyFHP22,
author = {Alexander El{-}Kady and
Apostolos P. Fournaris and
Evangelos Haleplidis and
Vassilis Paliouras},
title = {High-Level Synthesis design approach for Number-Theoretic Multiplier},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939657},
doi = {10.1109/VLSI-SOC54400.2022.9939657},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/El-KadyFHP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ojcs/VordonisP21,
author = {Dimitris Vordonis and
Vassilis Paliouras},
title = {Hardware Implementation and Performance Analysis of Improved Sphere
Decoder in Spatially Correlated Massive {MIMO} Channels},
journal = {{IEEE} Open J. Commun. Soc.},
volume = {2},
pages = {2680--2694},
year = {2021},
url = {https://doi.org/10.1109/OJCOMS.2021.3133014},
doi = {10.1109/OJCOMS.2021.3133014},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ojcs/VordonisP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/Dimitrakopoulos21,
author = {Giorgos Dimitrakopoulos and
Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Sum Propagate Adders},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {9},
number = {3},
pages = {1479--1488},
year = {2021},
url = {https://doi.org/10.1109/TETC.2021.3068729},
doi = {10.1109/TETC.2021.3068729},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tetc/Dimitrakopoulos21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahdiKP21,
author = {Ahmed Mahdi and
Nikos Kanistras and
Vassilis Paliouras},
title = {A Multirate Fully Parallel {LDPC} Encoder for the {IEEE} 802.11n/ac/ax
{QC-LDPC} Codes Based on Reduced Complexity {XOR} Trees},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {51--64},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3034046},
doi = {10.1109/TVLSI.2020.3034046},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahdiKP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/Dimitrakopoulos21,
author = {Giorgos Dimitrakopoulos and
Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Sum Propagate Adders},
booktitle = {28th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2021, Lyngby,
Denmark, June 14-16, 2021},
pages = {110},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ARITH51176.2021.00030},
doi = {10.1109/ARITH51176.2021.00030},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/Dimitrakopoulos21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KavvousanosP21,
author = {Emmanouil Kavvousanos and
Vassilis Paliouras},
title = {Optimizing Deep Learning Decoders for {FPGA} Implementation},
booktitle = {31st International Conference on Field-Programmable Logic and Applications,
{FPL} 2021, Dresden, Germany, August 30 - Sept. 3, 2021},
pages = {271--272},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FPL53798.2021.00053},
doi = {10.1109/FPL53798.2021.00053},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KavvousanosP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/ChytasP21,
author = {Dimitris Chytas and
Vassilis Paliouras},
title = {A 5G-code based iterative Non-Binary {LDPC} decoder},
booktitle = {28th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2021, Dubai, United Arab Emirates, November 28 -
Dec. 1, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICECS53924.2021.9665548},
doi = {10.1109/ICECS53924.2021.9665548},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/ChytasP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SakellariouPKSS21,
author = {Vasilis Sakellariou and
Vassilis Paliouras and
Ioannis Kouretas and
Hani H. Saleh and
Thanos Stouraitis},
title = {On Reducing the Number of Multiplications in RNS-based {CNN} Accelerators},
booktitle = {28th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2021, Dubai, United Arab Emirates, November 28 -
Dec. 1, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICECS53924.2021.9665461},
doi = {10.1109/ICECS53924.2021.9665461},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/SakellariouPKSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AndriakopoulosP21,
author = {Chris Andriakopoulos and
Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {A Novel Stochastic Polar Architecture for All-Digital Transmission},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401733},
doi = {10.1109/ISCAS51556.2021.9401733},
timestamp = {Fri, 02 Jul 2021 12:26:54 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AndriakopoulosP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KouretasP21,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Simplified Hardware Implementation of Memoryless Dot Product for Neural
Network Inference},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401625},
doi = {10.1109/ISCAS51556.2021.9401625},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/KouretasP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SakellariouP21,
author = {Vasilis Sakellariou and
Vassilis Paliouras},
title = {An {FPGA} Accelerator for Spiking Neural Network Simulation and Training},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401317},
doi = {10.1109/ISCAS51556.2021.9401317},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SakellariouP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KouretasP21,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Hardware Aspects of Parallel Neural Network Implementation},
booktitle = {10th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2021, Thessaloniki, Greece, July 5-7, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MOCAST52088.2021.9493365},
doi = {10.1109/MOCAST52088.2021.9493365},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mocast/KouretasP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/El-KadyFTHP21,
author = {Alexander El{-}Kady and
Apostolos P. Fournaris and
Thanasis Tsakoulis and
Evangelos Haleplidis and
Vassilis Paliouras},
title = {High-Level Synthesis design approach for Number-Theoretic Transform
Implementations},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9607003},
doi = {10.1109/VLSI-SOC53125.2021.9607003},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/El-KadyFTHP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ArnoldPK20,
author = {Mark G. Arnold and
Vassilis Paliouras and
Ioannis Kouretas},
title = {Implementing the Residue Logarithmic Number System Using Interpolation
and Cotransformation},
journal = {{IEEE} Trans. Computers},
volume = {69},
number = {12},
pages = {1719--1732},
year = {2020},
url = {https://doi.org/10.1109/TC.2019.2930514},
doi = {10.1109/TC.2019.2930514},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/ArnoldPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/Papachatzopoulos20,
author = {Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Maximum Delay Models for Parallel-Prefix Adders in the Presence of
Threshold Voltage Variations},
booktitle = {27th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2020, Portland,
OR, USA, June 7-10, 2020},
pages = {88--95},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ARITH48897.2020.00021},
doi = {10.1109/ARITH48897.2020.00021},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arith/Papachatzopoulos20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/globecom/KavvousanosP20,
author = {Emmanouil Kavvousanos and
Vassilis Paliouras},
title = {An Iterative Approach to Syndrome-based Deep Learning Decoding},
booktitle = {{IEEE} Globecom Workshops, {GLOBECOM} Workshops 2020, Virtual Event,
Taiwan, December 7-11, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/GCWkshps50303.2020.9367553},
doi = {10.1109/GCWKSHPS50303.2020.9367553},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/globecom/KavvousanosP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/ChytasP20,
author = {Dimitris Chytas and
Vassilis Paliouras},
title = {Approximate Sorting Check Node Processing in Non-Binary {LDPC} Decoders},
booktitle = {27th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2020, Glasgow, Scotland, UK, November 23-25, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICECS49266.2020.9294934},
doi = {10.1109/ICECS49266.2020.9294934},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/ChytasP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Papachatzopoulos20,
author = {Kleanthis Papachatzopoulos and
Chris Andriakopoulos and
Vassilis Paliouras},
title = {Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180770},
doi = {10.1109/ISCAS45731.2020.9180770},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Papachatzopoulos20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Papachatzopoulos19,
author = {Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {7},
pages = {2546--2559},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2900151},
doi = {10.1109/TCSI.2019.2900151},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Papachatzopoulos19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/ArnoldKPC19,
author = {Mark G. Arnold and
Ioannis Kouretas and
Vassilis Paliouras and
John R. Cowles},
editor = {Naofumi Takagi and
Sylvie Boldo and
Martin Langhammer},
title = {Under- and Overflow Detection in the Residue Logarithmic Number System},
booktitle = {26th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2019, Kyoto,
Japan, June 10-12, 2019},
pages = {112--115},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ARITH.2019.00030},
doi = {10.1109/ARITH.2019.00030},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arith/ArnoldKPC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KaragianniP19,
author = {Konstantina Karagianni and
Vassilis Paliouras},
title = {Versatile Hardware Generation of alpha-Stable Noise for {PLC} Channel
Emulation},
booktitle = {26th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2019, Genoa, Italy, November 27-29, 2019},
pages = {646--649},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICECS46596.2019.8965000},
doi = {10.1109/ICECS46596.2019.8965000},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/KaragianniP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KouretasP19,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Simplified Hardware Implementation of the Softmax Activation Function},
booktitle = {8th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2019, Thessaloniki, Greece, May 13-15, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MOCAST.2019.8741677},
doi = {10.1109/MOCAST.2019.8741677},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/KouretasP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/KavvousanosP19,
author = {Emmanouil Kavvousanos and
Vassilis Paliouras},
editor = {Jari Nurmi and
Peeter Ellervee and
Kari Halonen and
Juha R{\"{o}}ning},
title = {Hardware Implementation Aspects of a Syndrome-based Neural Network
Decoder for {BCH} Codes},
booktitle = {2019 {IEEE} Nordic Circuits and Systems Conference, {NORCAS} 2019:
{NORCHIP} and International Symposium of System-on-Chip (SoC), Helsinki,
Finland, October 29-30, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NORCHIP.2019.8906946},
doi = {10.1109/NORCHIP.2019.8906946},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/norchip/KavvousanosP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/VordonisP19,
author = {Dimitris Vordonis and
Vassilis Paliouras},
editor = {Jari Nurmi and
Peeter Ellervee and
Kari Halonen and
Juha R{\"{o}}ning},
title = {Sphere Decoder for Massive {MIMO} Systems},
booktitle = {2019 {IEEE} Nordic Circuits and Systems Conference, {NORCAS} 2019:
{NORCHIP} and International Symposium of System-on-Chip (SoC), Helsinki,
Finland, October 29-30, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NORCHIP.2019.8906929},
doi = {10.1109/NORCHIP.2019.8906929},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/norchip/VordonisP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ArnoldKPM19,
author = {Mark G. Arnold and
Ioannis Kouretas and
Vassilis Paliouras and
Austin Morgan},
title = {One-Hot Residue Logarithmic Number Systems},
booktitle = {29th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2019, Rhodes, Greece, July 1-3, 2019},
pages = {97--102},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/PATMOS.2019.8862159},
doi = {10.1109/PATMOS.2019.8862159},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ArnoldKPM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KouretasP19,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Radix-3 low-complexity modulo-M multipliers},
booktitle = {29th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2019, Rhodes, Greece, July 1-3, 2019},
pages = {107--112},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/PATMOS.2019.8862036},
doi = {10.1109/PATMOS.2019.8862036},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KouretasP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Papachatzopoulos18,
author = {Kleanthis Papachatzopoulos and
Vassilis Paliouras},
title = {Low-Power Addition With Borrow-Save Adders Under Threshold Voltage
Variability},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {5},
pages = {572--576},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2018.2821905},
doi = {10.1109/TCSII.2018.2821905},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Papachatzopoulos18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SakellariouP18,
author = {Panagiotis Sakellariou and
Vassilis Paliouras},
title = {Reconfigurable RO-Path Delay Sensor},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {12},
pages = {2027--2031},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2018.2798503},
doi = {10.1109/TCSII.2018.2798503},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/SakellariouP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsatsaragkosP18,
author = {Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {A Reconfigurable {LDPC} Decoder Optimized for 802.11n/ac Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {182--195},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2752086},
doi = {10.1109/TVLSI.2017.2752086},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsatsaragkosP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KouretasP18,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Hardware aspects of Long Short Term Memory},
booktitle = {25th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},
pages = {525--528},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICECS.2018.8617897},
doi = {10.1109/ICECS.2018.8617897},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/KouretasP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KavvousanosPK18,
author = {Emmanouil Kavvousanos and
Vassilis Paliouras and
Ioannis Kouretas},
title = {Simplified Deep-Learning-based decoders for linear block codes},
booktitle = {25th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},
pages = {769--772},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICECS.2018.8617843},
doi = {10.1109/ICECS.2018.8617843},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/KavvousanosPK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/AndriakopoulosP18,
author = {Christos Andriakopoulos and
Vassilis Paliouras},
title = {Data representation and hardware aspects in a fully-folded successive-cancellation
polar decoder},
booktitle = {7th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2018, Thessaloniki, Greece, May 7-9, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MOCAST.2018.8376633},
doi = {10.1109/MOCAST.2018.8376633},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/AndriakopoulosP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KalampoukasP18,
author = {Andreas Kalampoukas and
Vassilis Paliouras},
title = {A novel algorithm and hardware architecture for low-complexity soft
demappers},
booktitle = {7th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2018, Thessaloniki, Greece, May 7-9, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MOCAST.2018.8376571},
doi = {10.1109/MOCAST.2018.8376571},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/KalampoukasP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/KouretasP18,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Logarithmic number system for deep learning},
booktitle = {7th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2018, Thessaloniki, Greece, May 7-9, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MOCAST.2018.8376572},
doi = {10.1109/MOCAST.2018.8376572},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/KouretasP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/PaliourasKO18,
author = {Vassilis Paliouras and
Konstantina Karagianni and
Yann Oster},
title = {Low-cost soft-error compensation for transposed {FIR} digital filters},
booktitle = {7th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2018, Thessaloniki, Greece, May 7-9, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MOCAST.2018.8376574},
doi = {10.1109/MOCAST.2018.8376574},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/PaliourasKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PaliourasKO18,
author = {Vassilis Paliouras and
Konstantina Karagianni and
Yann Oster},
title = {Quantitative Evaluation of Certain {SET} Mitigation Techniques for
Multiply-Accumulate Circuits and State Machines},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {183--190},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464165},
doi = {10.1109/PATMOS.2018.8464165},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PaliourasKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/educon/AvourisSPK17,
author = {Nikolaos M. Avouris and
Kyriakos N. Sgarbas and
Vassilis Paliouras and
Michalis Koukias},
title = {Work in progress: An introduction to computing course using a Python-based
experiential approach},
booktitle = {2017 {IEEE} Global Engineering Education Conference, {EDUCON} 2017,
Athens, Greece, April 25-28, 2017},
pages = {1663--1666},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/EDUCON.2017.7943071},
doi = {10.1109/EDUCON.2017.7943071},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/educon/AvourisSPK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/Perris-SamiosP17,
author = {Georgios Perris{-}Samios and
Vassilis Paliouras},
title = {An approximate hardware check node for {\(\lambda\)}-min-based {LDPC}
decoders},
booktitle = {25th European Signal Processing Conference, {EUSIPCO} 2017, Kos, Greece,
August 28 - September 2, 2017},
pages = {1354--1357},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/EUSIPCO.2017.8081429},
doi = {10.23919/EUSIPCO.2017.8081429},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eusipco/Perris-SamiosP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TsiarasP17,
author = {Giorgos Tsiaras and
Vassilis Paliouras},
title = {Logarithmic number system addition-subtraction using fractional normalization},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050569},
doi = {10.1109/ISCAS.2017.8050569},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/TsiarasP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/ThanosP17,
author = {Alexios Thanos and
Vassilis Paliouras},
title = {Hardware trade-offs for massive {MIMO} uplink detection based on Newton
iteration method},
booktitle = {6th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2017, Thessaloniki, Greece, May 4-6, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MOCAST.2017.7937616},
doi = {10.1109/MOCAST.2017.7937616},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/ThanosP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/TsiarasP17,
author = {Giorgos Tsiaras and
Vassilis Paliouras},
title = {Multi-operand logarithmic addition/subtraction based on Fractional
Normalization},
booktitle = {6th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2017, Thessaloniki, Greece, May 4-6, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MOCAST.2017.7937686},
doi = {10.1109/MOCAST.2017.7937686},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/TsiarasP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/SakellariouP16,
author = {Panagiotis Sakellariou and
Vassilis Paliouras},
title = {Application-Specific Low-Power Multipliers},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {10},
pages = {2973--2985},
year = {2016},
url = {https://doi.org/10.1109/TC.2016.2516016},
doi = {10.1109/TC.2016.2516016},
timestamp = {Thu, 08 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/SakellariouP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Papachatzopoulos16,
author = {Kleanthis Papachatzopoulos and
Ioannis Kouretas and
Vassilis Paliouras},
title = {Dynamic delay variation behaviour of {RNS} multiply-add architectures},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {1978--1981},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7538963},
doi = {10.1109/ISCAS.2016.7538963},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Papachatzopoulos16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/TsatsaragkosP15,
author = {Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {Approximate Algorithms for Identifying Minima on Min-Sum {LDPC} Decoders
and Their Hardware Implementation},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {62-II},
number = {8},
pages = {766--770},
year = {2015},
url = {https://doi.org/10.1109/TCSII.2015.2433451},
doi = {10.1109/TCSII.2015.2433451},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/TsatsaragkosP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsp/MahdiP15,
author = {Ahmed Mahdi and
Vassilis Paliouras},
title = {On the Encoding Complexity of Quasi-Cyclic {LDPC} Codes},
journal = {{IEEE} Trans. Signal Process.},
volume = {63},
number = {22},
pages = {6096--6108},
year = {2015},
url = {https://doi.org/10.1109/TSP.2015.2463258},
doi = {10.1109/TSP.2015.2463258},
timestamp = {Tue, 10 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tsp/MahdiP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsp/MahdiP14,
author = {Ahmed Mahdi and
Vassilis Paliouras},
title = {A Low Complexity-High Throughput {QC-LDPC} Encoder},
journal = {{IEEE} Trans. Signal Process.},
volume = {62},
number = {10},
pages = {2696--2708},
year = {2014},
url = {https://doi.org/10.1109/TSP.2014.2314435},
doi = {10.1109/TSP.2014.2314435},
timestamp = {Tue, 10 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tsp/MahdiP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MermigkasP14,
author = {P. Mermigkas and
Vassilis Paliouras},
title = {Effective sum of squares implementation for {BPSK} soft-decision decoding},
booktitle = {21st {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},
pages = {822--825},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICECS.2014.7050112},
doi = {10.1109/ICECS.2014.7050112},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MermigkasP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/VasilopoulosP14,
author = {Christos Vasilopoulos and
Vassilis Paliouras},
title = {A technique for the identification of trapping sets in {LDPC} codes},
booktitle = {21st {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},
pages = {838--841},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICECS.2014.7050116},
doi = {10.1109/ICECS.2014.7050116},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/VasilopoulosP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KouretasBP13,
author = {Ioannis Kouretas and
Charalambos Basetas and
Vassilis Paliouras},
title = {Low-Power Logarithmic Number System Addition/Subtraction and Their
Impact on Digital Filters},
journal = {{IEEE} Trans. Computers},
volume = {62},
number = {11},
pages = {2196--2209},
year = {2013},
url = {https://doi.org/10.1109/TC.2012.111},
doi = {10.1109/TC.2012.111},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/KouretasBP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KouretasP13,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Delay-variation-tolerant {FIR} filter architectures based on the Residue
Number System},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {2223--2226},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572318},
doi = {10.1109/ISCAS.2013.6572318},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KouretasP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/KanistrasP13,
author = {Nikos Kanistras and
Vassilis Paliouras},
title = {A semi-analytical bivariate Gaussian model of the approximation error
impact on the Min-Sum {LDPC} decoding algorithm},
booktitle = {{IEEE} Workshop on Signal Processing Systems, SiPS 2013, Taipei City,
Taiwan, October 16-18, 2013},
pages = {89--94},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SiPS.2013.6674486},
doi = {10.1109/SIPS.2013.6674486},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/sips/KanistrasP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MahdiSKTP12,
author = {Ahmed Mahdi and
Panagiotis Sakellariou and
Nikos Kanistras and
Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {Hardware design and verification techniques for Giga-bit Forward-Error
Correction systems on FPGAs},
booktitle = {19th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},
pages = {89--92},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICECS.2012.6463792},
doi = {10.1109/ICECS.2012.6463792},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MahdiSKTP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SakellariouP12,
author = {Panagiotis Sakellariou and
Vassilis Paliouras},
title = {Low-power two's-complement multiplication based on selective activation},
booktitle = {19th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},
pages = {452--455},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICECS.2012.6463653},
doi = {10.1109/ICECS.2012.6463653},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SakellariouP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KouretasP12,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Residue arithmetic for designing multiply-add units in the presence
of non-gaussian variation},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {1231--1234},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271458},
doi = {10.1109/ISCAS.2012.6271458},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KouretasP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SakellariouP12,
author = {Panagiotis Sakellariou and
Vassilis Paliouras},
editor = {Jos{\'{e}} L. Ayala and
Delong Shang and
Alex Yakovlev},
title = {Low-Power Delay Sensors on FPGAs},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 22nd International Workshop, {PATMOS} 2012, Newcastle
upon Tyne, UK, September 4-6, 2012, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7606},
pages = {194--204},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-36157-9\_20},
doi = {10.1007/978-3-642-36157-9\_20},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SakellariouP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/SakellariouTKMP12,
author = {Panagiotis Sakellariou and
Ioannis Tsatsaragkos and
Nikos Kanistras and
Ahmed Mahdi and
Vassilis Paliouras},
title = {An FPGA-based prototyping method for verification, characterization
and optimization of {LDPC} error correction systems},
booktitle = {2012 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} XII, Samos, Greece, July 16-19,
2012},
pages = {286--293},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SAMOS.2012.6404188},
doi = {10.1109/SAMOS.2012.6404188},
timestamp = {Thu, 04 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/samos/SakellariouTKMP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/MahdiP12,
author = {Ahmed Mahdi and
Vassilis Paliouras},
title = {Simplified Multi-Level Quasi-Cyclic {LDPC} Codes for Low-Complexity
Encoders},
booktitle = {2012 {IEEE} Workshop on Signal Processing Systems, Quebec City, QC,
Canada, October 17-19, 2012},
pages = {1--6},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SiPS.2012.21},
doi = {10.1109/SIPS.2012.21},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/sips/MahdiP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/SpourlisTKP12,
author = {G. Spourlis and
Ioannis Tsatsaragkos and
Nikos Kanistras and
Vassilis Paliouras},
title = {Error Floor Compensation for {LDPC} Codes Using Concatenated Schemes},
booktitle = {2012 {IEEE} Workshop on Signal Processing Systems, Quebec City, QC,
Canada, October 17-19, 2012},
pages = {155--160},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SiPS.2012.38},
doi = {10.1109/SIPS.2012.38},
timestamp = {Thu, 04 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sips/SpourlisTKP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/KanistrasTP12,
author = {Nikos Kanistras and
Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {Propagation of {LLR} Saturation and Quantization Error in {LDPC} Min-Sum
Iterative Decoding},
booktitle = {2012 {IEEE} Workshop on Signal Processing Systems, Quebec City, QC,
Canada, October 17-19, 2012},
pages = {276--281},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/SiPS.2012.22},
doi = {10.1109/SIPS.2012.22},
timestamp = {Thu, 04 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sips/KanistrasTP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KanistrasP11,
author = {Nikos Kanistras and
Vassilis Paliouras},
title = {Impact of Approximation Error on the Decisions of {LDPC} Decoding},
journal = {J. Signal Process. Syst.},
volume = {64},
number = {1},
pages = {41--59},
year = {2011},
url = {https://doi.org/10.1007/s11265-010-0485-6},
doi = {10.1007/S11265-010-0485-6},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/KanistrasP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/ArnoldCPK10,
author = {Mark G. Arnold and
John R. Cowles and
Vassilis Paliouras and
Ioannis Kouretas},
editor = {Elisardo Antelo and
David Hough and
Paolo Ienne},
title = {Towards a Quaternion Complex Logarithmic Number System},
booktitle = {20th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2011, T{\"{u}}bingen,
Germany, 25-27 July 2011},
pages = {33--42},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ARITH.2011.14},
doi = {10.1109/ARITH.2011.14},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/ArnoldCPK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/ArnoldKP11,
author = {Mark G. Arnold and
Ioannis Kouretas and
Vassilis Paliouras},
editor = {Joseph R. Cavallaro and
Milos D. Ercegovac and
Frank Hannig and
Paolo Ienne and
Earl E. Swartzlander Jr. and
Alexandre F. Tenca},
title = {A Residue Logarithmic Number System {ALU} using interpolation and
cotransformation},
booktitle = {22nd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2011, Santa Monica, CA, USA,
Sept. 11-14, 2011},
pages = {255--258},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ASAP.2011.6043281},
doi = {10.1109/ASAP.2011.6043281},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/ArnoldKP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/ParaskevakosP11,
author = {Ioannis Paraskevakos and
Vassilis Paliouras},
title = {A flexible high-throughput hardware architecture for a gaussian noise
generator},
booktitle = {Proceedings of the {IEEE} International Conference on Acoustics, Speech,
and Signal Processing, {ICASSP} 2011, May 22-27, 2011, Prague Congress
Center, Prague, Czech Republic},
pages = {1673--1676},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICASSP.2011.5946821},
doi = {10.1109/ICASSP.2011.5946821},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icassp/ParaskevakosP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/TsatsaragkosKP11,
author = {Ioannis Tsatsaragkos and
Nikos Kanistras and
Vassilis Paliouras},
title = {A syndrome-based {LDPC} decoder with very low error floor},
booktitle = {17th International Conference on Digital Signal Processing, {DSP}
2011, Corfu, Greece, July 6-8, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICDSP.2011.6004950},
doi = {10.1109/ICDSP.2011.6004950},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icdsp/TsatsaragkosKP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/TsatsaragkosKP11a,
author = {Ioannis Tsatsaragkos and
Nikos Kanistras and
Vassilis Paliouras},
title = {Multiple {LDPC} decoder of very low bit-error rate},
booktitle = {17th International Conference on Digital Signal Processing, {DSP}
2011, Corfu, Greece, July 6-8, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICDSP.2011.6004951},
doi = {10.1109/ICDSP.2011.6004951},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icdsp/TsatsaragkosKP11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/TheodorakisP11,
author = {E. Theodorakis and
Vassilis Paliouras},
title = {On the impact of encoding on the complexity of residue arithmetic
circuits},
booktitle = {18th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2011, Beirut, Lebanon, December 11-14, 2011},
pages = {149--152},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICECS.2011.6122236},
doi = {10.1109/ICECS.2011.6122236},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/TheodorakisP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MakriTEPDBKPKBKSKSXKKVRAR11,
author = {Rodoula Makri and
Petros Tsenes and
Dimitrios Economou and
Yannis Papananos and
Dimitrios Dervenis and
Michael K. Birbas and
John C. Kikidis and
Vassilis Paliouras and
Grigorios Kalivas and
Alexios N. Birbas and
Panos Karaivazoglou and
Yorgos Stratakos and
John Korinthios and
Stelios Siskos and
Alkis A. Hatzopoulos and
John Komninos and
Serafeim Katsikas and
Konstantinos N. Voudouris and
Andreas Rigas and
George Agapiou and
Polivios Raxis},
title = {Next generation millimeter wave backhaul radio: Overall system design
for GbE 60GHz PtP wireless radio of high {CMOS} integration},
booktitle = {18th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2011, Beirut, Lebanon, December 11-14, 2011},
pages = {338--341},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICECS.2011.6122282},
doi = {10.1109/ICECS.2011.6122282},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MakriTEPDBKPKBKSKSXKKVRAR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KanistrasTMKPGLABKKP11,
author = {Nikos Kanistras and
Ioannis Tsatsaragkos and
Ahmed Mahdi and
Konstantina Karagianni and
Vassilis Paliouras and
Fotios Gioulekas and
E. Lalos and
Kostas Adaos and
Michael K. Birbas and
Panos Karaivazoglou and
M. V. Koziotis and
M. Perakis},
title = {Digital baseband challenges for a 60GHz gigabit link},
booktitle = {18th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2011, Beirut, Lebanon, December 11-14, 2011},
pages = {346--349},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICECS.2011.6122284},
doi = {10.1109/ICECS.2011.6122284},
timestamp = {Thu, 04 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/KanistrasTMKPGLABKKP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswcs/TsatsaragkosP11,
author = {Ioannis Tsatsaragkos and
Vassilis Paliouras},
title = {A flexible layered {LDPC} decoder},
booktitle = {8th International Symposium on Wireless Communication Systems, {ISWCS}
2011, Aachen, Germany, November 6-9, 2011},
pages = {36--40},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISWCS.2011.6125305},
doi = {10.1109/ISWCS.2011.6125305},
timestamp = {Thu, 04 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iswcs/TsatsaragkosP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/BrokalakisP11,
author = {Andreas Brokalakis and
Vassilis Paliouras},
title = {Using the arithmetic representation properties of data to reduce the
area and power consumption of {FFT} circuits for wireless {OFDM} systems},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2011, October 4-7, 2011, Beirut, Lebanon},
pages = {7--12},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/SiPS.2011.6088941},
doi = {10.1109/SIPS.2011.6088941},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/sips/BrokalakisP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/MahdiKP11,
author = {Ahmed Mahdi and
Nikos Kanistras and
Vassilis Paliouras},
title = {An encoding scheme and encoder architecture for rate-compatible {QC-LDPC}
codes},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2011, October 4-7, 2011, Beirut, Lebanon},
pages = {328--333},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/SiPS.2011.6088997},
doi = {10.1109/SIPS.2011.6088997},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/MahdiKP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KouretasP10,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {{RNS} multi-voltage low-power multiply-add unit},
booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
pages = {9--12},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICECS.2010.5724441},
doi = {10.1109/ICECS.2010.5724441},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/KouretasP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SpanosP10,
author = {Angelos Spanos and
Vassilis Paliouras},
title = {{VLSI} implementation and performance of turbo decoding stopping criteria},
booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
pages = {470--474},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICECS.2010.5724551},
doi = {10.1109/ICECS.2010.5724551},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SpanosP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KouretasP10,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {Residue arithmetic bases for reducing delay variation},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {3885--3888},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537692},
doi = {10.1109/ISCAS.2010.5537692},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KouretasP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KouretasP10,
author = {Ioannis Kouretas and
Vassilis Paliouras},
editor = {Ren{\'{e}} van Leuken and
Gilles Sicard},
title = {Residue Arithmetic for Designing Low-Power Multiply-Add Units},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization,
and Simulation - 20th International Workshop, {PATMOS} 2010, Grenoble,
France, September 7-10, 2010, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {6448},
pages = {31--40},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-17752-1\_4},
doi = {10.1007/978-3-642-17752-1\_4},
timestamp = {Tue, 13 Sep 2022 21:45:42 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KouretasP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KouretasP09,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {A Low-Complexity High-Radix {RNS} Multiplier},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {11},
pages = {2449--2462},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2009.2015548},
doi = {10.1109/TCSI.2009.2015548},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/KouretasP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/GiannopoulosP09,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
title = {A Low-Complexity PTS-based {PAPR} Reduction Technique for {OFDM} Signals
without Transmission of Side Information},
journal = {J. Signal Process. Syst.},
volume = {56},
number = {2-3},
pages = {141--153},
year = {2009},
url = {https://doi.org/10.1007/s11265-008-0238-y},
doi = {10.1007/S11265-008-0238-Y},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/GiannopoulosP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/KouretasP09,
author = {Ioannis Kouretas and
Vassilis Paliouras},
editor = {Antonio N{\'{u}}{\~{n}}ez and
Pedro P. Carballo},
title = {Variation-tolerant Design Using Residue Number System},
booktitle = {12th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2009, 27-29 August 2009, Patras, Greece},
pages = {157--163},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DSD.2009.160},
doi = {10.1109/DSD.2009.160},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/KouretasP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/KouretasP09,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {High-radix residue arithmetic bases for low-power {DSP} systems},
booktitle = {16th International Conference on Digital Signal Processing, {DSP}
2009, Santorini, Greece, July 5-7, 2009},
pages = {1--6},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ICDSP.2009.5201235},
doi = {10.1109/ICDSP.2009.5201235},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icdsp/KouretasP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KouretasP09,
author = {Ioannis Kouretas and
Vassilis Paliouras},
editor = {Jos{\'{e}} Monteiro and
Rene van Leuken},
title = {Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 19th International Workshop, {PATMOS} 2009, Delft,
The Netherlands, September 9-11, 2009, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5953},
pages = {26--35},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-11802-9\_7},
doi = {10.1007/978-3-642-11802-9\_7},
timestamp = {Tue, 13 Sep 2022 21:45:42 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KouretasP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KouretasBP08,
author = {Ioannis Kouretas and
Charalambos Basetas and
Vassilis Paliouras},
title = {Low-power logarithmic number system addition/subtraction and their
impact on digital filters},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {692--695},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4541512},
doi = {10.1109/ISCAS.2008.4541512},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KouretasBP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswpc/FotopoulouPS08,
author = {Eleni Fotopoulou and
Vassilis Paliouras and
Thanos Stouraitis},
title = {A frequency-domain interpolation implementation for {OFDM} transmitters},
booktitle = {Third International Symposium on Wireless Pervasive Computing, {ISWPC}
2008, May 7-9, 2008, Santorini, Greece, Proceedings},
pages = {628--632},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISWPC.2008.4556285},
doi = {10.1109/ISWPC.2008.4556285},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iswpc/FotopoulouPS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswpc/GiannopoulosP08,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
title = {Relationship among BER, power consumption and {PAPR}},
booktitle = {Third International Symposium on Wireless Pervasive Computing, {ISWPC}
2008, May 7-9, 2008, Santorini, Greece, Proceedings},
pages = {633--637},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISWPC.2008.4556286},
doi = {10.1109/ISWPC.2008.4556286},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iswpc/GiannopoulosP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswpc/KaraivazoglouKP08,
author = {Panos Karaivazoglou and
Konstantina Karagianni and
Vassilis Paliouras and
Kostas Berberidis},
title = {Roundoff error effects on a Quasi-Newton frequency domain channel
equalizer},
booktitle = {Third International Symposium on Wireless Pervasive Computing, {ISWPC}
2008, May 7-9, 2008, Santorini, Greece, Proceedings},
pages = {638--641},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISWPC.2008.4556287},
doi = {10.1109/ISWPC.2008.4556287},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iswpc/KaraivazoglouKP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswpc/AggourasP08,
author = {G. Aggouras and
Vassilis Paliouras},
title = {On the implementation of bus-based architectures for {LDPC} decoding},
booktitle = {Third International Symposium on Wireless Pervasive Computing, {ISWPC}
2008, May 7-9, 2008, Santorini, Greece, Proceedings},
pages = {642--645},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISWPC.2008.4556288},
doi = {10.1109/ISWPC.2008.4556288},
timestamp = {Mon, 04 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iswpc/AggourasP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswpc/KanistrasP08,
author = {Nikos Kanistras and
Vassilis Paliouras},
title = {Impact of roundoff errors in {LDPC} decoding},
booktitle = {Third International Symposium on Wireless Pervasive Computing, {ISWPC}
2008, May 7-9, 2008, Santorini, Greece, Proceedings},
pages = {646--650},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISWPC.2008.4556289},
doi = {10.1109/ISWPC.2008.4556289},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iswpc/KanistrasP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iswpc/PettasP08,
author = {D. Pettas and
Vassilis Paliouras},
title = {Packet detector for multiband {UWB}},
booktitle = {Third International Symposium on Wireless Pervasive Computing, {ISWPC}
2008, May 7-9, 2008, Santorini, Greece, Proceedings},
pages = {781--784},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISWPC.2008.4556317},
doi = {10.1109/ISWPC.2008.4556317},
timestamp = {Mon, 04 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iswpc/PettasP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KouretasP08,
author = {Ioannis Kouretas and
Vassilis Paliouras},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Mixed Radix-2 and High-Radix {RNS} Bases for Low-Power Multiplication},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {93--102},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_10},
doi = {10.1007/978-3-540-95948-9\_10},
timestamp = {Wed, 23 Feb 2022 16:05:31 +0100},
biburl = {https://dblp.org/rec/conf/patmos/KouretasP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/KanistrasP08,
author = {Nikos Kanistras and
Vassilis Paliouras},
title = {Impact of roundoff error on the decisions of the Log Sum-Product algorithm
for {LDPC} decoding},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2008, October 8-10, 2008, Washington, {D.C.} Metro Area, {USA}},
pages = {100--105},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/SIPS.2008.4671745},
doi = {10.1109/SIPS.2008.4671745},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/KanistrasP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BasetasKP07,
author = {Charalambos Basetas and
Ioannis Kouretas and
Vassilis Paliouras},
editor = {Nadine Az{\'{e}}mard and
Lars J. Svensson},
title = {Low-Power Digital Filtering Based on the Logarithmic Number System},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 17th International Workshop, {PATMOS} 2007, Gothenburg,
Sweden, September 3-5, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4644},
pages = {546--555},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-74442-9\_53},
doi = {10.1007/978-3-540-74442-9\_53},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BasetasKP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/GkrimpasP07,
author = {Dimitris Gkrimpas and
Vassilis Paliouras},
title = {On The Complexity of Joint Demodulation and Convolutional Decoding},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China},
pages = {669--674},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/SIPS.2007.4387629},
doi = {10.1109/SIPS.2007.4387629},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/GkrimpasP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/VounckxP06,
author = {Johan Vounckx and
Vassilis Paliouras},
title = {Editorial},
journal = {J. Low Power Electron.},
volume = {2},
number = {1},
year = {2006},
url = {https://doi.org/10.1166/jolpe.2006.015},
doi = {10.1166/JOLPE.2006.015},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/VounckxP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/GiannopoulosP06,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
title = {Novel efficient weighting factors for PTS-based {PAPR} reduction in
low-power {OFDM} transmitters},
booktitle = {14th European Signal Processing Conference, {EUSIPCO} 2006, Florence,
Italy, September 4-8, 2006},
pages = {1--5},
publisher = {{IEEE}},
year = {2006},
url = {https://ieeexplore.ieee.org/document/7071616/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eusipco/GiannopoulosP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GiannopoulosP06,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
title = {A novel technique for low-power {D/A} conversion based on {PAPR} reduction},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693754},
doi = {10.1109/ISCAS.2006.1693754},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GiannopoulosP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GiannopoulosP06,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
editor = {Johan Vounckx and
Nadine Az{\'{e}}mard and
Philippe Maurine},
title = {Low-Power Maximum Magnitude Computation for {PAPR} Reduction in {OFDM}
Transmitters},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 16th International Workshop, {PATMOS} 2006, Montpellier,
France, September 13-15, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4148},
pages = {203--213},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11847083\_20},
doi = {10.1007/11847083\_20},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GiannopoulosP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/KaragianniPG06,
author = {Konstantina Karagianni and
Vassilis Paliouras and
Theodoros Giannopoulos},
title = {Low-Power Saturated Arithmetic and its Application in {VLSI} Architectures
for {OFDM} Modems},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
pages = {200--204},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SIPS.2006.352581},
doi = {10.1109/SIPS.2006.352581},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/KaragianniPG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/GidarosP06,
author = {Spyros Gidaros and
Vassilis Paliouras},
title = {Simplified Criteria for Early Iterative Decoding Termination},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
pages = {209--214},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SIPS.2006.352583},
doi = {10.1109/SIPS.2006.352583},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/GidarosP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/GiannopoulosP06,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
title = {A Low-Complexity PTS-based {PAPR} Reduction Technique for {OFDM} Signals
without Transmission of Side Information},
booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
pages = {434--439},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SIPS.2006.352622},
doi = {10.1109/SIPS.2006.352622},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sips/GiannopoulosP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VouzisAP05,
author = {Panagiotis D. Vouzis and
Mark G. Arnold and
Vassilis Paliouras},
title = {Using {CLNS} for FFTs in {OFDM} demodulation of {UWB} receivers},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {3954--3957},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465496},
doi = {10.1109/ISCAS.2005.1465496},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VouzisAP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GiannopoulosP05,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {Low-Power {VLSI} Architectures for {OFDM} Transmitters Based on {PAPR}
Reduction},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven,
Belgium, September 21-23, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3728},
pages = {177--186},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11556930\_19},
doi = {10.1007/11556930\_19},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GiannopoulosP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KaragianniP05,
author = {Konstantina Karagianni and
Vassilis Paliouras},
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {Low-Power Aspects of Nonlinear Signal Processing},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven,
Belgium, September 21-23, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3728},
pages = {518--527},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11556930\_53},
doi = {10.1007/11556930\_53},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KaragianniP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/patmos/2005,
editor = {Vassilis Paliouras and
Johan Vounckx and
Diederik Verkest},
title = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation, 15th International Workshop, {PATMOS} 2005, Leuven,
Belgium, September 21-23, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3728},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11556930},
doi = {10.1007/11556930},
isbn = {3-540-29013-3},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/Dimitrakopoulos04,
author = {Giorgos Dimitrakopoulos and
Vassilis Paliouras},
title = {A novel architecture and a systematic graph-based optimization methodology
for modulo multiplication},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {51-I},
number = {2},
pages = {354--370},
year = {2004},
url = {https://doi.org/10.1109/TCSI.2003.820243},
doi = {10.1109/TCSI.2003.820243},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/Dimitrakopoulos04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/globecom/FotopoulouP04,
author = {Eleni Fotopoulou and
Vassilis Paliouras},
title = {An efficient computational method and a {VLSI} architecture for digital
filtering of {CP-OFDM} signals},
booktitle = {Proceedings of the Global Telecommunications Conference, 2004. {GLOBECOM}
'04, Dallas, Texas, USA, 29 November - 3 December 2004},
pages = {2393--2397},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/GLOCOM.2004.1378436},
doi = {10.1109/GLOCOM.2004.1378436},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/globecom/FotopoulouP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GiannopoulosP04,
author = {Theodoros Giannopoulos and
Vassilis Paliouras},
title = {An efficient architecture for peak-to-average power ratio reduction
in {OFDM} systems in the presence of pulse-shaping filtering},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {85--88},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ISCAS.2004.1328946},
doi = {10.1109/ISCAS.2004.1328946},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GiannopoulosP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KrommydasP04,
author = {Stamatis Krommydas and
Vassilis Paliouras},
title = {An efficient memory compression scheme for 8 k {FFT} in a {DVB-T}
receiver and the corresponding error model},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {89--92},
publisher = {{IEEE}},
year = {2004},
timestamp = {Fri, 20 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KrommydasP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/VouzisP04,
author = {Panagiotis D. Vouzis and
Vassilis Paliouras},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Optimal Logarithmic Representation in Terms of {SNR} Behavior},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {760--769},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_78},
doi = {10.1007/978-3-540-30205-6\_78},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/VouzisP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/patmos/2004,
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/b100662},
doi = {10.1007/B100662},
isbn = {3-540-23095-5},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/2004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FotopoulouPS03,
author = {Eleni Fotopoulou and
Vassilis Paliouras and
Thanos Stouraitis},
title = {A computational technique and a {VLSI} architecture for digital pulse
shaping in {OFDM} modems},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {125--128},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1205909},
doi = {10.1109/ISCAS.2003.1205909},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/FotopoulouPS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KouretasP03,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {High-radix redundant circuits for {RNS} modulo r\({}^{\mbox{n}}\)-1,
r\({}^{\mbox{n}}\), or r\({}^{\mbox{n}}\)+1},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {229--232},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206238},
doi = {10.1109/ISCAS.2003.1206238},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KouretasP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PaliourasSS02,
author = {Vassilis Paliouras and
Alexander Skavantzos and
Thanos Stouraitis},
editor = {Kanad Ghose and
Patrick H. Madden and
Vivek De and
Peter M. Kogge},
title = {Multi-voltage low power convolvers using the polynomial residue number
system},
booktitle = {Proceedings of the 12th {ACM} Great Lakes Symposium on {VLSI} 2002,
New York, NY, USA, April 18-19, 2002},
pages = {7--11},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505306.505309},
doi = {10.1145/505306.505309},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/PaliourasSS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/KouretasP02,
author = {Ioannis Kouretas and
Vassilis Paliouras},
title = {High-radix modulo r\({}^{\mbox{n}}\) - 1 multipliers and adders},
booktitle = {Proceedings of the 2002 9th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2002, Dubrovnik, Croatia, September
15-18, 2002},
pages = {561--564},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ICECS.2002.1046227},
doi = {10.1109/ICECS.2002.1046227},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/KouretasP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KaragianniPDS01,
author = {Konstantina Karagianni and
Vassilis Paliouras and
George Diamantakos and
Thanos Stouraitis},
title = {Operation-Saving {VLSI} Architectures for 3D Geometrical Transformations},
journal = {{IEEE} Trans. Computers},
volume = {50},
number = {6},
pages = {609--622},
year = {2001},
url = {https://doi.org/10.1109/12.931896},
doi = {10.1109/12.931896},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KaragianniPDS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/PaliourasS01,
author = {Vassilis Paliouras and
Thanos Stouraitis},
title = {Low-Power Properties of the Logarithmic Number System},
booktitle = {15th {IEEE} Symposium on Computer Arithmetic (Arith-15 2001), 11-17
June 2001, Vail, CO, {USA}},
pages = {229--236},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ARITH.2001.930124},
doi = {10.1109/ARITH.2001.930124},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/PaliourasS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PaliourasDTS01,
author = {Vassilis Paliouras and
J. Dagres and
Panagiotis Tsakalides and
Thanos Stouraitis},
title = {{VLSI} architectures for blind equalization based on fractional-order
statistics},
booktitle = {Proceedings of the 2001 8th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2001, Malta, September 2-5, 2001},
pages = {799--802},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ICECS.2001.957595},
doi = {10.1109/ICECS.2001.957595},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PaliourasDTS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PaliourasS01,
author = {Vassilis Paliouras and
Thanos Stouraitis},
title = {Signal activity and power consumption reduction using the logarithmic
number system},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {653--656},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.921155},
doi = {10.1109/ISCAS.2001.921155},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PaliourasS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PaliourasS00,
author = {Vassilis Paliouras and
Thanos Stouraitis},
title = {High-radix residue number system forward and inverse converters},
booktitle = {Proceedings of the 2000 7th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2000, Jounieh, Lebanon, December 17-20,
2000},
pages = {858--861},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ICECS.2000.913011},
doi = {10.1109/ICECS.2000.913011},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PaliourasS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PaliourasS00,
author = {Vassilis Paliouras and
Thanos Stouraitis},
editor = {Dimitrios Soudris and
Peter Pirsch and
Erich Barke},
title = {Logarithmic Number System for Low-Power Arithmetic},
booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization
and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen,
Germany, September 13-15, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1918},
pages = {285--294},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-45373-3\_30},
doi = {10.1007/3-540-45373-3\_30},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PaliourasS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PaliourasS99,
author = {Vassilis Paliouras and
Thanos Stouraitis},
title = {Novel high-radix residue number system multipliers and adders},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {451--454},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.777911},
doi = {10.1109/ISCAS.1999.777911},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PaliourasS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PaliourasKAS98,
author = {Vassilis Paliouras and
J. Karagiannis and
G. Aggouras and
Thanos Stouraitis},
title = {A very-long instruction word digital signal processor based on the
logarithmic number system},
booktitle = {5th {IEEE} International Conference on Electronics, Circuits and Systems,
{ICECS} 1998, Surfing the Waves of Science and Technology, Lisbon,
Portugal, September 7-10, 1998},
pages = {59--62},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ICECS.1998.813936},
doi = {10.1109/ICECS.1998.813936},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PaliourasKAS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PaliourasKS98,
author = {Vassilis Paliouras and
Konstantina Karagianni and
Thanos Stouraitis},
title = {A {VLSI} architecture for fast and accurate floating-point sine/cosine
evaluation},
booktitle = {5th {IEEE} International Conference on Electronics, Circuits and Systems,
{ICECS} 1998, Surfing the Waves of Science and Technology, Lisbon,
Portugal, September 7-10, 1998},
pages = {473--476},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ICECS.1998.813365},
doi = {10.1109/ICECS.1998.813365},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/PaliourasKS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/PaliourasS97,
author = {Vassilis Paliouras and
Thanos Stouraitis},
title = {Area-time performance of {VLSI} {FIR} filter architectures based on
residue arithmetic},
booktitle = {23rd {EUROMICRO} Conference '97, New Frontiers of Information Technology,
1-4 September 1997, Budapest, Hungary},
pages = {576--583},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EURMIC.1997.617376},
doi = {10.1109/EURMIC.1997.617376},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/PaliourasS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/KaragianniDPS97,
author = {Konstantina Karagianni and
George Diamantakos and
Vassilis Paliouras and
Thanos Stouraitis},
title = {An operation-saving {VLSI} geometry engine core},
booktitle = {1997 {IEEE} International Conference on Acoustics, Speech, and Signal
Processing, {ICASSP} '97, Munich, Germany, April 21-24, 1997},
pages = {607--610},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICASSP.1997.599841},
doi = {10.1109/ICASSP.1997.599841},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icassp/KaragianniDPS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/MalamasPS96,
author = {E. N. Malamas and
Vassilis Paliouras and
Thanos Stouraitis},
title = {Efficient algorithms and {VLSI} architectures for trigonometric functions
in the logarithmic number system based on the subtraction function},
booktitle = {Proceedings of Third International Conference on Electronics, Circuits,
and Systems, {ICECS} 1996, Rodos, Greece, October 13-16, 1996},
pages = {964--967},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/ICECS.1996.584546},
doi = {10.1109/ICECS.1996.584546},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/MalamasPS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/OrginosPS95,
author = {I. Orginos and
Vassilis Paliouras and
Thanos Stouraitis},
title = {A Novel Algorithm for Multi-Operand Logarithmic Number System Addition
and Subtraction Using Polynominal Approximation},
booktitle = {1995 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1995, Seattle, Washington, USA, April 30 - May 3, 1995},
pages = {1992--1995},
publisher = {{IEEE}},
year = {1995},
url = {https://doi.org/10.1109/ISCAS.1995.523812},
doi = {10.1109/ISCAS.1995.523812},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/OrginosPS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PaliourasS94,
author = {Vassilis Paliouras and
Thanos Stouraitis},
title = {Systematic Design of Multi-Modulus/Multi-Function Residue Number System
Processors},
booktitle = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1994, London, England, UK, May 30 - June 2, 1994},
pages = {79--82},
publisher = {{IEEE}},
year = {1994},
url = {https://doi.org/10.1109/ISCAS.1994.409201},
doi = {10.1109/ISCAS.1994.409201},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PaliourasS94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/SoudrisPSSG93,
author = {Dimitrios Soudris and
Vassilis Paliouras and
Thanos Stouraitis and
Alexander Skavantzos and
Constantinos E. Goutis},
title = {Systematic design of full adder-based architectures for convolution},
booktitle = {{IEEE} International Conference on Acoustics, Speech, and Signal Processing,
{ICASSP} '93, Minneapolis, Minnesota, USA, April 27-30, 1993},
pages = {389--392},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.ieeecomputersociety.org/10.1109/ICASSP.1993.319137},
doi = {10.1109/ICASSP.1993.319137},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icassp/SoudrisPSSG93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PaliourasSS93,
author = {Vassilis Paliouras and
Dimitrios Soudris and
Thanos Stouraitis},
title = {Methodology for the Design of Signed-digit {DSP} Processors},
booktitle = {1993 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1993, Chicago, Illinois, USA, May 3-6, 1993},
pages = {1833--1836},
publisher = {{IEEE}},
year = {1993},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PaliourasSS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/SoudrisPS92,
author = {Dimitrios Soudris and
Vassilis Paliouras and
Thanos Stouraitis},
title = {Systematic development of architectures for multidimensional {DSP}
using the residue number system},
booktitle = {1992 {IEEE} International Conference on Acoustics, Speech, and Signal
Processing, {ICASSP} '92, San Francisco, California, USA, March 23-26,
1992},
pages = {397--400},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ICASSP.1992.226192},
doi = {10.1109/ICASSP.1992.226192},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/icassp/SoudrisPS92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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