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ORCIDBibTeX records: Sai Phaneendra P.
@article{DBLP:journals/sncs/PhaneendraVS22,
author = {P. Sai Phaneendra and
Chetan Vudadha and
M. B. Srinivas},
title = {Optimization of Reversible Circuits Using Gate Pair Classification},
journal = {{SN} Comput. Sci.},
volume = {3},
number = {1},
pages = {40},
year = {2022},
url = {https://doi.org/10.1007/s42979-021-00900-5},
doi = {10.1007/S42979-021-00900-5},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sncs/PhaneendraVS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/VudadhaPS18,
author = {Chetan Vudadha and
Sai Phaneendra Parlapalli and
M. B. Srinivas},
title = {Energy efficient design of CNFET-based multi-digit ternary adders},
journal = {Microelectron. J.},
volume = {75},
pages = {75--86},
year = {2018},
url = {https://doi.org/10.1016/j.mejo.2018.02.004},
doi = {10.1016/J.MEJO.2018.02.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/VudadhaPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/ParlapalliVS17,
author = {Sai Phaneendra Parlapalli and
Chetan Vudadha and
M. B. Srinivas},
editor = {Iain Phillips and
Hafizur Rahaman},
title = {Optimizing the Reversible Circuits Using Complementary Control Line
Transformation},
booktitle = {Reversible Computation - 9th International Conference, {RC} 2017,
Kolkata, India, July 6-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10301},
pages = {111--126},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-59936-6\_9},
doi = {10.1007/978-3-319-59936-6\_9},
timestamp = {Tue, 22 Oct 2019 15:21:14 +0200},
biburl = {https://dblp.org/rec/conf/rc/ParlapalliVS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/ParlapalliVS17a,
author = {Sai Phaneendra Parlapalli and
Chetan Vudadha and
M. B. Srinivas},
editor = {Iain Phillips and
Hafizur Rahaman},
title = {An {ESOP} Based Cube Decomposition Technique for Reversible Circuits},
booktitle = {Reversible Computation - 9th International Conference, {RC} 2017,
Kolkata, India, July 6-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10301},
pages = {127--140},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-59936-6\_10},
doi = {10.1007/978-3-319-59936-6\_10},
timestamp = {Mon, 26 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/ParlapalliVS17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/VudadhaPS16,
author = {Chetan Vudadha and
P. Sai Phaneendra and
M. B. Srinivas},
title = {An Efficient Design Methodology for {CNFET} Based Ternary Logic Circuits},
booktitle = {{IEEE} International Symposium on Nanoelectronic and Information Systems,
iNIS 2016, Gwalior, India, December 19-21, 2016},
pages = {278--283},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/iNIS.2016.070},
doi = {10.1109/INIS.2016.070},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/VudadhaPS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/PalVPVM14,
author = {Subhankar Pal and
Chetan Vudadha and
P. Sai Phaneendra and
Sreehari Veeramachaneni and
Srinivas B. Mandalika},
title = {A New Design of an N-Bit Reversible Arithmetic Logic Unit},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal,
Mangalore, India, December 15-17, 2014},
pages = {224--225},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISED.2014.56},
doi = {10.1109/ISED.2014.56},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/PalVPVM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PVVS14,
author = {P. Sai Phaneendra and
Chetan Vudadha and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Optimized Design of Reversible Quantum Comparator},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {557--562},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.103},
doi = {10.1109/VLSID.2014.103},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PVVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/VudadhaPVS12,
author = {Chetan Vudadha and
Phaneendra P. Sai and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {{CNFET} based ternary magnitude comparator},
booktitle = {International Symposium on Communications and Information Technologies,
{ISCIT} 2012, Gold Coast, Australia, October 2-5, 2012},
pages = {942--946},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCIT.2012.6381040},
doi = {10.1109/ISCIT.2012.6381040},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscit/VudadhaPVS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VudadhaPVAMS12,
author = {Chetan Vudadha and
P. Sai Phaneendra and
Sreehari Veeramachaneni and
Syed Ershad Ahmed and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Design of Prefix-Based Optimal Reversible Comparator},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {201--206},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.49},
doi = {10.1109/ISVLSI.2012.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VudadhaPVAMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VudadhaPAVMS12,
author = {Chetan Vudadha and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple
Hybrid Adders},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {225--230},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.50},
doi = {10.1109/ISVLSI.2012.50},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VudadhaPAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VudadhaMNPAVMS12,
author = {Chetan Vudadha and
Goutham Makkena and
M. Venkata Swamy Nayudu and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
editor = {Vishwani D. Agrawal and
Srimat T. Chakradhar},
title = {Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive
Resolution Flash ADCs},
booktitle = {25th International Conference on {VLSI} Design, Hyderabad, India,
January 7-11, 2012},
pages = {280--285},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/VLSID.2012.84},
doi = {10.1109/VLSID.2012.84},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VudadhaMNPAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/VPAVMS11,
author = {Chetan Kumar V. and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Unified Architecture for {BCD} and Binary Adder/Subtractor},
booktitle = {14th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2011, August 31 - September 2, 2011, Oulu,
Finland},
pages = {426--429},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DSD.2011.58},
doi = {10.1109/DSD.2011.58},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/PVAVMS11,
author = {P. Sai Phaneendra and
Chetan Vudadha and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {Increment/decrement/2's complement/priority encoder circuit for varying
operand lengths},
booktitle = {11th International Symposium on Communications and Information Technologies,
{ISCIT} 2011, Hangzhou, China, October 12-14, 2011},
pages = {472--477},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCIT.2011.6092152},
doi = {10.1109/ISCIT.2011.6092152},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscit/PVAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/VPAVMS11,
author = {Chetan Kumar V. and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with
Improved Decision Block},
booktitle = {International Symposium on Electronic System Design, {ISED} 2011,
Kochi, Kerala, India, December 19-21, 2011},
pages = {100--105},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISED.2011.52},
doi = {10.1109/ISED.2011.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VPAVMS11,
author = {Chetan Kumar V. and
Sai Phaneendra P. and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Prefix Based Reconfigurable Adder},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
July 2011, Chennai, India},
pages = {349--350},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISVLSI.2011.69},
doi = {10.1109/ISVLSI.2011.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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