BibTeX records: Asit K. Mishra

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@article{DBLP:journals/corr/abs-2104-08378,
  author       = {Asit K. Mishra and
                  Jorge Albericio Latorre and
                  Jeff Pool and
                  Darko Stosic and
                  Dusan Stosic and
                  Ganesh Venkatesh and
                  Chong Yu and
                  Paulius Micikevicius},
  title        = {Accelerating Sparse Deep Neural Networks},
  journal      = {CoRR},
  volume       = {abs/2104.08378},
  year         = {2021},
  url          = {https://arxiv.org/abs/2104.08378},
  eprinttype    = {arXiv},
  eprint       = {2104.08378},
  timestamp    = {Mon, 26 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2104-08378.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2109-07710,
  author       = {Anup Sarma and
                  Sonali Singh and
                  Huaipan Jiang and
                  Ashutosh Pattnaik and
                  Asit K. Mishra and
                  Vijaykrishnan Narayanan and
                  Mahmut T. Kandemir and
                  Chita R. Das},
  title        = {Exploiting Activation based Gradient Output Sparsity to Accelerate
                  Backpropagation in CNNs},
  journal      = {CoRR},
  volume       = {abs/2109.07710},
  year         = {2021},
  url          = {https://arxiv.org/abs/2109.07710},
  eprinttype    = {arXiv},
  eprint       = {2109.07710},
  timestamp    = {Wed, 22 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2109-07710.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/PattnaikTKJMKSD19,
  author       = {Ashutosh Pattnaik and
                  Xulong Tang and
                  Onur Kayiran and
                  Adwait Jog and
                  Asit K. Mishra and
                  Mahmut T. Kandemir and
                  Anand Sivasubramaniam and
                  Chita R. Das},
  editor       = {Srilatha Bobbie Manne and
                  Hillery C. Hunter and
                  Erik R. Altman},
  title        = {Opportunistic computing in {GPU} architectures},
  booktitle    = {Proceedings of the 46th International Symposium on Computer Architecture,
                  {ISCA} 2019, Phoenix, AZ, USA, June 22-26, 2019},
  pages        = {210--223},
  publisher    = {{ACM}},
  year         = {2019},
  url          = {https://doi.org/10.1145/3307650.3322212},
  doi          = {10.1145/3307650.3322212},
  timestamp    = {Fri, 09 Jul 2021 15:51:20 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/PattnaikTKJMKSD19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ColangeloNNMMN18,
  author       = {Philip Colangelo and
                  Nasibeh Nasiri and
                  Eriko Nurvitadhi and
                  Asit K. Mishra and
                  Martin Margala and
                  Kevin Nealis},
  title        = {Exploration of Low Numeric Precision Deep Learning Inference Using
                  Intel{\textregistered} FPGAs},
  booktitle    = {26th {IEEE} Annual International Symposium on Field-Programmable Custom
                  Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May
                  1, 2018},
  pages        = {73--80},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/FCCM.2018.00020},
  doi          = {10.1109/FCCM.2018.00020},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fccm/ColangeloNNMMN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MossSNRJSMMSL18,
  author       = {Duncan J. M. Moss and
                  Krishnan Srivatsan and
                  Eriko Nurvitadhi and
                  Piotr Ratuszniak and
                  Chris Johnson and
                  Jaewoong Sim and
                  Asit K. Mishra and
                  Debbie Marr and
                  Suchit Subhaschandra and
                  Philip Heng Wai Leong},
  editor       = {Jason Helge Anderson and
                  Kia Bazargan},
  title        = {A Customizable Matrix Multiplication Framework for the Intel HARPv2
                  Xeon+FPGA Platform: {A} Deep Learning Case Study},
  booktitle    = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
                  Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
  pages        = {107--116},
  publisher    = {{ACM}},
  year         = {2018},
  url          = {https://doi.org/10.1145/3174243.3174258},
  doi          = {10.1145/3174243.3174258},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/fpga/MossSNRJSMMSL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NurvitadhiCMMNC18,
  author       = {Eriko Nurvitadhi and
                  Jeffrey J. Cook and
                  Asit K. Mishra and
                  Debbie Marr and
                  Kevin Nealis and
                  Philip Colangelo and
                  Andrew C. Ling and
                  Davor Capalija and
                  Utku Aydonat and
                  Sergey Y. Shumarayev and
                  Aravind Dasu},
  editor       = {Jason Helge Anderson and
                  Kia Bazargan},
  title        = {In-Package Domain-Specific ASICs for Intel{\textregistered} Stratix{\textregistered}
                  10 FPGAs: {A} Case Study of Accelerating Deep Learning Using TensorTile
                  ASIC(Abstract Only)},
  booktitle    = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
                  Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
  pages        = {287},
  publisher    = {{ACM}},
  year         = {2018},
  url          = {https://doi.org/10.1145/3174243.3174966},
  doi          = {10.1145/3174243.3174966},
  timestamp    = {Sat, 28 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/NurvitadhiCMMNC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ColangeloNNMMN18,
  author       = {Philip Colangelo and
                  Nasibeh Nasiri and
                  Eriko Nurvitadhi and
                  Asit K. Mishra and
                  Martin Margala and
                  Kevin Nealis},
  editor       = {Jason Helge Anderson and
                  Kia Bazargan},
  title        = {Exploration of Low Numeric Precision Deep Learning Inference Using
                  Intel{\textregistered} FPGAs: (Abstract Only)},
  booktitle    = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
                  Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
  pages        = {294},
  publisher    = {{ACM}},
  year         = {2018},
  url          = {https://doi.org/10.1145/3174243.3174999},
  doi          = {10.1145/3174243.3174999},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/ColangeloNNMMN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/NurvitadhiCMMNC18,
  author       = {Eriko Nurvitadhi and
                  Jeffrey J. Cook and
                  Asit K. Mishra and
                  Debbie Marr and
                  Kevin Nealis and
                  Philip Colangelo and
                  Andrew C. Ling and
                  Davor Capalija and
                  Utku Aydonat and
                  Aravind Dasu and
                  Sergey Y. Shumarayev},
  title        = {In-Package Domain-Specific ASICs for Intel{\textregistered} Stratix{\textregistered}
                  10 FPGAs: {A} Case Study of Accelerating Deep Learning Using TensorTile
                  {ASIC}},
  booktitle    = {28th International Conference on Field Programmable Logic and Applications,
                  {FPL} 2018, Dublin, Ireland, August 27-31, 2018},
  pages        = {106--110},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/FPL.2018.00027},
  doi          = {10.1109/FPL.2018.00027},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpl/NurvitadhiCMMNC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iclr/MishraM18,
  author       = {Asit K. Mishra and
                  Debbie Marr},
  title        = {Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision
                  Network Accuracy},
  booktitle    = {6th International Conference on Learning Representations, {ICLR} 2018,
                  Vancouver, BC, Canada, April 30 - May 3, 2018, Conference Track Proceedings},
  publisher    = {OpenReview.net},
  year         = {2018},
  url          = {https://openreview.net/forum?id=B1ae1lZRb},
  timestamp    = {Thu, 25 Jul 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iclr/MishraM18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iclr/MishraNCM18,
  author       = {Asit K. Mishra and
                  Eriko Nurvitadhi and
                  Jeffrey J. Cook and
                  Debbie Marr},
  title        = {{WRPN:} Wide Reduced-Precision Networks},
  booktitle    = {6th International Conference on Learning Representations, {ICLR} 2018,
                  Vancouver, BC, Canada, April 30 - May 3, 2018, Conference Track Proceedings},
  publisher    = {OpenReview.net},
  year         = {2018},
  url          = {https://openreview.net/forum?id=B1ZvaaeAZ},
  timestamp    = {Thu, 25 Jul 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iclr/MishraNCM18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1803-00227,
  author       = {Asit K. Mishra and
                  Debbie Marr},
  title        = {{WRPN} {\&} Apprentice: Methods for Training and Inference using
                  Low-Precision Numerics},
  journal      = {CoRR},
  volume       = {abs/1803.00227},
  year         = {2018},
  url          = {http://arxiv.org/abs/1803.00227},
  eprinttype    = {arXiv},
  eprint       = {1803.00227},
  timestamp    = {Wed, 03 Apr 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1803-00227.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1806-11547,
  author       = {Philip Colangelo and
                  Nasibeh Nasiri and
                  Asit K. Mishra and
                  Eriko Nurvitadhi and
                  Martin Margala and
                  Kevin Nealis},
  title        = {Exploration of Low Numeric Precision Deep Learning Inference Using
                  Intel FPGAs},
  journal      = {CoRR},
  volume       = {abs/1806.11547},
  year         = {2018},
  url          = {http://arxiv.org/abs/1806.11547},
  eprinttype    = {arXiv},
  eprint       = {1806.11547},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1806-11547.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MishraNVPM17,
  author       = {Asit K. Mishra and
                  Eriko Nurvitadhi and
                  Ganesh Venkatesh and
                  Jonathan Pearce and
                  Debbie Marr},
  title        = {Fine-grained accelerators for sparse machine learning workloads},
  booktitle    = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2017, Chiba, Japan, January 16-19, 2017},
  pages        = {635--640},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASPDAC.2017.7858395},
  doi          = {10.1109/ASPDAC.2017.7858395},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/MishraNVPM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/MossNSMMSL17,
  author       = {Duncan J. M. Moss and
                  Eriko Nurvitadhi and
                  Jaewoong Sim and
                  Asit K. Mishra and
                  Debbie Marr and
                  Suchit Subhaschandra and
                  Philip Heng Wai Leong},
  editor       = {Marco D. Santambrogio and
                  Diana G{\"{o}}hringer and
                  Dirk Stroobandt and
                  Nele Mentens and
                  Jari Nurmi},
  title        = {High performance binary neural networks on the Xeon+FPGA{\texttrademark}
                  platform},
  booktitle    = {27th International Conference on Field Programmable Logic and Applications,
                  {FPL} 2017, Ghent, Belgium, September 4-8, 2017},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.23919/FPL.2017.8056823},
  doi          = {10.23919/FPL.2017.8056823},
  timestamp    = {Tue, 29 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpl/MossNSMMSL17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/MishraCNM17,
  author       = {Asit K. Mishra and
                  Jeffrey J. Cook and
                  Eriko Nurvitadhi and
                  Debbie Marr},
  title        = {{WRPN:} Training and Inference using Wide Reduced-Precision Networks},
  journal      = {CoRR},
  volume       = {abs/1704.03079},
  year         = {2017},
  url          = {http://arxiv.org/abs/1704.03079},
  eprinttype    = {arXiv},
  eprint       = {1704.03079},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/MishraCNM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1709-01134,
  author       = {Asit K. Mishra and
                  Eriko Nurvitadhi and
                  Jeffrey J. Cook and
                  Debbie Marr},
  title        = {{WRPN:} Wide Reduced-Precision Networks},
  journal      = {CoRR},
  volume       = {abs/1709.01134},
  year         = {2017},
  url          = {http://arxiv.org/abs/1709.01134},
  eprinttype    = {arXiv},
  eprint       = {1709.01134},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1709-01134.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1710-07706,
  author       = {Supriya Kapur and
                  Asit K. Mishra and
                  Debbie Marr},
  title        = {Low Precision RNNs: Quantizing RNNs Without Losing Accuracy},
  journal      = {CoRR},
  volume       = {abs/1710.07706},
  year         = {2017},
  url          = {http://arxiv.org/abs/1710.07706},
  eprinttype    = {arXiv},
  eprint       = {1710.07706},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1710-07706.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1711-05852,
  author       = {Asit K. Mishra and
                  Debbie Marr},
  title        = {Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision
                  Network Accuracy},
  journal      = {CoRR},
  volume       = {abs/1711.05852},
  year         = {2017},
  url          = {http://arxiv.org/abs/1711.05852},
  eprinttype    = {arXiv},
  eprint       = {1711.05852},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-1711-05852.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/PattnaikTJKMKMD16,
  author       = {Ashutosh Pattnaik and
                  Xulong Tang and
                  Adwait Jog and
                  Onur Kayiran and
                  Asit K. Mishra and
                  Mahmut T. Kandemir and
                  Onur Mutlu and
                  Chita R. Das},
  editor       = {Ayal Zaks and
                  Bilha Mendelson and
                  Lawrence Rauchwerger and
                  Wen{-}mei W. Hwu},
  title        = {Scheduling Techniques for {GPU} Architectures with Processing-In-Memory
                  Capabilities},
  booktitle    = {Proceedings of the 2016 International Conference on Parallel Architectures
                  and Compilation, {PACT} 2016, Haifa, Israel, September 11-15, 2016},
  pages        = {31--44},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2967938.2967940},
  doi          = {10.1145/2967938.2967940},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/IEEEpact/PattnaikTJKMKMD16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/NurvitadhiMWVM16,
  author       = {Eriko Nurvitadhi and
                  Asit K. Mishra and
                  Yu Wang and
                  Ganesh Venkatesh and
                  Debbie Marr},
  editor       = {Luca Fanucci and
                  J{\"{u}}rgen Teich},
  title        = {Hardware accelerator for analytics of sparse data},
  booktitle    = {2016 Design, Automation {\&} Test in Europe Conference {\&}
                  Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
  pages        = {1616--1621},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://ieeexplore.ieee.org/document/7459571/},
  timestamp    = {Mon, 09 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/date/NurvitadhiMWVM16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/NurvitadhiSSMKM16,
  author       = {Eriko Nurvitadhi and
                  Jaewoong Sim and
                  David Sheffield and
                  Asit K. Mishra and
                  Krishnan Srivatsan and
                  Debbie Marr},
  editor       = {Paolo Ienne and
                  Walid A. Najjar and
                  Jason Helge Anderson and
                  Philip Brisk and
                  Walter Stechele},
  title        = {Accelerating recurrent neural networks in analytics servers: Comparison
                  of FPGA, CPU, GPU, and {ASIC}},
  booktitle    = {26th International Conference on Field Programmable Logic and Applications,
                  {FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/FPL.2016.7577314},
  doi          = {10.1109/FPL.2016.7577314},
  timestamp    = {Fri, 17 Jan 2020 17:11:15 +0100},
  biburl       = {https://dblp.org/rec/conf/fpl/NurvitadhiSSMKM16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/NurvitadhiSSMVM16,
  author       = {Eriko Nurvitadhi and
                  David Sheffield and
                  Jaewoong Sim and
                  Asit K. Mishra and
                  Ganesh Venkatesh and
                  Debbie Marr},
  editor       = {Yuchen Song and
                  Shaojun Wang and
                  Brent Nelson and
                  Junbao Li and
                  Yu Peng},
  title        = {Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU,
                  and {ASIC}},
  booktitle    = {2016 International Conference on Field-Programmable Technology, {FPT}
                  2016, Xi'an, China, December 7-9, 2016},
  pages        = {77--84},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/FPT.2016.7929192},
  doi          = {10.1109/FPT.2016.7929192},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/fpt/NurvitadhiSSMVM16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/GopireddySTKAM16,
  author       = {Bhargava Gopireddy and
                  Choungki Song and
                  Josep Torrellas and
                  Nam Sung Kim and
                  Aditya Agrawal and
                  Asit K. Mishra},
  title        = {ScalCore: Designing a core for voltage scalability},
  booktitle    = {2016 {IEEE} International Symposium on High Performance Computer Architecture,
                  {HPCA} 2016, Barcelona, Spain, March 12-16, 2016},
  pages        = {681--693},
  publisher    = {{IEEE} Computer Society},
  year         = {2016},
  url          = {https://doi.org/10.1109/HPCA.2016.7446104},
  doi          = {10.1109/HPCA.2016.7446104},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/GopireddySTKAM16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/NurvitadhiMM15,
  author       = {Eriko Nurvitadhi and
                  Asit K. Mishra and
                  Debbie Marr},
  editor       = {Ravi Iyer and
                  Siddharth Garg},
  title        = {A sparse matrix vector multiply accelerator for support vector machine},
  booktitle    = {2015 International Conference on Compilers, Architecture and Synthesis
                  for Embedded Systems, {CASES} 2015, Amsterdam, The Netherlands, October
                  4-9, 2015},
  pages        = {109--116},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/CASES.2015.7324551},
  doi          = {10.1109/CASES.2015.7324551},
  timestamp    = {Wed, 16 Oct 2019 14:14:51 +0200},
  biburl       = {https://dblp.org/rec/conf/cases/NurvitadhiMM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/AnsariMXT14,
  author       = {Amin Ansari and
                  Asit K. Mishra and
                  Jianping Xu and
                  Josep Torrellas},
  title        = {Tangle: Route-oriented dynamic voltage minimization for variation-afflicted,
                  energy-efficient on-chip networks},
  booktitle    = {20th {IEEE} International Symposium on High Performance Computer Architecture,
                  {HPCA} 2014, Orlando, FL, USA, February 15-19, 2014},
  pages        = {440--451},
  publisher    = {{IEEE} Computer Society},
  year         = {2014},
  url          = {https://doi.org/10.1109/HPCA.2014.6835953},
  doi          = {10.1109/HPCA.2014.6835953},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/AnsariMXT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/JogKNMKMID13,
  author       = {Adwait Jog and
                  Onur Kayiran and
                  Nachiappan Chidambaram Nachiappan and
                  Asit K. Mishra and
                  Mahmut T. Kandemir and
                  Onur Mutlu and
                  Ravishankar R. Iyer and
                  Chita R. Das},
  editor       = {Vivek Sarkar and
                  Rastislav Bod{\'{\i}}k},
  title        = {{OWL:} cooperative thread array aware scheduling techniques for improving
                  {GPGPU} performance},
  booktitle    = {Architectural Support for Programming Languages and Operating Systems,
                  {ASPLOS} 2013, Houston, TX, USA, March 16-20, 2013},
  pages        = {395--406},
  publisher    = {{ACM}},
  year         = {2013},
  url          = {https://doi.org/10.1145/2451116.2451158},
  doi          = {10.1145/2451116.2451158},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asplos/JogKNMKMID13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishraMD13,
  author       = {Asit K. Mishra and
                  Onur Mutlu and
                  Chita R. Das},
  title        = {A heterogeneous multiple network-on-chip design: an application-aware
                  approach},
  booktitle    = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
                  TX, USA, May 29 - June 07, 2013},
  pages        = {36:1--36:10},
  publisher    = {{ACM}},
  year         = {2013},
  url          = {https://doi.org/10.1145/2463209.2488779},
  doi          = {10.1145/2463209.2488779},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/MishraMD13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/CarterABCDDFGGKLMMPTTVVX13,
  author       = {Nicholas P. Carter and
                  Aditya Agrawal and
                  Shekhar Borkar and
                  Romain Cledat and
                  Howard David and
                  Dave Dunning and
                  Joshua B. Fryman and
                  Ivan Ganev and
                  Roger A. Golliver and
                  Rob C. Knauerhase and
                  Richard Lethin and
                  Beno{\^{\i}}t Meister and
                  Asit K. Mishra and
                  Wilfred R. Pinfold and
                  Justin Teller and
                  Josep Torrellas and
                  Nicolas Vasilache and
                  Ganesh Venkatesh and
                  Jianping Xu},
  title        = {Runnemede: An architecture for Ubiquitous High-Performance Computing},
  booktitle    = {19th {IEEE} International Symposium on High Performance Computer Architecture,
                  {HPCA} 2013, Shenzhen, China, February 23-27, 2013},
  pages        = {198--209},
  publisher    = {{IEEE} Computer Society},
  year         = {2013},
  url          = {https://doi.org/10.1109/HPCA.2013.6522319},
  doi          = {10.1109/HPCA.2013.6522319},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/hpca/CarterABCDDFGGKLMMPTTVVX13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/JogKMKMID13,
  author       = {Adwait Jog and
                  Onur Kayiran and
                  Asit K. Mishra and
                  Mahmut T. Kandemir and
                  Onur Mutlu and
                  Ravishankar R. Iyer and
                  Chita R. Das},
  editor       = {Avi Mendelson},
  title        = {Orchestrated scheduling and prefetching for GPGPUs},
  booktitle    = {The 40th Annual International Symposium on Computer Architecture,
                  ISCA'13, Tel-Aviv, Israel, June 23-27, 2013},
  pages        = {332--343},
  publisher    = {{ACM}},
  year         = {2013},
  url          = {https://doi.org/10.1145/2485922.2485951},
  doi          = {10.1145/2485922.2485951},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/JogKMKMID13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/SharifiMSKD12,
  author       = {Akbar Sharifi and
                  Asit K. Mishra and
                  Shekhar Srikantaiah and
                  Mahmut T. Kandemir and
                  Chita R. Das},
  editor       = {Pen{-}Chung Yew and
                  Sangyeun Cho and
                  Luiz DeRose and
                  David J. Lilja},
  title        = {{PEPON:} performance-aware hierarchical power budgeting for NoC based
                  multicores},
  booktitle    = {International Conference on Parallel Architectures and Compilation
                  Techniques, {PACT} '12, Minneapolis, MN, {USA} - September 19 - 23,
                  2012},
  pages        = {65--74},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2370816.2370828},
  doi          = {10.1145/2370816.2370828},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/IEEEpact/SharifiMSKD12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/NachiappanMKSMD12,
  author       = {Nachiappan Chidambaram Nachiappan and
                  Asit K. Mishra and
                  Mahmut T. Kandemir and
                  Anand Sivasubramaniam and
                  Onur Mutlu and
                  Chita R. Das},
  editor       = {Pen{-}Chung Yew and
                  Sangyeun Cho and
                  Luiz DeRose and
                  David J. Lilja},
  title        = {Application-aware prefetch prioritization in on-chip networks},
  booktitle    = {International Conference on Parallel Architectures and Compilation
                  Techniques, {PACT} '12, Minneapolis, MN, {USA} - September 19 - 23,
                  2012},
  pages        = {441--442},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2370816.2370886},
  doi          = {10.1145/2370816.2370886},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/IEEEpact/NachiappanMKSMD12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JogMXXNID12,
  author       = {Adwait Jog and
                  Asit K. Mishra and
                  Cong Xu and
                  Yuan Xie and
                  Vijaykrishnan Narayanan and
                  Ravishankar R. Iyer and
                  Chita R. Das},
  editor       = {Patrick Groeneveld and
                  Donatella Sciuto and
                  Soha Hassoun},
  title        = {Cache revive: architecting volatile {STT-RAM} caches for enhanced
                  performance in CMPs},
  booktitle    = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
                  Francisco, CA, USA, June 3-7, 2012},
  pages        = {243--252},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2228360.2228406},
  doi          = {10.1145/2228360.2228406},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dac/JogMXXNID12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/SaripalliSMXDN11,
  author       = {Vinay Saripalli and
                  Guangyu Sun and
                  Asit K. Mishra and
                  Yuan Xie and
                  Suman Datta and
                  Vijaykrishnan Narayanan},
  title        = {Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors},
  journal      = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
  volume       = {1},
  number       = {2},
  pages        = {109--119},
  year         = {2011},
  url          = {https://doi.org/10.1109/JETCAS.2011.2158343},
  doi          = {10.1109/JETCAS.2011.2158343},
  timestamp    = {Sun, 19 May 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/esticas/SaripalliSMXDN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jpdc/MishraYDEIVD11,
  author       = {Asit K. Mishra and
                  Aditya Yanamandra and
                  Reetuparna Das and
                  Soumya Eachempati and
                  Ravi R. Iyer and
                  Narayanan Vijaykrishnan and
                  Chita R. Das},
  title        = {{RAFT:} {A} router architecture with frequency tuning for on-chip
                  networks},
  journal      = {J. Parallel Distributed Comput.},
  volume       = {71},
  number       = {5},
  pages        = {625--640},
  year         = {2011},
  url          = {https://doi.org/10.1016/j.jpdc.2010.09.005},
  doi          = {10.1016/J.JPDC.2010.09.005},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jpdc/MishraYDEIVD11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SaripalliMDN11,
  author       = {Vinay Saripalli and
                  Asit K. Mishra and
                  Suman Datta and
                  Vijaykrishnan Narayanan},
  editor       = {Leon Stok and
                  Nikil D. Dutt and
                  Soha Hassoun},
  title        = {An energy-efficient heterogeneous {CMP} based on hybrid {TFET-CMOS}
                  cores},
  booktitle    = {Proceedings of the 48th Design Automation Conference, {DAC} 2011,
                  San Diego, California, USA, June 5-10, 2011},
  pages        = {729--734},
  publisher    = {{ACM}},
  year         = {2011},
  url          = {https://doi.org/10.1145/2024724.2024889},
  doi          = {10.1145/2024724.2024889},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/SaripalliMDN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/JiangMZIFSMBD11,
  author       = {Xiaowei Jiang and
                  Asit K. Mishra and
                  Li Zhao and
                  Ravishankar R. Iyer and
                  Zhen Fang and
                  Sadagopan Srinivasan and
                  Srihari Makineni and
                  Paul Brett and
                  Chita R. Das},
  title        = {{ACCESS:} Smart scheduling for asymmetric cache CMPs},
  booktitle    = {17th International Conference on High-Performance Computer Architecture
                  {(HPCA-17} 2011), February 12-16 2011, San Antonio, Texas, {USA}},
  pages        = {527--538},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/HPCA.2011.5749757},
  doi          = {10.1109/HPCA.2011.5749757},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/hpca/JiangMZIFSMBD11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/MishraDSXVD11,
  author       = {Asit K. Mishra and
                  Xiangyu Dong and
                  Guangyu Sun and
                  Yuan Xie and
                  Narayanan Vijaykrishnan and
                  Chita R. Das},
  editor       = {Ravi R. Iyer and
                  Qing Yang and
                  Antonio Gonz{\'{a}}lez},
  title        = {Architecting on-chip interconnects for stacked 3D {STT-RAM} caches
                  in CMPs},
  booktitle    = {38th International Symposium on Computer Architecture {(ISCA} 2011),
                  June 4-8, 2011, San Jose, CA, {USA}},
  pages        = {69--80},
  publisher    = {{ACM}},
  year         = {2011},
  url          = {https://doi.org/10.1145/2000064.2000074},
  doi          = {10.1145/2000064.2000074},
  timestamp    = {Mon, 15 May 2023 22:11:15 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/MishraDSXVD11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/MishraVD11,
  author       = {Asit K. Mishra and
                  Narayanan Vijaykrishnan and
                  Chita R. Das},
  editor       = {Ravi R. Iyer and
                  Qing Yang and
                  Antonio Gonz{\'{a}}lez},
  title        = {A case for heterogeneous on-chip interconnects for CMPs},
  booktitle    = {38th International Symposium on Computer Architecture {(ISCA} 2011),
                  June 4-8, 2011, San Jose, CA, {USA}},
  pages        = {389--400},
  publisher    = {{ACM}},
  year         = {2011},
  url          = {https://doi.org/10.1145/2000064.2000111},
  doi          = {10.1145/2000064.2000111},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/MishraVD11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sigmetrics/SharifiSMKD11,
  author       = {Akbar Sharifi and
                  Shekhar Srikantaiah and
                  Asit K. Mishra and
                  Mahmut T. Kandemir and
                  Chita R. Das},
  editor       = {Arif Merchant and
                  Kimberly Keeton and
                  Dan Rubenstein},
  title        = {{METE:} meeting end-to-end QoS in multicores through system-wide resource
                  management},
  booktitle    = {{SIGMETRICS} 2011, Proceedings of the 2011 {ACM} {SIGMETRICS} International
                  Conference on Measurement and Modeling of Computer Systems, San Jose,
                  CA, USA, 07-11 June 2011 (Co-located with {FCRC} 2011)},
  pages        = {13--24},
  publisher    = {{ACM}},
  year         = {2011},
  url          = {https://doi.org/10.1145/1993744.1993747},
  doi          = {10.1145/1993744.1993747},
  timestamp    = {Sun, 01 Aug 2021 14:20:40 +0200},
  biburl       = {https://dblp.org/rec/conf/sigmetrics/SharifiSMKD11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigmetrics/MishraHCD10,
  author       = {Asit K. Mishra and
                  Joseph L. Hellerstein and
                  Walfredo Cirne and
                  Chita R. Das},
  title        = {Towards characterizing cloud backend workloads: insights from Google
                  compute clusters},
  journal      = {{SIGMETRICS} Perform. Evaluation Rev.},
  volume       = {37},
  number       = {4},
  pages        = {34--41},
  year         = {2010},
  url          = {https://doi.org/10.1145/1773394.1773400},
  doi          = {10.1145/1773394.1773400},
  timestamp    = {Sat, 25 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigmetrics/MishraHCD10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sc/MishraSKD10,
  author       = {Asit K. Mishra and
                  Shekhar Srikantaiah and
                  Mahmut T. Kandemir and
                  Chita R. Das},
  title        = {{CPM} in CMPs: Coordinated Power Management in Chip-Multiprocessors},
  booktitle    = {Conference on High Performance Computing Networking, Storage and Analysis,
                  {SC} 2010, New Orleans, LA, USA, November 13-19, 2010},
  pages        = {1--12},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/SC.2010.15},
  doi          = {10.1109/SC.2010.15},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/sc/MishraSKD10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sigmetrics/MishraSKD10,
  author       = {Asit K. Mishra and
                  Shekhar Srikantaiah and
                  Mahmut T. Kandemir and
                  Chita R. Das},
  editor       = {Vishal Misra and
                  Paul Barford and
                  Mark S. Squillante},
  title        = {Coordinated power management of voltage islands in CMPs},
  booktitle    = {{SIGMETRICS} 2010, Proceedings of the 2010 {ACM} {SIGMETRICS} International
                  Conference on Measurement and Modeling of Computer Systems, New York,
                  New York, USA, 14-18 June 2010},
  pages        = {359--360},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811039.1811086},
  doi          = {10.1145/1811039.1811086},
  timestamp    = {Fri, 30 Jul 2021 16:13:32 +0200},
  biburl       = {https://dblp.org/rec/conf/sigmetrics/MishraSKD10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/DasEMVD09,
  author       = {Reetuparna Das and
                  Soumya Eachempati and
                  Asit K. Mishra and
                  Narayanan Vijaykrishnan and
                  Chita R. Das},
  title        = {Design and evaluation of a hierarchical on-chip interconnect for next-generation
                  CMPs},
  booktitle    = {15th International Conference on High-Performance Computer Architecture
                  {(HPCA-15} 2009), 14-18 February 2009, Raleigh, North Carolina, {USA}},
  pages        = {175--186},
  publisher    = {{IEEE} Computer Society},
  year         = {2009},
  url          = {https://doi.org/10.1109/HPCA.2009.4798252},
  doi          = {10.1109/HPCA.2009.4798252},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/hpca/DasEMVD09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/MishraIDVED09,
  author       = {Asit K. Mishra and
                  Reetuparna Das and
                  Soumya Eachempati and
                  Ravishankar R. Iyer and
                  Narayanan Vijaykrishnan and
                  Chita R. Das},
  editor       = {David H. Albonesi and
                  Margaret Martonosi and
                  David I. August and
                  Jos{\'{e}} F. Mart{\'{\i}}nez},
  title        = {A case for dynamic frequency tuning in on-chip networks},
  booktitle    = {42st Annual {IEEE/ACM} International Symposium on Microarchitecture
                  {(MICRO-42} 2009), December 12-16, 2009, New York, New York, {USA}},
  pages        = {292--303},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1669112.1669151},
  doi          = {10.1145/1669112.1669151},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/MishraIDVED09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sc/SrikantaiahDMDK09,
  author       = {Shekhar Srikantaiah and
                  Reetuparna Das and
                  Asit K. Mishra and
                  Chita R. Das and
                  Mahmut T. Kandemir},
  title        = {A case for integrated processor-cache partitioning in chip multiprocessors},
  booktitle    = {Proceedings of the {ACM/IEEE} Conference on High Performance Computing,
                  {SC} 2009, November 14-20, 2009, Portland, Oregon, {USA}},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1654059.1654066},
  doi          = {10.1145/1654059.1654066},
  timestamp    = {Tue, 06 Nov 2018 16:59:29 +0100},
  biburl       = {https://dblp.org/rec/conf/sc/SrikantaiahDMDK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/DasMNPNIYD08,
  author       = {Reetuparna Das and
                  Asit K. Mishra and
                  Chrysostomos Nicopoulos and
                  Dongkook Park and
                  Vijaykrishnan Narayanan and
                  Ravishankar R. Iyer and
                  Mazin S. Yousif and
                  Chita R. Das},
  title        = {Performance and power optimization through data compression in Network-on-Chip
                  architectures},
  booktitle    = {14th International Conference on High-Performance Computer Architecture
                  {(HPCA-14} 2008), 16-20 February 2008, Salt Lake City, UT, {USA}},
  pages        = {215--225},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/HPCA.2008.4658641},
  doi          = {10.1109/HPCA.2008.4658641},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/DasMNPNIYD08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iciis/MishraRP08,
  author       = {Asit K. Mishra and
                  Aurobinda Routray and
                  Ashok Kumar Pradhan},
  title        = {Detection of Arcing in Low Voltage Distribution Systems},
  booktitle    = {{IEEE} Reglon 10 Colloquium and Third International Conference on
                  Industrial and Information Systems, {ICIIS} 2008, Kharagpur, India,
                  December 8-10, 2008},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ICIINFS.2008.4798477},
  doi          = {10.1109/ICIINFS.2008.4798477},
  timestamp    = {Wed, 07 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iciis/MishraRP08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ParkEDMXVD08,
  author       = {Dongkook Park and
                  Soumya Eachempati and
                  Reetuparna Das and
                  Asit K. Mishra and
                  Yuan Xie and
                  Narayanan Vijaykrishnan and
                  Chita R. Das},
  title        = {{MIRA:} {A} Multi-layered On-Chip Interconnect Router Architecture},
  booktitle    = {35th International Symposium on Computer Architecture {(ISCA} 2008),
                  June 21-25, 2008, Beijing, China},
  pages        = {251--261},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISCA.2008.13},
  doi          = {10.1109/ISCA.2008.13},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ParkEDMXVD08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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