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ORCIDBibTeX records: Sanu Mathew
@article{DBLP:journals/jssc/KumarVTTDM24,
author = {Raghavan Kumar and
Avinash L. Varna and
Carlos Tokunaga and
Sachin Taneja and
Vivek De and
Sanu K. Mathew},
title = {A 100-Gbps Fault-Injection Attack-Resistant {AES-256} Engine With
99.1{\%}-99.99{\%} Error Coverage in Intel 4 {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {79--89},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3305188},
doi = {10.1109/JSSC.2023.3305188},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KumarVTTDM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiWMDS24,
author = {Mao Li and
Zhaoqing Wang and
Sanu K. Mathew and
Vivek De and
Mingoo Seok},
title = {16.6 {PACTOR:} {A} Variation-Tolerant Probing-Attack Detector for
a 2.5Gb/s{\texttimes}4-Channel Chip-to-Chip Interface in 28nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {306--308},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454309},
doi = {10.1109/ISSCC49657.2024.10454309},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/LiWMDS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/OrugantiWIWYKMK24,
author = {Sirish Oruganti and
Meizhi Wang and
Vishnuvardhan V. Iyer and
Yipeng Wang and
Mengtian Yang and
Raghavan Kumar and
Sanu K. Mathew and
Jaydeep P. Kulkarni},
title = {Power and {EM} Side-Channel-Attack-Resilient {AES-128} Core with Round-Aligned
Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable
Replica Circuits},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {308--310},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454574},
doi = {10.1109/ISSCC49657.2024.10454574},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/OrugantiWIWYKMK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HossainRMSW23,
author = {Masum Hossain and
Arijit Raychowdhury and
Sanu K. Mathew and
Yakun Sophia Shao and
Yih Wang},
title = {Guest Editorial Introduction to the Special Issue on the 2022 {IEEE}
International Solid-State Circuits Conference {(ISSCC)}},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {1},
pages = {3--7},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3225691},
doi = {10.1109/JSSC.2022.3225691},
timestamp = {Mon, 09 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HossainRMSW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KumarSTAHADM23,
author = {Raghavan Kumar and
Vikram B. Suresh and
Sachin Taneja and
Mark A. Anders and
Steven Hsu and
Amit Agarwal and
Vivek De and
Sanu K. Mathew},
title = {A 7-Gbps SCA-Resistant Multiplicative-Masked {AES} Engine in Intel
4 {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {4},
pages = {1106--1116},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3230372},
doi = {10.1109/JSSC.2022.3230372},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KumarSTAHADM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KumarVTTDM23,
author = {Raghavan Kumar and
Avinash Varna and
Carlos Tokunaga and
Sachin Taneja and
Vivek De and
Sanu Mathew},
title = {A 100Gbps Fault-Injection Attack Resistant {AES-256} Engine with 99.1-to-99.99{\%}
Error Coverage in Intel 4 {CMOS}},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {244--245},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067715},
doi = {10.1109/ISSCC42615.2023.10067715},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KumarVTTDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/TanejaSKDM23,
author = {Sachin Taneja and
Vikram B. Suresh and
Raghavan Kumar and
Vivek De and
Sanu Mathew},
title = {218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication
Accelerator with a Crypto-Double-Coupled {PUF} in 4nm class {CMOS}},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185214},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185214},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/TanejaSKDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasNCKLKSMGS22,
author = {Debayan Das and
Mayukh Nath and
Baibhab Chatterjee and
Raghavan Kumar and
Xiaosen Liu and
Harish Krishnamurthy and
Manoj R. Sastry and
Sanu Mathew and
Santosh Ghosh and
Shreyas Sen},
title = {{EM} {SCA} White-Box Analysis-Based Reduced Leakage Cell Design and
Presilicon Evaluation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {4927--4938},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3144369},
doi = {10.1109/TCAD.2022.3144369},
timestamp = {Mon, 02 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DasNCKLKSMGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/WangOXKMK22,
author = {Meizhi Wang and
Sirish Oruganti and
Shanshan Xie and
Raghavan Kumar and
Sanu Mathew and
Jaydeep P. Kulkarni},
title = {Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure
{AES} Core with Stacked Voltage Domains and Spatio-temporally Randomized
Circuit Blocks},
booktitle = {48th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2022,
Milan, Italy, September 19-22, 2022},
pages = {529--532},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ESSCIRC55480.2022.9911449},
doi = {10.1109/ESSCIRC55480.2022.9911449},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/WangOXKMK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Mathew22,
author = {Sanu K. Mathew},
editor = {Ioannis Savidis and
Avesta Sasan and
Himanshu Thapliyal and
Ronald F. DeMara},
title = {Attack-Resistant Circuit Technologies for sub-5nm Secure Computing
Platforms},
booktitle = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
June 6 - 8, 2022},
pages = {403},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3526241.3530053},
doi = {10.1145/3526241.3530053},
timestamp = {Fri, 03 Jun 2022 08:45:20 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/Mathew22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KumarS0H0DM22,
author = {Raghavan Kumar and
Vikram B. Suresh and
Mark A. Anders and
Steven K. Hsu and
Amit Agarwal and
Vivek K. De and
Sanu K. Mathew},
title = {An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk
{AES} Engine in Intel 4 {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731739},
doi = {10.1109/ISSCC42614.2022.9731739},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KumarS0H0DM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SureshKRZPRGMH22,
author = {Vikram B. Suresh and
Chandra S. Katta and
Srinivasan Rajagopalan and
Tao Z. Zhou and
Amit Kumar Patel and
Raju Rakha and
Nikhil Krishna Gopalakrishna and
Sanu Mathew and
Ajat Hukkoo},
title = {Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining
{ASIC}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {354--356},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731547},
doi = {10.1109/ISSCC42614.2022.9731547},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SureshKRZPRGMH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/KumarST0H0DM22,
author = {Raghavan Kumar and
Vikram B. Suresh and
Sachin Taneja and
Mark A. Anders and
Steven Hsu and
Amit Agarwal and
Vivek De and
Sanu Mathew},
title = {A 7Gbps SCA-Resistant Multiplicative-Masked {AES} Engine in Intel
4 {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {138--139},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830470},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830470},
timestamp = {Thu, 04 Aug 2022 10:53:40 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/KumarST0H0DM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DasDGMMCSCVKMGR21,
author = {Debayan Das and
Josef Danial and
Anupam Golder and
Nirmoy Modak and
Shovan Maity and
Baibhab Chatterjee and
Dong{-}Hyun Seo and
Muya Chang and
Avinash Varna and
Harish K. Krishnamurthy and
Sanu Mathew and
Santosh Ghosh and
Arijit Raychowdhury and
Shreyas Sen},
title = {{EM} and Power SCA-Resilient {AES-256} Through {\textgreater}350{\texttimes}
Current-Domain Signature Attenuation and Local Lower Metal Routing},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {1},
pages = {136--150},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3032975},
doi = {10.1109/JSSC.2020.3032975},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/DasDGMMCSCVKMGR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KumarLSKSAKRDM21,
author = {Raghavan Kumar and
Xiaosen Liu and
Vikram B. Suresh and
Harish K. Krishnamurthy and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Krishnan Ravichandran and
Vivek De and
Sanu K. Mathew},
title = {A Time-/Frequency-Domain Side-Channel Attack Resistant {AES-128} and
{RSA-4K} Crypto-Processor in 14-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {4},
pages = {1141--1151},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3052146},
doi = {10.1109/JSSC.2021.3052146},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KumarLSKSAKRDM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/WangIXLMKOYK21,
author = {Meizhi Wang and
Vishnuvardhan V. Iyer and
Shanshan Xie and
Ge Li and
Sanu K. Mathew and
Raghavan Kumar and
Michael Orshansky and
Ali E. Yilmaz and
Jaydeep P. Kulkarni},
title = {Physical Design Strategies for Mitigating Fine-Grained Electromagnetic
Side-Channel Attacks},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2021, Austin,
TX, USA, April 25-30, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CICC51472.2021.9431438},
doi = {10.1109/CICC51472.2021.9431438},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/WangIXLMKOYK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MathewDM21,
author = {Sanu Mathew and
Shidhartha Das and
Hugh Mair},
title = {Session 4 Overview: Processors Digital Architectures and Systems Subcommittee},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {52--53},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365772},
doi = {10.1109/ISSCC42613.2021.9365772},
timestamp = {Wed, 10 Mar 2021 15:02:58 +0100},
biburl = {https://dblp.org/rec/conf/isscc/MathewDM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinghKCMRDM20,
author = {Arvind Singh and
Monodeep Kar and
Venkata Chaitanya Krishna Chekuri and
Sanu K. Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Enhanced Power and Electromagnetic {SCA} Resistance of Encryption
Engines via a Security-Aware Integrated All-Digital {LDO}},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {2},
pages = {478--493},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2945944},
doi = {10.1109/JSSC.2019.2945944},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinghKCMRDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KumarSKSAKAHCKD20,
author = {Raghavan Kumar and
Vikram B. Suresh and
Monodeep Kar and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram K. Krishnamurthy and
Vivek De and
Sanu K. Mathew},
title = {A 4900- {\textdollar}{\textbackslash}mu{\textdollar} m\({}^{\mbox{2}}\)
839-Mb/s Side-Channel Attack- Resistant {AES-128} in 14-nm {CMOS}
With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail
Key Addition},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {4},
pages = {945--955},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2960482},
doi = {10.1109/JSSC.2019.2960482},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KumarSKSAKAHCKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SureshKM20,
author = {Vikram B. Suresh and
Raghavan Kumar and
Sanu Mathew},
title = {{INVITED:} {A} 0.26{\%} BER, Machine-Learning Resistant 10\({}^{\mbox{28}}\)
Challenge-Response {PUF} in 14nm {CMOS} Featuring Stability-Aware
Adversarial Challenge Selection},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--3},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218720},
doi = {10.1109/DAC18072.2020.9218720},
timestamp = {Wed, 14 Oct 2020 10:56:17 +0200},
biburl = {https://dblp.org/rec/conf/dac/SureshKM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/0001HRACKKSKKMK20,
author = {Amit Agarwal and
Steven Hsu and
Simeon Realov and
Mark A. Anders and
Gregory K. Chen and
Monodeep Kar and
Raghavan Kumar and
Huseyin Sumbul and
Phil C. Knag and
Himanshu Kaul and
Sanu Mathew and
Mahesh Kumashikar and
Ram Krishnamurthy and
Vivek De},
title = {25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN
Characterization Circuits in 10nm {CMOS}},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {392--394},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062941},
doi = {10.1109/ISSCC19947.2020.9062941},
timestamp = {Thu, 03 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/0001HRACKKSKKMK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AndersKKCKSKKH020,
author = {Mark A. Anders and
Himanshu Kaul and
Seongjong Kim and
Gregory K. Chen and
Raghavan Kumar and
Huseyin Ekin Sumbul and
Phil C. Knag and
Monodeep Kar and
Steven K. Hsu and
Amit Agarwal and
Vikram B. Suresh and
Sanu K. Mathew and
Ram K. Krishnamurthy and
Vivek De},
title = {25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits
in 10nm {CMOS} for High-Performance Processors with Wide Voltage-Frequency
Operating Range},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {396--398},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063158},
doi = {10.1109/ISSCC19947.2020.9063158},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/AndersKKCKSKKH020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DasDGMMCSCVKMGR20,
author = {Debayan Das and
Josef Danial and
Anupam Golder and
Nirmoy Modak and
Shovan Maity and
Baibhab Chatterjee and
Dong{-}Hyun Seo and
Muya Chang and
Avinash Varna and
Harish Krishnamurthy and
Sanu Mathew and
Santosh Ghosh and
Arijit Raychowdhury and
Shreyas Sen},
title = {27.3 {EM} and Power SCA-Resilient {AES-256} in 65nm {CMOS} Through
{\textgreater}350{\texttimes} Current-Domain Signature Attenuation},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {424--426},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062997},
doi = {10.1109/ISSCC19947.2020.9062997},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/DasDGMMCSCVKMGR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Hsu0RACKKSKKSMR20,
author = {Steven Hsu and
Amit Agarwal and
Simeon Realov and
Mark A. Anders and
Gregory K. Chen and
Monodeep Kar and
Raghavan Kumar and
Huseyin Sumbul and
Phil C. Knag and
Himanshu Kaul and
Vikram B. Suresh and
Sanu Mathew and
Iqbal Rajwani and
Satish Damaraju and
Ram Krishnamurthy and
Vivek De},
title = {Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI
Processors in 10nm {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9163007},
doi = {10.1109/VLSICIRCUITS18222.2020.9163007},
timestamp = {Sun, 03 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Hsu0RACKKSKKSMR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarLSKAKRDM20,
author = {Raghavan Kumar and
Xiaosen Liu and
Vikram B. Suresh and
Harish Krishnamurthy and
Mark A. Anders and
Himanshu Kaul and
Krishnan Ravichandran and
Vivek De and
Sanu Mathew},
title = {A SCA-Resistant {AES} Engine in 14nm {CMOS} with Time/Frequency-Domain
Leakage Suppression using Non-Linear Digital {LDO} Cascaded with Arithmetic
Countermeasures},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162988},
doi = {10.1109/VLSICIRCUITS18222.2020.9162988},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarLSKAKRDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarSSAKDM20,
author = {Raghavan Kumar and
Sudhir Satpathy and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Vivek De and
Sanu Mathew},
title = {A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor
for Secure {RSA-4K} Public-Key Encryption in 14nm {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162905},
doi = {10.1109/VLSICIRCUITS18222.2020.9162905},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarSSAKDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SureshKAKDM20,
author = {Vikram B. Suresh and
Raghavan Kumar and
Mark A. Anders and
Himanshu Kaul and
Vivek De and
Sanu Mathew},
title = {A 0.26{\%} BER, 10\({}^{\mbox{28}}\) Challenge-Response Machine-Learning
Resistant Strong-PUF in 14nm {CMOS} Featuring Stability-Aware Adversarial
Challenge Selection},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162890},
doi = {10.1109/VLSICIRCUITS18222.2020.9162890},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SureshKAKDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinghKMRDM19,
author = {Arvind Singh and
Monodeep Kar and
Sanu K. Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Improved Power/EM Side-Channel Attack Resistance of 128-Bit {AES}
Engines With Random Fast Voltage Dithering},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {2},
pages = {569--583},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2875112},
doi = {10.1109/JSSC.2018.2875112},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinghKMRDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SatpathyMKSAKAH19,
author = {Sudhir Satpathy and
Sanu K. Mathew and
Raghavan Kumar and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram K. Krishnamurthy and
Vivek De},
title = {An All-Digital Unified Physically Unclonable Function and True Random
Number Generator Featuring Self-Calibrating Hierarchical Von Neumann
Extraction in 14-nm Tri-gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {4},
pages = {1074--1085},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2886350},
doi = {10.1109/JSSC.2018.2886350},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SatpathyMKSAKAH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/KaulAMKK19,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu Mathew and
Seongjong Kim and
Ram Krishnamurthy},
editor = {Naofumi Takagi and
Sylvie Boldo and
Martin Langhammer},
title = {Optimized Fused Floating-Point Many-Term Dot-Product Hardware for
Machine Learning Accelerators},
booktitle = {26th {IEEE} Symposium on Computer Arithmetic, {ARITH} 2019, Kyoto,
Japan, June 10-12, 2019},
pages = {84--87},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ARITH.2019.00021},
doi = {10.1109/ARITH.2019.00021},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/KaulAMKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/0001HKAKKSMKD19,
author = {Amit Agarwal and
Steven Hsu and
Monodeep Kar and
Mark A. Anders and
Himanshu Kaul and
Raghavan Kumar and
Vikram B. Suresh and
Sanu Mathew and
Ram Krishnamurthy and
Vivek De},
title = {A 54{\%} Power-Saving Static Fully-Interruptible Single-Phase-Clocked
Shared-Keeper Flip-Flop in 14nm {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {137--140},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056939},
doi = {10.1109/A-SSCC47793.2019.9056939},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/0001HKAKKSMKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SatpathySKGGYAK19,
author = {Sudhir Satpathy and
Vikram B. Suresh and
Raghavan Kumar and
Vinodh Gopal and
James Guilford and
Kirk Yap and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Sanu Mathew},
title = {A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for {DEFLATE}
Compression in 14nm {CMOS}},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2019, Austin,
TX, USA, April 14-17, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CICC.2019.8780272},
doi = {10.1109/CICC.2019.8780272},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/SatpathySKGGYAK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SureshSKAK0HKM19,
author = {Vikram B. Suresh and
Sudhir Satpathy and
Raghavan Kumar and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Sanu Mathew},
title = {A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive
Platforms in 14nm {CMOS}},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2019, Austin,
TX, USA, April 14-17, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CICC.2019.8780302},
doi = {10.1109/CICC.2019.8780302},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/SureshSKAK0HKM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SinghKMRDM19,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {A 128b {AES} Engine with Higher Resistance to Power and Electromagnetic
Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital
Low-Dropout Regulator},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {404--406},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662344},
doi = {10.1109/ISSCC.2019.8662344},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SinghKMRDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SureshSKAK0HKDM19,
author = {Vikram B. Suresh and
Sudhir Satpathy and
Raghavan Kumar and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm {CMOS} Featuring
Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {32},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777966},
doi = {10.23919/VLSIC.2019.8777966},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SureshSKAK0HKDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Hsu0KAKKSSMKD19,
author = {Steven Hsu and
Amit Agarwal and
Monodeep Kar and
Mark A. Anders and
Himanshu Kaul and
Raghavan Kumar and
Sudhir Satpathy and
Vikram B. Suresh and
Sanu Mathew and
Ram Krishnamurthy and
Vivek De},
title = {A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power
{AOI} Clocked Circuits in 14nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {50},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777978},
doi = {10.23919/VLSIC.2019.8777978},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Hsu0KAKKSSMKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarSKSAKAHCKD19,
author = {Raghavan Kumar and
Vikram B. Suresh and
Monodeep Kar and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 4900{\texttimes}m\({}^{\mbox{2}}\) 839Mbps Side-Channel Attack Resistant
{AES-128} in 14nm {CMOS} with Heterogeneous Sboxes, Linear Masked
MixColumns and Dual-Rail Key Addition},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {234},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778041},
doi = {10.23919/VLSIC.2019.8778041},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarSKSAKAHCKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathySKGGAKA19,
author = {Sudhir Satpathy and
Vikram B. Suresh and
Raghavan Kumar and
Vinodh Gopal and
James Guilford and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 1.4GHz 20.5Gbps {GZIP} decompression accelerator in 14nm {CMOS}
featuring dual-path out-of-order speculative Huffman decoder and multi-write
enabled register file array},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {238},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777934},
doi = {10.23919/VLSIC.2019.8777934},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathySKGGAKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KarSMRDM18,
author = {Monodeep Kar and
Arvind Singh and
Sanu K. Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Reducing Power Side-Channel Information Leakage of {AES} Engines Using
Fully Integrated Inductive Voltage Regulator},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {8},
pages = {2399--2414},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2018.2822691},
doi = {10.1109/JSSC.2018.2822691},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KarSMRDM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/KaulAMSSAHK18,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu Mathew and
Vikram B. Suresh and
Sudhir Satpathy and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W {SIMON} 32/64
Cipher Accelerators for IoT in 14nm Tri-gate {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579274},
doi = {10.1109/ASSCC.2018.8579274},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/KaulAMSSAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/SatpathyMSGGAKA18,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Vinodh Gopal and
James Guilford and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {A 280mV 3.1pJ/code Huffman Decoder for {DEFLATE} Decompression Featuring
Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate
{CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {263--266},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579341},
doi = {10.1109/ASSCC.2018.8579341},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/SatpathyMSGGAKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MathewSSK18,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Ram Krishnamurthy},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Ultra-low energy circuit building blocks for security technologies},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {391--394},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342041},
doi = {10.23919/DATE.2018.8342041},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/MathewSSK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SinghKMRDM18,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Exploiting on-chip power management for side-channel security},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {401--406},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342043},
doi = {10.23919/DATE.2018.8342043},
timestamp = {Tue, 24 Apr 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SinghKMRDM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SatpathyMSGGAKA18,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Vinodh Gopal and
James Guilford and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Kam Krisnnamurthy},
title = {34.4Mbps 1.56Tbps/W {DEFLATE} Decompression Accelerator Featuring
Block-Adaptive Huffman Decoder in 14nm Tri-Gate {CMOS} for IoT Platforms},
booktitle = {44th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2018,
Dresden, Germany, September 3-6, 2018},
pages = {90--93},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ESSCIRC.2018.8494238},
doi = {10.1109/ESSCIRC.2018.8494238},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/SatpathyMSGGAKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SureshSMAKAHK18,
author = {Vikram B. Suresh and
Sudhir Satpathy and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {A 230mV-950mV 2.8Tbps/W Unified {SHA256/SM3} Secure Hashing Hardware
Accelerator in 14nm Tri-Gate {CMOS}},
booktitle = {44th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2018,
Dresden, Germany, September 3-6, 2018},
pages = {98--101},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ESSCIRC.2018.8494257},
doi = {10.1109/ESSCIRC.2018.8494257},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/SureshSMAKAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/SaxenaMS18,
author = {Nirmal R. Saxena and
Sanu Mathew and
Krishna Saraswat},
title = {Keynote 1: The road to resilient computing in autonomous driving is
paved with redundancy},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2018, Burlingame,
CA, USA, March 11-15, 2018},
pages = {1--3},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IRPS.2018.8353536},
doi = {10.1109/IRPS.2018.8353536},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/irps/SaxenaMS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AndersKMSSAHK18,
author = {Mark A. Anders and
Himanshu Kaul and
Sanu Mathew and
Vikram B. Suresh and
Sudhir Satpathy and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator
with Unified {INT8/INTI6/FP16} Datapath in 14NM Tri-Gate {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {39--40},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502333},
doi = {10.1109/VLSIC.2018.8502333},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/AndersKMSSAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathyMSAKAHK18,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De},
title = {An All-Digital Unified Static/Dynamic Entropy Generator Featuring
Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving
Mutual Authentication in IoT Mote Platforms},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {169--170},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502369},
doi = {10.1109/VLSIC.2018.8502369},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathyMSAKAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathySMAKAHK18,
author = {Sudhir Satpathy and
Vikram B. Suresh and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {220MV-900MV 794/584/754 {GBPS/W} Reconfigurable GF(2\({}^{\mbox{4}}\))2
AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate
{CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {175--176},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502262},
doi = {10.1109/VLSIC.2018.8502262},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathySMAKAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1802-09096,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Santosh Ghosh and
Anand Rajan and
Vivek De and
Raheem A. Beyah and
Saibal Mukhopadhyay},
title = {Blindsight: Blinding {EM} Side-Channel Leakage using Built-In Fully
Integrated Inductive Voltage Regulator},
journal = {CoRR},
volume = {abs/1802.09096},
year = {2018},
url = {http://arxiv.org/abs/1802.09096},
eprinttype = {arXiv},
eprint = {1802.09096},
timestamp = {Fri, 12 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1802-09096.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jhss/SinghKMRDM17,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Reducing Side-Channel Leakage of Encryption Engines Using Integrated
Low-Dropout Voltage Regulators},
journal = {J. Hardw. Syst. Secur.},
volume = {1},
number = {4},
pages = {340--355},
year = {2017},
url = {https://doi.org/10.1007/s41635-017-0023-0},
doi = {10.1007/S41635-017-0023-0},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jhss/SinghKMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SatpathyMSAKAHC17,
author = {Sudhir Satpathy and
Sanu K. Mathew and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram K. Krishnamurthy and
Vivek K. De},
title = {A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With
Selective Bit Destabilization in 14-nm Trigate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {4},
pages = {940--949},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2636859},
doi = {10.1109/JSSC.2016.2636859},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SatpathyMSAKAHC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/MathewSSK17,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Ram K. Krishnamurthy},
title = {Energy efficient and ultra low voltage security circuits for nanoscale
{CMOS} technologies},
booktitle = {2017 {IEEE} Custom Integrated Circuits Conference, {CICC} 2017, Austin,
TX, USA, April 30 - May 3, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/CICC.2017.7993609},
doi = {10.1109/CICC.2017.7993609},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/MathewSSK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SinghKMRDM17,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Improved power side channel attack resistance of a 128-bit {AES} engine
with random fast voltage dithering},
booktitle = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
Leuven, Belgium, September 11-14, 2017},
pages = {51--54},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ESSCIRC.2017.8094523},
doi = {10.1109/ESSCIRC.2017.8094523},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/SinghKMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KarSMRDM17,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Invited paper: Low power requirements and side-channel protection
of encryption engines: Challenges and opportunities},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--2},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009186},
doi = {10.1109/ISLPED.2017.8009186},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/KarSMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/MathewSSK17,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Ram Krishnamurthy},
title = {Invited paper: Ultra-low energy security circuit primitives for IoT
platforms},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009185},
doi = {10.1109/ISLPED.2017.8009185},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/MathewSSK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KarSMRDM17,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {8.1 Improved power-side-channel-attack resistance of an {AES-128}
core via a security-aware integrated buck voltage regulator},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {142--143},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870301},
doi = {10.1109/ISSCC.2017.7870301},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KarSMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Mathew17,
author = {Sanu Mathew},
title = {Security keynote: Ultra-low-energy security circuit primitives for
IoT platforms},
booktitle = {{IEEE} International Test Conference, {ITC} 2017, Fort Worth, TX,
USA, October 31 - Nov. 2, 2017},
pages = {1},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/TEST.2017.8242026},
doi = {10.1109/TEST.2017.8242026},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/itc/Mathew17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewJSSNAKAHC16,
author = {Sanu K. Mathew and
David Johnston and
Sudhir Satpathy and
Vikram B. Suresh and
Paul Newman and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram K. Krishnamurthy},
title = {{\(\mathrm{\mu}\)}RNG: {A} 300-950 mV, 323 Gbps/W All-Digital Full-Entropy
True Random Number Generator in 14 nm FinFET {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {7},
pages = {1695--1704},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2016.2558490},
doi = {10.1109/JSSC.2016.2558490},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/MathewJSSNAKAHC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/GueronM16,
author = {Shay Gueron and
Sanu Mathew},
editor = {Paolo Montuschi and
Michael J. Schulte and
Javier Hormigo and
Stuart F. Oberman and
Nathalie Revol},
title = {Hardware Implementation of {AES} Using Area-Optimal Polynomials for
Composite-Field Representation GF(2{\^{}}4){\^{}}2 of GF(2{\^{}}8)},
booktitle = {23nd {IEEE} Symposium on Computer Arithmetic, {ARITH} 2016, Silicon
Valley, CA, USA, July 10-13, 2016},
pages = {112--117},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ARITH.2016.32},
doi = {10.1109/ARITH.2016.32},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/GueronM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/SatpathyMSACKAH16,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Mark A. Anders and
Gregory K. Chen and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De},
title = {A 305mV-850mV 400{\(\mu\)}W 45GSamples/J reconfigurable compressive
sensing engine with early-termination for ultra-low energy target
detection in 14nm tri-gate {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {253--256},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844183},
doi = {10.1109/ASSCC.2016.7844183},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/SatpathyMSACKAH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SatpathyMSK16,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Ram Krishnamurthy},
title = {Ultra-low energy security circuits for IoT applications},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {682--685},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753358},
doi = {10.1109/ICCD.2016.7753358},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SatpathyMSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KarSMRDM16,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Exploiting Fully Integrated Inductive Voltage Regulators to Improve
Side Channel Resistance of Encryption Engines},
booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics
and Design, {ISLPED} 2016, San Francisco Airport, CA, USA, August
08 - 10, 2016},
pages = {130--135},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2934583.2934607},
doi = {10.1145/2934583.2934607},
timestamp = {Tue, 06 Nov 2018 16:59:21 +0100},
biburl = {https://dblp.org/rec/conf/islped/KarSMRDM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KaulAMCSHAK16,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu K. Mathew and
Gregory K. Chen and
Sudhir Satpathy and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy},
title = {14.4 {A} 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor
accelerator with adaptive precision in 14nm tri-gate {CMOS}},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {260--261},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7418006},
doi = {10.1109/ISSCC.2016.7418006},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KaulAMCSHAK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AgarwalHAMCKSK16,
author = {Amit Agarwal and
Steven Hsu and
Mark A. Anders and
Sanu Mathew and
Gregory K. Chen and
Himanshu Kaul and
Sudhir Satpathy and
Ram Krishnamurthy},
title = {A 350mV-900mV 2.1GHz 0.011mm\({}^{\mbox{2}}\) regular expression matching
accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate
{CMOS}},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573514},
doi = {10.1109/VLSIC.2016.7573514},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/AgarwalHAMCKSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MathewSSAKAHCKD16,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy and
Vivek De},
title = {A 4fJ/bit delay-hardened physically unclonable function circuit with
selective bit destabilization in 14nm tri-gate {CMOS}},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573554},
doi = {10.1109/VLSIC.2016.7573554},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MathewSSAKAHCKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathyMSAKAHC16,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy},
title = {250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field
{SMS4} encrypt/decrypt accelerator in 14nm tri-gate {CMOS}},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573552},
doi = {10.1109/VLSIC.2016.7573552},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathyMSAKAHC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenAKSMHAKDB15,
author = {Gregory K. Chen and
Mark A. Anders and
Himanshu Kaul and
Sudhir Satpathy and
Sanu K. Mathew and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy and
Vivek De and
Shekhar Borkar},
title = {A 340 mV-to-0.9 {V} 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched
16 {\texttimes} 16 Network-on-Chip in 22 nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {59--67},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2369508},
doi = {10.1109/JSSC.2014.2369508},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChenAKSMHAKDB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewSSAKAHCK15,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy},
title = {340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With
Area-Optimized Encrypt/Decrypt {GF(2} 4 {)} 2 Polynomials in 22 nm
Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {4},
pages = {1048--1058},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2384039},
doi = {10.1109/JSSC.2014.2384039},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MathewSSAKAHCK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/MathewJNSSAKCAH15,
author = {Sanu Mathew and
David Johnston and
Paul Newman and
Sudhir Satpathy and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Gregory K. Chen and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
editor = {Wolfgang Pribyl and
Franz Dielacher and
Gernot Hueber},
title = {{\(\mu\)}RNG: {A} 300-950mV 323Gbps/W all-digital full-entropy true
random number generator in 14nm FinFET {CMOS}},
booktitle = {{ESSCIRC} Conference 2015 - 41\({}^{\mbox{st}}\) European Solid-State
Circuits Conference, Graz, Austria, September 14-18, 2015},
pages = {116--119},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ESSCIRC.2015.7313842},
doi = {10.1109/ESSCIRC.2015.7313842},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/MathewJNSSAKCAH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SatpathyM0KAKCAHK14,
author = {Sudhir Satpathy and
Sanu Mathew and
Jiangtao Li and
Patrick Koeberl and
Mark A. Anders and
Himanshu Kaul and
Gregory K. Chen and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {13fJ/bit probing-resilient 250K {PUF} array with soft darkbit masking
for 1.94{\%} bit-error in 22nm tri-gate {CMOS}},
booktitle = {{ESSCIRC} 2014 - 40th European Solid State Circuits Conference, Venice
Lido, Italy, September 22-26, 2014},
pages = {239--242},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ESSCIRC.2014.6942066},
doi = {10.1109/ESSCIRC.2014.6942066},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/SatpathyM0KAKCAHK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChenAKSMHAKBD14,
author = {Gregory K. Chen and
Mark A. Anders and
Himanshu Kaul and
Sudhir Satpathy and
Sanu K. Mathew and
Steven K. Hsu and
Amit Agarwal and
Ram K. Krishnamurthy and
Shekhar Borkar and
Vivek De},
title = {16.1 {A} 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched
16{\texttimes}16 network-on-chip in 22nm tri-gate {CMOS}},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {276--277},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757432},
doi = {10.1109/ISSCC.2014.6757432},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChenAKSMHAKBD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MathewSAKHACPKD14,
author = {Sanu K. Mathew and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Steven K. Hsu and
Amit Agarwal and
Gregory K. Chen and
R. J. Parker and
Ram K. Krishnamurthy and
Vivek De},
title = {16.2 {A} 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable
function circuit for 100{\%} stable secure key generation in 22nm
{CMOS}},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {278--279},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757433},
doi = {10.1109/ISSCC.2014.6757433},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/MathewSAKHACPKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MathewSSKACAHK14,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Himanshu Kaul and
Mark A. Anders and
Gregory K. Chen and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with
area-optimized encrypt/decrypt GF(2\({}^{\mbox{4}}\))\({}^{\mbox{2}}\)
polynomials in 22nm tri-gate {CMOS}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
Honolulu, HI, USA, June 10-13, 2014},
pages = {1--2},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSIC.2014.6858420},
doi = {10.1109/VLSIC.2014.6858420},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MathewSSKACAHK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuAAMKSK13,
author = {Steven Hsu and
Amit Agarwal and
Mark A. Anders and
Sanu Mathew and
Himanshu Kaul and
Farhana Sheikh and
Ram K. Krishnamurthy},
title = {A 280 mV-to-1.1 {V} 256b Reconfigurable {SIMD} Vector Permutation
Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {1},
pages = {118--127},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2222811},
doi = {10.1109/JSSC.2012.2222811},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HsuAAMKSK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SheikhMAKHAKB13,
author = {Farhana Sheikh and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Steven Hsu and
Amit Agarwal and
Ram K. Krishnamurthy and
Shekhar Borkar},
title = {A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex
and Pixel Shading in 32 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {1},
pages = {128--139},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2222813},
doi = {10.1109/JSSC.2012.2222813},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SheikhMAKHAKB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acssc/CarterNKHBJMMSM13,
author = {Andrew Carter and
Paula Ning and
William Koven and
David Money Harris and
Michael Braly and
Nathan Jones and
Julien Massas and
Trevin Murakami and
Alexandra Simoni and
Sanu Mathew},
editor = {Michael B. Matthews},
title = {Comparison of parallelized radix-2 and radix-4 scalable Montgomery
multipliers},
booktitle = {2013 Asilomar Conference on Signals, Systems and Computers, Pacific
Grove, CA, USA, November 3-6, 2013},
pages = {1144--1148},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ACSSC.2013.6810473},
doi = {10.1109/ACSSC.2013.6810473},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/acssc/CarterNKHBJMMSM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/SrinivasanBRBJMKE13,
author = {Suresh Srinivasan and
Ketan Bhudiya and
Rajaraman Ramanarayanan and
P. Sahit Babu and
Tiju Jacob and
Sanu Mathew and
Ram Krishnamurthy and
Vasantha Erraguntla},
editor = {Alberto Nannarelli and
Peter{-}Michael Seidel and
Ping Tak Peter Tang},
title = {Split-Path Fused Floating Point Multiply Accumulate {(FPMAC)}},
booktitle = {21st {IEEE} Symposium on Computer Arithmetic, {ARITH} 2013, Austin,
TX, USA, April 7-10, 2013},
pages = {17--24},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ARITH.2013.32},
doi = {10.1109/ARITH.2013.32},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/SrinivasanBRBJMKE13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewSAKHSASK12,
author = {Sanu Mathew and
Suresh Srinivasan and
Mark A. Anders and
Himanshu Kaul and
Steven Hsu and
Farhana Sheikh and
Amit Agarwal and
Sudhir Satpathy and
Ram Krishnamurthy},
title = {2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number
Generator for 45 nm {CMOS} High-Performance Microprocessors},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {11},
pages = {2807--2821},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2217631},
doi = {10.1109/JSSC.2012.2217631},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/MathewSAKHSASK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AgarwalHMAKSK12,
author = {Amit Agarwal and
Steven Hsu and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Farhana Sheikh and
Ram Krishnamurthy},
title = {A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted
skip in 22nm tri-gate {CMOS}},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
2012, Bordeaux, France, September 17-21, 2012},
pages = {177--180},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ESSCIRC.2012.6341287},
doi = {10.1109/ESSCIRC.2012.6341287},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/AgarwalHMAKSK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HsuAAMKSK12,
author = {Steven Hsu and
Amit Agarwal and
Mark A. Anders and
Sanu Mathew and
Himanshu Kaul and
Farhana Sheikh and
Ram Krishnamurthy},
title = {A 280mV-to-1.1V 256b reconfigurable {SIMD} vector permutation engine
with 2-dimensional shuffle in 22nm {CMOS}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {178--180},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176966},
doi = {10.1109/ISSCC.2012.6176966},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HsuAAMKSK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KaulAMHASKB12,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu Mathew and
Steven Hsu and
Amit Agarwal and
Farhana Sheikh and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused
multiply-add unit with certainty tracking in 32nm {CMOS}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {182--184},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176987},
doi = {10.1109/ISSCC.2012.6176987},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KaulAMHASKB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SheikhMAKHAKB12,
author = {Farhana Sheikh and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex
and pixel shading in 32nm {CMOS}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {184--186},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176967},
doi = {10.1109/ISSCC.2012.6176967},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SheikhMAKHAKB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HsuAAKMSKB12,
author = {Steven Hsu and
Amit Agarwal and
Mark A. Anders and
Himanshu Kaul and
Sanu Mathew and
Farhana Sheikh and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 2.8GHz 128-entry {\texttimes} 152b 3-read/2-write multi-precision
floating-point register file and shuffler in 32nm {CMOS}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {118--119},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243818},
doi = {10.1109/VLSIC.2012.6243818},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/HsuAAKMSKB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewSKGAHKAK11,
author = {Sanu Mathew and
Farhana Sheikh and
Michael E. Kounavis and
Shay Gueron and
Amit Agarwal and
Steven Hsu and
Himanshu Kaul and
Mark A. Anders and
Ram Krishnamurthy},
title = {53 Gbps Native {GF(2} \({}^{\mbox{4}}\)) \({}^{\mbox{2}}\) Composite-Field
AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance
Microprocessors},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {4},
pages = {767--776},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2108131},
doi = {10.1109/JSSC.2011.2108131},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/MathewSKGAHKAK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KrishnamurthyMS11,
author = {Ram Krishnamurthy and
Sanu Mathew and
Farhana Sheikh},
editor = {Leon Stok and
Nikil D. Dutt and
Soha Hassoun},
title = {High-performance energy-efficient encryption in the sub-45nm {CMOS}
Era},
booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011,
San Diego, California, USA, June 5-10, 2011},
pages = {332},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2024724.2024804},
doi = {10.1145/2024724.2024804},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KrishnamurthyMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AgarwalHMAKSK11,
author = {Amit Agarwal and
Steven Hsu and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Farhana Sheikh and
Ram Krishnamurthy},
title = {A 128{\texttimes}128b high-speed wide-and match-line content addressable
memory in 32nm {CMOS}},
booktitle = {Proceedings of the 37th European Solid-State Circuits Conference,
{ESSCIRC} 2011, Helsinki, Finland, Sept. 12-16, 2011},
pages = {83--86},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ESSCIRC.2011.6044920},
doi = {10.1109/ESSCIRC.2011.6044920},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/AgarwalHMAKSK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KaulAMHAKB10,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu Mathew and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way {SIMD} Vector
Processing Accelerator in 45 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {1},
pages = {95--102},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2009.2031813},
doi = {10.1109/JSSC.2009.2031813},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KaulAMHAKB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/MathewKSHAKABK10,
author = {Sanu Mathew and
Michael E. Kounavis and
Farhana Sheikh and
Steven Hsu and
Amit Agarwal and
Himanshu Kaul and
Mark A. Anders and
Frank L. Berry and
Ram Krishnamurthy},
title = {3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key
encryption acceleration in 45nm {CMOS}},
booktitle = {36th European Solid-State Circuits Conference, {ESSCIRC} 2010, Sevilla,
Spain, September 13-17, 2010},
pages = {198--201},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ESSCIRC.2010.5619895},
doi = {10.1109/ESSCIRC.2010.5619895},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/MathewKSHAKABK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/RamanarayananMS10,
author = {Rajaraman Ramanarayanan and
Sanu Mathew and
Farhana Sheikh and
Suresh Srinivasan and
Amit Agarwal and
Steven Hsu and
Himanshu Kaul and
Mark A. Anders and
Vasantha Erraguntla and
Ram Krishnamurthy},
title = {18Gbps, 50mW reconfigurable multi-mode {SHA} Hashing accelerator in
45nm {CMOS}},
booktitle = {36th European Solid-State Circuits Conference, {ESSCIRC} 2010, Sevilla,
Spain, September 13-17, 2010},
pages = {210--213},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ESSCIRC.2010.5619892},
doi = {10.1109/ESSCIRC.2010.5619892},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/RamanarayananMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AndersKHAMSKB10,
author = {Mark A. Anders and
Himanshu Kaul and
Steven Hsu and
Amit Agarwal and
Sanu Mathew and
Farhana Sheikh and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched
8{\texttimes}8 mesh network-on-chip in 45nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {110--111},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5434078},
doi = {10.1109/ISSCC.2010.5434078},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/AndersKHAMSKB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AgarwalMHAKSRSKB10,
author = {Amit Agarwal and
Sanu Mathew and
Steven Hsu and
Mark A. Anders and
Himanshu Kaul and
Farhana Sheikh and
Rajaraman Ramanarayanan and
Suresh Srinivasan and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media
accelerators in 32nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {328--329},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433903},
doi = {10.1109/ISSCC.2010.5433903},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/AgarwalMHAKSRSKB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KaulAMHAKB09,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu K. Mathew and
Steven Hsu and
Amit Agarwal and
Ram K. Krishnamurthy and
Shekhar Borkar},
title = {A 320 mV 56 {\(\mu\)}W 411 GOPS/Watt Ultra-Low Voltage Motion Estimation
Accelerator in 65 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {107--114},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2007164},
doi = {10.1109/JSSC.2008.2007164},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KaulAMHAKB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KaulAMHAKB09,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu Mathew and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 300mV 494GOPS/W reconfigurable dual-supply 4-Way {SIMD} vector processing
accelerator in 45nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {260--261},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977407},
doi = {10.1109/ISSCC.2009.4977407},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KaulAMHAKB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SrinivasanMEK09,
author = {Suresh Srinivasan and
Sanu Mathew and
Vasantha Erraguntla and
Ram Krishnamurthy},
title = {A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant
All-Digital True Random Number Generator in 45nm {CMOS}},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {301--306},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.69},
doi = {10.1109/VLSI.DESIGN.2009.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SrinivasanMEK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AndersMHKB08,
author = {Mark A. Anders and
Sanu K. Mathew and
Steven Hsu and
Ram K. Krishnamurthy and
Shekhar Borkar},
title = {A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator
in 90 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {1},
pages = {214--222},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2007.909336},
doi = {10.1109/JSSC.2007.909336},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/AndersMHKB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KaulAMHAKB08,
author = {Himanshu Kaul and
Mark A. Anders and
Sanu Mathew and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 320mV 56{\(\mu\)}W 411GOPS/Watt Ultra-Low Voltage Motion Estimation
Accelerator in 65nm {CMOS}},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {316--317},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523184},
doi = {10.1109/ISSCC.2008.4523184},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KaulAMHAKB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/RamanarayananMEKG08,
author = {Rajaraman Ramanarayanan and
Sanu Mathew and
Vasantha Erraguntla and
Ram Krishnamurthy and
Shay Gueron},
title = {A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm
High-Performance Microprocessor Execution Cores},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {273--278},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.75},
doi = {10.1109/VLSI.2008.75},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/RamanarayananMEKG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WijeratneSMAKAE07,
author = {Sapumal B. Wijeratne and
Nanda Siddaiah and
Sanu K. Mathew and
Mark A. Anders and
Ram K. Krishnamurthy and
Jeremy Anderson and
Matthew Ernest and
Mark D. Nardin},
title = {A 9-GHz 65-nm Intel{\textregistered} Pentium 4 Processor Integer Execution
Unit},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {1},
pages = {26--37},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2006.885055},
doi = {10.1109/JSSC.2006.885055},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WijeratneSMAKAE07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AndersMHKB07,
author = {Mark A. Anders and
Sanu Mathew and
Steven Hsu and
Ram Krishnamurthy and
Shekhar Borkar},
title = {A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator
in 90nm {CMOS}},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {256--600},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373391},
doi = {10.1109/ISSCC.2007.373391},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/AndersMHKB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/MathewHAHK07,
author = {Sanu Mathew and
David Money Harris and
Mark A. Anders and
Steven Hsu and
Ram Krishnamurthy},
title = {A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery
multiplier in 90nm {CMOS}},
booktitle = {2007 {IEEE} International {SOC} Conference, Tampere, Finland, November
19-21, 2007},
pages = {25--28},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/SOCC.2007.4545418},
doi = {10.1109/SOCC.2007.4545418},
timestamp = {Fri, 04 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/socc/MathewHAHK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuMAZOKB06,
author = {Steven K. Hsu and
Sanu K. Mathew and
Mark A. Anders and
Bart R. Zeydel and
Vojin G. Oklobdzija and
Ram K. Krishnamurthy and
Shekhar Y. Borkar},
title = {A 110 {GOPS/W} 16-bit multiplier and reconfigurable {PLA} loop in
90-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {1},
pages = {256--264},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2005.859893},
doi = {10.1109/JSSC.2005.859893},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HsuMAZOKB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WijeratneSMAKAH06,
author = {Sapumal B. Wijeratne and
Nanda Siddaiah and
Sanu Mathew and
Mark A. Anders and
Ram Krishnamurthy and
Jeremy Anderson and
Seung Hwang and
Matthew Ernest and
Mark D. Nardin},
title = {A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {353--365},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696066},
doi = {10.1109/ISSCC.2006.1696066},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/WijeratneSMAKAH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HsuAAMKB06,
author = {Steven K. Hsu and
Amit Agarwal and
Mark A. Anders and
Sanu Mathew and
Ram Krishnamurthy and
Shekhar Borkar},
title = {An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm
{CMOS}},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {1785--1797},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696235},
doi = {10.1109/ISSCC.2006.1696235},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HsuAAMKB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewABNKB05,
author = {Sanu K. Mathew and
Mark A. Anders and
Brad Bloechel and
Trang Nguyen and
Ram K. Krishnamurthy and
Shekhar Borkar},
title = {A 4-GHz 300-mW 64-bit integer execution {ALU} with dual supply voltages
in 90-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {40},
number = {1},
pages = {44--51},
year = {2005},
url = {https://doi.org/10.1109/JSSC.2004.838019},
doi = {10.1109/JSSC.2004.838019},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/MathewABNKB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OklobdzijaZDMK05,
author = {Vojin G. Oklobdzija and
Bart R. Zeydel and
Hoang Q. Dao and
Sanu Mathew and
Ram Krishnamurthy},
title = {Comparison of high-performance {VLSI} adders in the energy-delay space},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {754--758},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848819},
doi = {10.1109/TVLSI.2005.848819},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OklobdzijaZDMK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/HarrisKAMH05,
author = {David Money Harris and
Ram Krishnamurthy and
Mark A. Anders and
Sanu Mathew and
Steven Hsu},
title = {An Improved Unified Scalable Radix-2 Montgomery Multiplier},
booktitle = {17th {IEEE} Symposium on Computer Arithmetic {(ARITH-17} 2005), 27-29
June 2005, Cape Cod, MA, {USA}},
pages = {172--178},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ARITH.2005.9},
doi = {10.1109/ARITH.2005.9},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/HarrisKAMH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/HsuVMKADBK05,
author = {Steven Hsu and
Vishak Venkatraman and
Sanu Mathew and
Himanshu Kaul and
Mark A. Anders and
Saurabh Dighe and
Wayne P. Burleson and
Ram Krishnamurthy},
editor = {Laurent Fesquet and
Andreas Kaiser and
Sorin Cristoloveanu and
Michel Brillou{\"{e}}t},
title = {A 2GHz 13.6mW 12 {\texttimes} 9b multiplier for energy efficient {FFT}
accelerators},
booktitle = {Proceedings of the 31st European Solid-State Circuits Conference,
{ESSCIRC} 2005, Grenoble, France, 12-16 September 2005},
pages = {199--202},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ESSCIR.2005.1541594},
doi = {10.1109/ESSCIR.2005.1541594},
timestamp = {Fri, 28 Apr 2023 15:39:25 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/HsuVMKADBK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewAKB03,
author = {Sanu Mathew and
Mark A. Anders and
Ram K. Krishnamurthy and
Shekhar Borkar},
title = {A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder
core},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {5},
pages = {689--695},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.810056},
doi = {10.1109/JSSC.2003.810056},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MathewAKB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuAMLKB03,
author = {Steven Hsu and
Atila Alvandpour and
Sanu Mathew and
Shih{-}Lien Lu and
Ram K. Krishnamurthy and
Shekhar Borkar},
title = {A 4.5-GHz 130-nm 32-KB {L0} cache with a leakage-tolerant self reverse-bias
bitline scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {5},
pages = {755--761},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.810058},
doi = {10.1109/JSSC.2003.810058},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HsuAMLKB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/OklobdzijaZDMK03,
author = {Vojin G. Oklobdzija and
Bart R. Zeydel and
Hoang Q. Dao and
Sanu Mathew and
Ram Krishnamurthy},
title = {Energy-Delay Estimation Technique for High-Performance Microprocessor
{VLSI} Adders},
booktitle = {16th {IEEE} Symposium on Computer Arithmetic (Arith-16 2003), 15-18
June 2003, Santiago de Compostela, Spain},
pages = {272--279},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ARITH.2003.1207688},
doi = {10.1109/ARITH.2003.1207688},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/OklobdzijaZDMK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/VangalABSGEWPVT02,
author = {Sriram R. Vangal and
Mark A. Anders and
Nitin Borkar and
Erik Seligman and
Venkatesh Govindarajulu and
Vasantha Erraguntla and
Howard Wilson and
Amaresh Pangal and
Venkat Veeramachaneni and
James W. Tschanz and
Yibin Ye and
Dinesh Somasekhar and
Bradley A. Bloechel and
Gregory E. Dermer and
Ram K. Krishnamurthy and
Krishnamurthy Soumyanath and
Sanu Mathew and
Siva G. Narendra and
Mircea R. Stan and
Scott Thompson and
Vivek De and
Shekhar Borkar},
title = {5-GHz 32-bit integer execution core in 130-nm dual-V\({}_{\mbox{T}}\)
{CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {37},
number = {11},
pages = {1421--1432},
year = {2002},
url = {https://doi.org/10.1109/JSSC.2002.803944},
doi = {10.1109/JSSC.2002.803944},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/VangalABSGEWPVT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MathewKARMS01,
author = {Sanu K. Mathew and
Ram K. Krishnamurthy and
Mark A. Anders and
Rafael Rios and
Kaizad R. Mistry and
Krishnamurthy Soumyanath},
title = {Sub-500-ps 64-b ALUs in 0.18-{\(\mu\)}m SOI/bulk {CMOS:} design and
scaling trends},
journal = {{IEEE} J. Solid State Circuits},
volume = {36},
number = {11},
pages = {1636--1646},
year = {2001},
url = {https://doi.org/10.1109/4.962283},
doi = {10.1109/4.962283},
timestamp = {Wed, 06 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MathewKARMS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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