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ORCIDBibTeX records: Chien-Nan Jimmy Liu
@article{DBLP:journals/todaes/SongCKLH23,
author = {Ling{-}Yen Song and
Chih{-}Yun Chou and
Tung{-}Chieh Kuo and
Chien{-}Nan Liu and
Juinn{-}Dar Huang},
title = {Machine Learning Assisted Circuit Sizing Approach for Low-Voltage
Analog Circuits with Efficient Variation-Aware Optimization},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {2},
pages = {18:1--18:22},
year = {2023},
url = {https://doi.org/10.1145/3567422},
doi = {10.1145/3567422},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/SongCKLH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChiangHLCJWCLC23,
author = {Cheng{-}Yu Chiang and
Chia{-}Lin Hu and
Mark Po{-}Hung Lin and
Yu{-}Szu Chung and
Shyh{-}Jye Jou and
Jieh{-}Tsorng Wu and
Shiuh{-}Hua Wood Chiang and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
editor = {Atsushi Takahashi},
title = {On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching
for Custom {SAR} {ADC}},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {352--357},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567878},
doi = {10.1145/3566097.3567878},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChiangHLCJWCLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ChenHWLHCL23,
author = {Hung{-}Ming Chen and
Chu{-}Wen Ho and
Shih{-}Hsien Wu and
Wei Lu and
Po{-}Tsang Huang and
Hao{-}Ju Chang and
Chien{-}Nan Jimmy Liu},
editor = {David G. Chinnery and
Iris Hui{-}Ru Jiang},
title = {Reshaping System Design in 3D Integration: Perspectives and Challenges},
booktitle = {Proceedings of the 2023 International Symposium on Physical Design,
{ISPD} 2023, Virtual Event, USA, March 26-29, 2023},
pages = {71--77},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3569052.3578918},
doi = {10.1145/3569052.3578918},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/ChenHWLHCL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/WangLLC23,
author = {Po{-}Chun Wang and
Mark Po{-}Hung Lin and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
title = {Layout Synthesis of Analog Primitive Cells with Variational Autoencoder},
booktitle = {19th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2023,
Funchal, Portugal, July 3-5, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SMACD58065.2023.10192172},
doi = {10.1109/SMACD58065.2023.10192172},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/smacd/WangLLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SongKWLH22,
author = {Ling{-}Yen Song and
Tung{-}Chieh Kuo and
Ming{-}Hung Wang and
Chien{-}Nan Jimmy Liu and
Juinn{-}Dar Huang},
title = {Fast Variation-aware Circuit Sizing Approach for Analog Design with
ML-Assisted Evolutionary Algorithm},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {80--85},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712559},
doi = {10.1109/ASP-DAC52403.2022.9712559},
timestamp = {Fri, 04 Mar 2022 13:11:07 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SongKWLH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LaiCKWHCLJ22,
author = {Bo{-}Cheng Lai and
Tzu{-}Chieh Chiang and
Po{-}Shen Kuo and
Wan{-}Ching Wang and
Yan{-}Lin Hung and
Hung{-}Ming Chen and
Chien{-}Nan Liu and
Shyh{-}Jye Jou},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {{DASC:} {A} {DRAM} Data Mapping Methodology for Sparse Convolutional
Neural Networks},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {208--213},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774608},
doi = {10.23919/DATE54114.2022.9774608},
timestamp = {Wed, 25 May 2022 22:56:19 +0200},
biburl = {https://dblp.org/rec/conf/date/LaiCKWHCLJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChiCCLKCH22,
author = {Hao{-}Yu Chi and
Simon Yi{-}Hung Chen and
Hung{-}Ming Chen and
Chien{-}Nan Liu and
Yun{-}Chih Kuo and
Ya{-}Hsin Chang and
Kuan{-}Hsien Ho},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {Practical Substrate Design Considering Symmetrical and Shielding Routes},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {951--956},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774733},
doi = {10.23919/DATE54114.2022.9774733},
timestamp = {Wed, 25 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ChiCCLKCH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/ChangLK22,
author = {Shih{-}Han Chang and
Chien{-}Nan Jimmy Liu and
Alexandra K{\"{u}}ster},
title = {Behavioral Level Simulation Framework to Support Error-Aware {CNN}
Training with In-Memory Computing},
booktitle = {18th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2022,
Villasimius, Italy, June 12-15, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/SMACD55068.2022.9816307},
doi = {10.1109/SMACD55068.2022.9816307},
timestamp = {Fri, 22 Jul 2022 13:09:21 +0200},
biburl = {https://dblp.org/rec/conf/smacd/ChangLK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/ChiangHCLJCLC22,
author = {Cheng{-}Yu Chiang and
Chia{-}Lin Hu and
Kang{-}Yu Chang and
Mark Po{-}Hung Lin and
Shyh{-}Jye Jou and
Hung{-}Yu Chen and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
title = {On Optimizing Capacitor Array Design for Advanced Node {SAR} {ADC}},
booktitle = {18th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2022,
Villasimius, Italy, June 12-15, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/SMACD55068.2022.9816200},
doi = {10.1109/SMACD55068.2022.9816200},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/smacd/ChiangHCLJCLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/FanCLH22,
author = {Kang{-}Yi Fan and
Jyun{-}Hua Chen and
Chien{-}Nan Liu and
Juinn{-}Dar Huang},
title = {Performance Optimization for {MLP} Accelerators using ILP-Based On-Chip
Weight Allocation Strategy},
booktitle = {2022 International Symposium on {VLSI} Design, Automation and Test,
{VLSI-DAT} 2022, Hsinchu, Taiwan, April 18-21, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-DAT54769.2022.9768095},
doi = {10.1109/VLSI-DAT54769.2022.9768095},
timestamp = {Mon, 23 May 2022 16:36:24 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/FanCLH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChiLHLC21,
author = {Hao{-}Yu Chi and
Zi{-}Jun Lin and
Chia{-}Hao Hung and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
title = {A Style-Based Analog Layout Migration Technique With Complete Routing
Behavior Preservation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {12},
pages = {2556--2567},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3046561},
doi = {10.1109/TCAD.2020.3046561},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChiLHLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChiCYLJ21,
author = {Hao{-}Yu Chi and
Han{-}Chung Chang and
Chih{-}Hsin Yang and
Chien{-}Nan Liu and
Jing{-}Yang Jou},
title = {Performance-driven Routing Methodology with Incremental Placement
Refinement for Analog Layout Design},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1218--1223},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474213},
doi = {10.23919/DATE51398.2021.9474213},
timestamp = {Wed, 21 Jul 2021 10:04:34 +0200},
biburl = {https://dblp.org/rec/conf/date/ChiCYLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChenNCCCCLLJ21,
author = {Hung{-}Ming Chen and
Cheng{-}En Ni and
Kang{-}Yu Chang and
Tzu{-}Chieh Chiang and
Shih{-}Han Chang and
Cheng{-}Yu Chiang and
Bo{-}Cheng Lai and
Chien{-}Nan Liu and
Shyh{-}Jye Jou},
title = {On Reconfiguring Memory-Centric {AI} Edge Devices for {CIM}},
booktitle = {18th International SoC Design Conference, {ISOCC} 2021, Jeju Island,
South Korea, Republic of, October 6-9, 2021},
pages = {262--263},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISOCC53507.2021.9613893},
doi = {10.1109/ISOCC53507.2021.9613893},
timestamp = {Mon, 06 Dec 2021 17:33:24 +0100},
biburl = {https://dblp.org/rec/conf/isocc/ChenNCCCCLLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/SongYLH21,
author = {Ling{-}Yen Song and
Chih{-}Shen Yeh and
Chien{-}Nan Liu and
Juinn{-}Dar Huang},
title = {Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization
on Digital Microfluidic Biochips},
booktitle = {International Symposium on {VLSI} Design, Automation and Test, {VLSI-DAT}
2021, Hsinchu, Taiwan, April 19-22, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-DAT52063.2021.9427345},
doi = {10.1109/VLSI-DAT52063.2021.9427345},
timestamp = {Mon, 17 May 2021 15:11:23 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/SongYLH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChiLC20,
author = {Hao{-}Yu Chi and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
title = {Wire Load Oriented Analog Routing with Matching Constraints},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {25},
number = {6},
pages = {55:1--55:26},
year = {2020},
url = {https://doi.org/10.1145/3403932},
doi = {10.1145/3403932},
timestamp = {Thu, 05 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChiLC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LinCPLZLC20,
author = {Mark Po{-}Hung Lin and
Hao{-}Yu Chi and
Abhishek Patyal and
Zheng{-}Yao Liu and
Jun{-}Jie Zhao and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
title = {Achieving Analog Layout Integrity through Learning and Migration Invited
Talk},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {55:1--55:8},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415752},
doi = {10.1145/3400302.3415752},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LinCPLZLC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenHCKLKCLLJ20,
author = {Hung{-}Ming Chen and
Chia{-}Lin Hu and
Kang{-}Yu Chang and
Alexandra K{\"{u}}ster and
Yu{-}Hsien Lin and
Po{-}Shen Kuo and
Wei{-}Tung Chao and
Bo{-}Cheng Lai and
Chien{-}Nan Liu and
Shyh{-}Jye Jou},
title = {On {EDA} Solutions for Reconfigurable Memory-Centric {AI} Edge Applications},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {127:1--127:8},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415772},
doi = {10.1145/3400302.3415772},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChenHCKLKCLLJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChiLHLC19,
author = {Hao{-}Yu Chi and
Zi{-}Jun Lin and
Chia{-}Hao Hung and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
editor = {David Z. Pan},
title = {Achieving Routing Integrity in Analog Layout Migration via Cartesian
Detection Lines},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942088},
doi = {10.1109/ICCAD45719.2019.8942088},
timestamp = {Wed, 19 Feb 2020 16:38:01 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChiLHLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/ChenCSLC19,
author = {Yu{-}Hsien Chen and
Hao{-}Yu Chi and
Ling{-}Yen Song and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
title = {A Structure-Based Methodology for Analog Layout Generation},
booktitle = {16th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2019,
Lausanne, Switzerland, July 15-18, 2019},
pages = {33--36},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SMACD.2019.8795227},
doi = {10.1109/SMACD.2019.8795227},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/smacd/ChenCSLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChiTLC18,
author = {Hao{-}Yu Chi and
Hwa{-}Yi Tseng and
Chien{-}Nan Jimmy Liu and
Hung{-}Ming Chen},
editor = {Youngsoo Shin},
title = {Performance-preserved analog routing methodology via wire load reduction},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {482--487},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297370},
doi = {10.1109/ASPDAC.2018.8297370},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChiTLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PatyalPACCL18,
author = {Abhishek Patyal and
Po{-}Cheng Pan and
K. A. Asha and
Hung{-}Ming Chen and
Hao{-}Yu Chi and
Chien{-}Nan Liu},
title = {Analog placement with current flow and symmetry constraints using
{PCP-SP}},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {10:1--10:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3195990},
doi = {10.1145/3195970.3195990},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/dac/PatyalPACCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/HsuCYL18,
author = {Hsin{-}Ju Hsu and
Wan{-}Chun Chen and
Long{-}Ching Yeh and
Chien{-}Nan Jimmy Liu},
title = {Spec-to-Layout Automation Flow for Buck Converters with Current-Mode
Control in {SOC} Applications},
booktitle = {15th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2018,
Prague, Czech Republic, July 2-5, 2018},
pages = {169--172},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SMACD.2018.8434911},
doi = {10.1109/SMACD.2018.8434911},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/smacd/HsuCYL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/QuiHL17,
author = {Nguyen Cao Qui and
Si{-}Rong He and
Chien{-}Nan Jimmy Liu},
title = {An Incremental Simulation Technique Based on Delta Model for Lifetime
Yield Analysis},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {100-A},
number = {11},
pages = {2370--2378},
year = {2017},
url = {https://doi.org/10.1587/transfun.E100.A.2370},
doi = {10.1587/TRANSFUN.E100.A.2370},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/QuiHL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/QuiHL17,
author = {Nguyen Cao Qui and
Si{-}Rong He and
Chien{-}Nan Jimmy Liu},
title = {Cluster-based delta-QMC technique for fast yield analysis},
journal = {Integr.},
volume = {58},
pages = {64--73},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.011},
doi = {10.1016/J.VLSI.2017.02.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/QuiHL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/HeQKL17,
author = {Si{-}Rong He and
Nguyen Cao Qui and
Yu{-}Hsuan Kuo and
Chien{-}Nan Jimmy Liu},
title = {An Incremental Aging Analysis Method Based on Delta Circuit Simulation
Technique},
booktitle = {26th {IEEE} Asian Test Symposium, {ATS} 2017, Taipei City, Taiwan,
November 27-30, 2017},
pages = {64--69},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ATS.2017.24},
doi = {10.1109/ATS.2017.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/HeQKL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SongWLLLLK17,
author = {Ling{-}Yen Song and
Chun Wang and
Chien{-}Nan Jimmy Liu and
Yun{-}Jing Lin and
Meng{-}Jung Lee and
Yu{-}Lan Lo and
Shu{-}Yi Kao},
title = {Non-regression approach for the behavioral model generator in mixed-signal
system verification},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203462},
doi = {10.1109/VLSI-SOC.2017.8203462},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SongWLLLLK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/LeeTKLH17,
author = {Chih{-}Wei Lee and
Hwa{-}Yi Tseng and
Chi{-}Lien Kuo and
Chien{-}Nan Jimmy Liu and
Chin Hsia},
title = {Layout placement optimization with isolation rings for high-voltage
{VLSI} circuits},
booktitle = {2017 International Symposium on {VLSI} Design, Automation and Test,
{VLSI-DAT} 2017, Hsinchu, Taiwan, April 24-27, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-DAT.2017.7939658},
doi = {10.1109/VLSI-DAT.2017.7939658},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/LeeTKLH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/TuYHLCCTSLCF17,
author = {Yo{-}Hao Tu and
Kai{-}Wen Yao and
Minghao Huang and
Yu{-}Yun Lin and
Hao{-}Yu Chi and
Po{-}Min Cheng and
Pei{-}Yun Tsai and
Muh{-}Tian Shiue and
Chien{-}Nan Liu and
Kuo{-}Hsing Cheng and
Jia{-}Shiang Fu},
title = {A body sensor node SoC for {ECG/EMG} applications with compressed
sensing and wireless powering},
booktitle = {2017 International Symposium on {VLSI} Design, Automation and Test,
{VLSI-DAT} 2017, Hsinchu, Taiwan, April 24-27, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-DAT.2017.7939668},
doi = {10.1109/VLSI-DAT.2017.7939668},
timestamp = {Tue, 20 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/TuYHLCCTSLCF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WuCMLJPH16,
author = {Wei Wu and
Yen{-}Lung Chen and
Yue Ma and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou and
Sudhakar Pamarti and
Lei He},
title = {Wave digital filter based analog circuit emulation on {FPGA}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {1286--1289},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7527483},
doi = {10.1109/ISCAS.2016.7527483},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WuCMLJPH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenWLH15,
author = {Yen{-}Lung Chen and
Wei Wu and
Chien{-}Nan Jimmy Liu and
Lei He},
title = {Incremental Latin hypercube sampling for lifetime stochastic behavioral
modeling of analog circuits},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {556--561},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059065},
doi = {10.1109/ASPDAC.2015.7059065},
timestamp = {Fri, 22 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChenWLH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WuGCLPWH15,
author = {Wei Wu and
Peng Gu and
Yen{-}Lung Chen and
Chien{-}Nan Liu and
Sudhakar Pamarti and
Chang Wu and
Lei He},
editor = {George A. Constantinides and
Deming Chen},
title = {Toward Wave Digital Filter based Analog Circuit Emulation on {FPGA}
(Abstract Only)},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {276},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689143},
doi = {10.1145/2684746.2689143},
timestamp = {Fri, 22 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WuGCLPWH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChangCYL15,
author = {Hsin{-}Ju Chang and
Yen{-}Lung Chen and
Conan Yeh and
Chien{-}Nan Jimmy Liu},
title = {Layout-aware analog synthesis environment with yield consideration},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {589--593},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085493},
doi = {10.1109/ISQED.2015.7085493},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChangCYL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/LienLLTL15,
author = {Ying{-}Chi Lien and
Ching{-}Mao Lee and
Chih{-}Wei Li and
Ban{-}Han Tsai and
Chien{-}Nan Jimmy Liu},
title = {Low-noise analog synthesis platform for bio-signal acquisition system},
booktitle = {{VLSI} Design, Automation and Test, {VLSI-DAT} 2015, Hsinchu, Taiwan,
April 27-29, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-DAT.2015.7114568},
doi = {10.1109/VLSI-DAT.2015.7114568},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/LienLLTL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenWLL14,
author = {Yen{-}Lung Chen and
Wan{-}Rong Wu and
Chien{-}Nan Jimmy Liu and
James Chien{-}Mo Li},
title = {Simultaneous Optimization of Analog Circuits With Reliability and
Variability for Applications on Flexible Electronics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {1},
pages = {24--35},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2282757},
doi = {10.1109/TCAD.2013.2282757},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenWLL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TsengWCL14,
author = {Hsing{-}Han Tseng and
Shiou{-}Wen Wang and
Jian{-}Yu Chen and
Chien{-}Nan Jimmy Liu},
title = {A novel design space reduction method for efficient simulation-based
optimization},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {381--384},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865145},
doi = {10.1109/ISCAS.2014.6865145},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/TsengWCL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChenCLLL14,
author = {Yen{-}Lung Chen and
Guan{-}Ming Chu and
Ying{-}Chi Lien and
Ching{-}Mao Lee and
Chien{-}Nan Jimmy Liu},
title = {Simultaneous optimization for low dropout regulator and its error
amplifier with process variation},
booktitle = {Technical Papers of 2014 International Symposium on {VLSI} Design,
Automation and Test, {VLSI-DAT} 2014, Hsinchu, Taiwan, April 28-30,
2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-DAT.2014.6834870},
doi = {10.1109/VLSI-DAT.2014.6834870},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChenCLLL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LuCLS13,
author = {Chao{-}Hung Lu and
Hung{-}Ming Chen and
Chien{-}Nan Jimmy Liu and
Wen{-}Yu Shih},
title = {Package routability- and IR-drop-aware finger/pad planning for single
chip and stacking {IC} designs},
journal = {Integr.},
volume = {46},
number = {3},
pages = {280--289},
year = {2013},
url = {https://doi.org/10.1016/j.vlsi.2012.05.001},
doi = {10.1016/J.VLSI.2012.05.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LuCLS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChenWLL13,
author = {Yen{-}Lung Chen and
Wan{-}Rong Wu and
Guan{-}Ruei Lu and
Chien{-}Nan Jimmy Liu},
editor = {Enrico Macii},
title = {Automatic circuit sizing technique for the analog circuits with flexible
TFTs considering process variation and bending effects},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1458--1461},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.297},
doi = {10.7873/DATE.2013.297},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/ChenWLL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiaoCCLC13,
author = {Yu{-}Ching Liao and
Yen{-}Lung Chen and
Xian{-}Ting Cai and
Chien{-}Nan Jimmy Liu and
Tai{-}Chen Chen},
editor = {Jos{\'{e}} Luis Ayala and
Alex K. Jones and
Patrick H. Madden and
Ayse K. Coskun},
title = {{LASER:} layout-aware analog synthesis environment on laker},
booktitle = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
France, May 2-4, 2013},
pages = {107--112},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2483028.2483071},
doi = {10.1145/2483028.2483071},
timestamp = {Tue, 23 Jul 2019 15:03:09 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/LiaoCCLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChenDLCL13,
author = {Yen{-}Lung Chen and
Yi{-}Ching Ding and
Yu{-}Ching Liao and
Hsin{-}Ju Chang and
Chien{-}Nan Jimmy Liu},
title = {A layout-aware automatic sizing approach for retargeting analog integrated
circuits},
booktitle = {2013 International Symposium on {VLSI} Design, Automation, and Test,
{VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLDI-DAT.2013.6533820},
doi = {10.1109/VLDI-DAT.2013.6533820},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChenDLCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeLL12,
author = {Mu{-}Shun Matt Lee and
Wei{-}Ting Liao and
Chien{-}Nan Jimmy Liu},
title = {Levelized High-Level Current Model of Logic Blocks for Dynamic Supply
Noise Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {845--857},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2182766},
doi = {10.1109/TCAD.2012.2182766},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiuCKT12,
author = {Chien{-}Nan Jimmy Liu and
Yen{-}Lung Chen and
Chin{-}Cheng Kuo and
I{-}Ching Tsai},
title = {A fast heuristic approach for parametric yield enhancement of analog
designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {17},
number = {3},
pages = {35:1--35:20},
year = {2012},
url = {https://doi.org/10.1145/2209291.2209308},
doi = {10.1145/2209291.2209308},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiuCKT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/ChangCJL12,
author = {Kai{-}Hui Chang and
Chia{-}Wei Chang and
Jie{-}Hong Roland Jiang and
Chien{-}Nan Jimmy Liu},
title = {Improving design verifiability by early {RTL} coverability analysis},
booktitle = {Tenth {ACM/IEEE} International Conference on Formal Methods and Models
for Codesign, {MEMCODE} 2012, Arlington, VA, USA, July 16-17, 2012},
pages = {25--32},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/MEMCOD.2012.6292297},
doi = {10.1109/MEMCOD.2012.6292297},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/memocode/ChangCJL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ChangCJL12,
author = {Kai{-}Hui Chang and
Chia{-}Wei Chang and
Jie{-}Hong Roland Jiang and
Chien{-}Nan Jimmy Liu},
title = {Reducing test point overhead with don't-cares},
booktitle = {55th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2012, Boise, ID, USA, August 5-8, 2012},
pages = {534--537},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/MWSCAS.2012.6292075},
doi = {10.1109/MWSCAS.2012.6292075},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ChangCJL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/LeeLWL12,
author = {Mu{-}Shun Matt Lee and
Yi{-}Chu Liu and
Wan{-}Rong Wu and
Chien{-}Nan Jimmy Liu},
title = {Peak wake-up current estimation at gate-level with standard library
information},
booktitle = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation
and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-DAT.2012.6212629},
doi = {10.1109/VLSI-DAT.2012.6212629},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/LeeLWL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ChuangL11,
author = {Chin{-}Lung Chuang and
Chien{-}Nan Jimmy Liu},
title = {Hybrid Testbench Acceleration for Reducing Communication Overhead},
journal = {{IEEE} Des. Test Comput.},
volume = {28},
number = {2},
pages = {40--51},
year = {2011},
url = {https://doi.org/10.1109/MDT.2011.33},
doi = {10.1109/MDT.2011.33},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/ChuangL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jise/LuCL11,
author = {Chao{-}Hung Lu and
Hung{-}Ming Chen and
Chien{-}Nan Jimmy Liu},
title = {Design Planning with 3D-Via Optimization in Alternative Stacking Integrated
Circuits},
journal = {J. Inf. Sci. Eng.},
volume = {27},
number = {1},
pages = {287--302},
year = {2011},
url = {http://www.iis.sinica.edu.tw/page/jise/2011/201101\_18.html},
timestamp = {Fri, 16 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jise/LuCL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChangHCL11,
author = {Chia{-}Jen Chang and
Pao{-}Jen Huang and
Tai{-}Chen Chen and
Chien{-}Nan Jimmy Liu},
title = {ILP-based inter-die routing for 3D ICs},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {330--335},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722209},
doi = {10.1109/ASPDAC.2011.5722209},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChangHCL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChangCCJLHK11,
author = {Chia{-}Wei Chang and
Hong{-}Zu Chou and
Kai{-}Hui Chang and
Jie{-}Hong Roland Jiang and
Chien{-}Nan Jimmy Liu and
Chiu{-}Han Hsiao and
Sy{-}Yen Kuo},
title = {Constraint generation for software-based post-silicon bug masking
with scalable resynthesis technique for constraint optimization},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {174--181},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770722},
doi = {10.1109/ISQED.2011.5770722},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChangCCJLHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LeeL10,
author = {Mu{-}Shun Matt Lee and
Chien{-}Nan Jimmy Liu},
title = {Dynamic Supply Current Waveform Estimation with Standard Library Information},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {93-A},
number = {3},
pages = {595--606},
year = {2010},
url = {https://doi.org/10.1587/transfun.E93.A.595},
doi = {10.1587/TRANSFUN.E93.A.595},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LeeL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsengSL10,
author = {Yuhwai Tseng and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {Measuring the Transmission Characteristic of the Human Body in an
Electrostatic-Coupling Intra Body Communication System Using a Square
Test Stimulus},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {93-A},
number = {3},
pages = {664--668},
year = {2010},
url = {https://doi.org/10.1587/transfun.E93.A.664},
doi = {10.1587/TRANSFUN.E93.A.664},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TsengSL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsengSL10a,
author = {Yuhwai Tseng and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {Measurement and Evaluation of the Bioelectrical Impedance of the Human
Body by Deconvolution of a Square Wave},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {93-D},
number = {6},
pages = {1656--1660},
year = {2010},
url = {https://doi.org/10.1587/transinf.E93.D.1656},
doi = {10.1587/TRANSINF.E93.D.1656},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TsengSL10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KuoL10,
author = {Chin{-}Cheng Kuo and
Chien{-}Nan Jimmy Liu},
title = {Fast and Accurate Analysis of Supply Noise Effects in {PLL} With Noise
Interactions},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {57-I},
number = {1},
pages = {44--52},
year = {2010},
url = {https://doi.org/10.1109/TCSI.2009.2016185},
doi = {10.1109/TCSI.2009.2016185},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KuoL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KuoCTCL10,
author = {Chin{-}Cheng Kuo and
Yen{-}Lung Chen and
I{-}Ching Tsai and
Li{-}Yu Chan and
Chien{-}Nan Jimmy Liu},
editor = {Sachin S. Sapatnekar},
title = {Behavior-level yield enhancement approach for large-scaled analog
circuits},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {903--908},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837501},
doi = {10.1145/1837274.1837501},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KuoCTCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiFLL10,
author = {Hsiu{-}Wen Li and
Ren{-}Hong Fu and
Hsin{-}Yu Luo and
Chien{-}Nan Jimmy Liu},
title = {Automatic circuit adjustment technique for process sensitivity reduction
and yield improvement},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {2582--2585},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537103},
doi = {10.1109/ISCAS.2010.5537103},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiFLL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LeeLHL10,
author = {Mu{-}Shun Matt Lee and
Kuo{-}Sheng Lai and
Chia{-}Ling Hsu and
Chien{-}Nan Jimmy Liu},
title = {Dynamic {IR} drop estimation at gate level with standard library information},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {2606--2609},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537092},
doi = {10.1109/ISCAS.2010.5537092},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LeeLHL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ChengTLHK09,
author = {Kuo{-}Hsing Cheng and
Yu{-}Chang Tsai and
Chien{-}Nan Jimmy Liu and
Kai{-}Wei Hong and
Chin{-}Cheng Kuo},
title = {A Low Jitter Self-Calibration {PLL} for 10-Gbps SoC Transmission Links
Application},
journal = {{IEICE} Trans. Electron.},
volume = {92-C},
number = {7},
pages = {964--972},
year = {2009},
url = {https://doi.org/10.1587/transele.E92.C.964},
doi = {10.1587/TRANSELE.E92.C.964},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ChengTLHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsengSL09,
author = {Yuhwai Tseng and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling
Intra-Body Communication System},
journal = {{IEICE} Trans. Commun.},
volume = {92-B},
number = {11},
pages = {3557--3563},
year = {2009},
url = {https://doi.org/10.1587/transcom.E92.B.3557},
doi = {10.1587/TRANSCOM.E92.B.3557},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TsengSL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangLJ09,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {Accurate Rank Ordering of Error Candidates for Efficient {HDL} Design
Debugging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {2},
pages = {272--284},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009163},
doi = {10.1109/TCAD.2008.2009163},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangLJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LuSL09,
author = {Hungwen Lu and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {A Tree-Topology Multiplexer for Multiphase Clock System},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {1},
pages = {124--131},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.926578},
doi = {10.1109/TCSI.2008.926578},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LuSL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KuoLLH09,
author = {Chin{-}Cheng Kuo and
Meng{-}Jung Lee and
Chien{-}Nan Jimmy Liu and
Ching{-}Ji Huang},
title = {Fast Statistical Analysis of Process Variation Effects Using Accurate
{PLL} Behavioral Models},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {6},
pages = {1160--1172},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2008502},
doi = {10.1109/TCSI.2008.2008502},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KuoLLH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LuWSL09,
author = {Hungwen Lu and
Hsin{-}Wen Wang and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {Design of an All-Digital {LVDS} Driver},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {8},
pages = {1635--1644},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2008279},
doi = {10.1109/TCSI.2008.2008279},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LuWSL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KuoLL09,
author = {Chin{-}Cheng Kuo and
Pei{-}Syun Lin and
Chien{-}Nan Jimmy Liu},
editor = {Kazutoshi Wakabayashi},
title = {A {SCORE} macromodel for {PLL} designs to analyze supply noise interaction
issues at behavioral level},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {516--521},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796532},
doi = {10.1109/ASPDAC.2009.4796532},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KuoLL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LuCLS09,
author = {Chao{-}Hung Lu and
Hung{-}Ming Chen and
Chien{-}Nan Jimmy Liu and
Wen{-}Yu Shih},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Package routability- and IR-drop-aware finger/pad assignment in chip-package
co-design},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {845--850},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090780},
doi = {10.1109/DATE.2009.5090780},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/LuCLS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jise/LuCL08,
author = {Chao{-}Hung Lu and
Hung{-}Ming Chen and
Chien{-}Nan Jimmy Liu},
title = {An Effective Decap Insertion Method Considering Power Supply Noise
during Floorplanning},
journal = {J. Inf. Sci. Eng.},
volume = {24},
number = {1},
pages = {115--127},
year = {2008},
url = {http://www.iis.sinica.edu.tw/page/jise/2008/200801\_08.html},
timestamp = {Fri, 16 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jise/LuCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LuSL08,
author = {Hungwen Lu and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {A Scalable Digitalized Buffer for Gigabit {I/O}},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {55-II},
number = {10},
pages = {1026--1030},
year = {2008},
url = {https://doi.org/10.1109/TCSII.2008.925661},
doi = {10.1109/TCSII.2008.925661},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LuSL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/WangCLLLS08,
author = {Chih{-}Hu Wang and
Bor{-}Sen Chen and
Bore{-}Kuen Lee and
Tsu{-}Tian Lee and
Chien{-}Nan Jimmy Liu and
Chauchin Su},
title = {Long-Range Prediction for Real-Time {MPEG} Video Traffic: An H\({}_{\mbox{infty}}\)
Filter Approach},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {18},
number = {12},
pages = {1771--1775},
year = {2008},
url = {https://doi.org/10.1109/TCSVT.2008.2004926},
doi = {10.1109/TCSVT.2008.2004926},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/WangCLLLS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LuCL08,
author = {Chao{-}Hung Lu and
Hung{-}Ming Chen and
Chien{-}Nan Jimmy Liu},
title = {Effective decap insertion in area-array SoC floorplan design},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {13},
number = {4},
pages = {66:1--66:20},
year = {2008},
url = {https://doi.org/10.1145/1391962.1391974},
doi = {10.1145/1391962.1391974},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LuCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/LuSL08,
author = {Hungwen Lu and
Chauchin Su and
Chien{-}Nan Liu},
title = {A scalable digitalized buffer for gigabit {I/O}},
booktitle = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference,
{CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September
21-24, 2008},
pages = {241--244},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/CICC.2008.4672068},
doi = {10.1109/CICC.2008.4672068},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/LuSL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LeeLLL08,
author = {Mu{-}Shun Matt Lee and
Chin{-}Hsun Lin and
Chien{-}Nan Jimmy Liu and
Shih{-}Che Lin},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {Quick supply current waveform estimation at gate level using existed
cell library information},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {135--138},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366144},
doi = {10.1145/1366110.1366144},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LeeLLL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ChuangCLL07,
author = {Chin{-}Lung Chuang and
Wei{-}Hsiang Cheng and
Dong{-}Jung Lu and
Chien{-}Nan Jimmy Liu},
title = {Hybrid Approach to Faster Functional Verification with Full Visibility},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {2},
pages = {154--162},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.46},
doi = {10.1109/MDT.2007.46},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/ChuangCLL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HsiehYLC07,
author = {Wen{-}Tsan Hsieh and
Chi{-}Chia Yu and
Chien{-}Nan Jimmy Liu and
Yi{-}Fang Chiu},
title = {An Efficient Approach with Scaling Capability to Improve Existing
Memory Power Model},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {90-A},
number = {5},
pages = {1038--1044},
year = {2007},
url = {https://doi.org/10.1093/ietfec/e90-a.5.1038},
doi = {10.1093/IETFEC/E90-A.5.1038},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HsiehYLC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jise/HsuHLJ07,
author = {Chih{-}Yang Hsu and
Wen{-}Tsan Hsieh and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {A Tableless Approach for High-Level Power Modeling Using Neural Networks},
journal = {J. Inf. Sci. Eng.},
volume = {23},
number = {1},
pages = {71--90},
year = {2007},
url = {http://www.iis.sinica.edu.tw/page/jise/2007/200701\_04.html},
timestamp = {Fri, 16 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jise/HsuHLJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangLJ07,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {Observability Analysis on {HDL} Descriptions for Effective Functional
Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1509--1521},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891366},
doi = {10.1109/TCAD.2007.891366},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangLJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LuCL07,
author = {Chao{-}Hung Lu and
Hung{-}Ming Chen and
Chien{-}Nan Jimmy Liu},
title = {On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array
SoC Floorplan Design},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {792--797},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358086},
doi = {10.1109/ASPDAC.2007.358086},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LuCL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/YehCHWLL07,
author = {Chi{-}Yi Yeh and
Hung{-}Ming Chen and
Li{-}Da Huang and
Wei{-}Ting Wei and
Chao{-}Hung Lu and
Chien{-}Nan Jimmy Liu},
title = {Using power gating techniques in area-array SoC floorplan design},
booktitle = {2007 {IEEE} International {SOC} Conference, Tampere, Finland, November
19-21, 2007},
pages = {233--236},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/SOCC.2007.4545465},
doi = {10.1109/SOCC.2007.4545465},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/YehCHWLL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KuoWL06,
author = {Chin{-}Cheng Kuo and
Yu{-}Chien Wang and
Chien{-}Nan Jimmy Liu},
title = {An Efficient Approach to Build Accurate Behavioral Models of {PLL}
Designs},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {89-A},
number = {2},
pages = {391--398},
year = {2006},
url = {https://doi.org/10.1093/ietfec/e89-a.2.391},
doi = {10.1093/IETFEC/E89-A.2.391},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KuoWL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsengLS06,
author = {Wenliang Tseng and
Chien{-}Nan Jimmy Liu and
Chauchin Su},
title = {Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect
Systems},
journal = {{IEICE} Trans. Electron.},
volume = {89-C},
number = {11},
pages = {1713--1718},
year = {2006},
url = {https://doi.org/10.1093/ietele/e89-c.11.1713},
doi = {10.1093/IETELE/E89-C.11.1713},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TsengLS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChengCL06,
author = {Wei{-}Hsiang Cheng and
Chin{-}Lung Chuang and
Chien{-}Nan Jimmy Liu},
title = {An efficient mechanism to provide full visibility for hardware debugging},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692709},
doi = {10.1109/ISCAS.2006.1692709},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChengCL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HsiehYLC06,
author = {Wen{-}Tsan Hsieh and
Chi{-}Chia Yu and
Chien{-}Nan Jimmy Liu and
Yi{-}Fang Chiu},
editor = {Johan Vounckx and
Nadine Az{\'{e}}mard and
Philippe Maurine},
title = {A Scalable Power Modeling Approach for Embedded Memory Using {LIB}
Format},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 16th International Workshop, {PATMOS} 2006, Montpellier,
France, September 13-15, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4148},
pages = {543--552},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11847083\_53},
doi = {10.1007/11847083\_53},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HsiehYLC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smc/WangLTFSL06,
author = {Chih{-}Hu Wang and
Bore{-}Kuen Lee and
Wei{-}Hang Tseng and
Chung{-}Hsi Fu and
Chauchin Su and
Chien{-}Nan Jimmy Liu},
title = {Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative
H{\(\infty\)} Filter},
booktitle = {Proceedings of the {IEEE} International Conference on Systems, Man
and Cybernetics, Taipei, Taiwan, October 8-11, 2006},
pages = {960--965},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ICSMC.2006.384524},
doi = {10.1109/ICSMC.2006.384524},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/smc/WangLTFSL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KuoL06,
author = {Chin{-}Cheng Kuo and
Chien{-}Nan Jimmy Liu},
title = {On Efficient Behavioral Modeling to Accurately Predict Supply Noise
Effects of {PLL} Designs in Real Systems},
booktitle = {{IFIP} VLSI-SoC 2006, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Nice, France, 16-18
October 2006},
pages = {116--121},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/VLSISOC.2006.313214},
doi = {10.1109/VLSISOC.2006.313214},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KuoL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JiangLJ05,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
editor = {Tingao Tang},
title = {An observability measure to enhance statement coverage metric for
proper evaluation of verification completeness},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {323--326},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120859},
doi = {10.1145/1120725.1120859},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JiangLJ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KuoWL05,
author = {Chin{-}Cheng Kuo and
Yu{-}Chien Wang and
Chien{-}Nan Jimmy Liu},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {An efficient bottom-up extraction approach to build accurate {PLL}
behavioral models for {SOC} designs},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {286--290},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057730},
doi = {10.1145/1057661.1057730},
timestamp = {Wed, 15 Dec 2021 17:59:57 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KuoWL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HsiehSL05,
author = {Wen{-}Tsan Hsieh and
Chih{-}Chieh Shiue and
Chien{-}Nan Jimmy Liu},
title = {A novel approach for high-level power modeling of sequential circuits
using recurrent neural networks},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {3591--3594},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465406},
doi = {10.1109/ISCAS.2005.1465406},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HsiehSL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/JiangLJ05,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {Estimating likelihood of correctness for error candidates to assist
debugging faulty {HDL} designs},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {5682--5685},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465927},
doi = {10.1109/ISCAS.2005.1465927},
timestamp = {Mon, 07 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/JiangLJ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ChuangLL04,
author = {Chin{-}Lung Chuang and
Dong{-}Jung Lu and
Chien{-}Nan Jimmy Liu},
title = {A Snapshot Method to Provide Full Visibility for Functional Debugging
Using {FPGA}},
booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting,
Taiwan},
pages = {164--169},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ATS.2004.15},
doi = {10.1109/ATS.2004.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ChuangLL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/ShaLL04,
author = {Yuan{-}Bin Sha and
Mu{-}Shun Matt Lee and
Chien{-}Nan Jimmy Liu},
title = {On code coverage measurement for Verilog-A},
booktitle = {Ninth {IEEE} International High-Level Design Validation and Test Workshop
2004, Sonoma Valley, CA, USA, November 10-12, 2004},
pages = {115--120},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/HLDVT.2004.1431251},
doi = {10.1109/HLDVT.2004.1431251},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/ShaLL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/LiuCJ03,
author = {Chien{-}Nan Jimmy Liu and
I{-}Ling Chen and
Jing{-}Yang Jou},
title = {A Design-for-Verification Technique for Functional Pattern Reduction},
journal = {{IEEE} Des. Test Comput.},
volume = {20},
number = {2},
pages = {48--55},
year = {2003},
url = {https://doi.org/10.1109/MDT.2003.1188262},
doi = {10.1109/MDT.2003.1188262},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/LiuCJ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/HsuLJ03,
author = {Chih{-}Yang Hsu and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {An Efficient Power Model for IP-Level Complex Designs},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {8},
pages = {2073--2080},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_8\_2073},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/HsuLJ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HsuLJ03,
author = {Chih{-}Yang Hsu and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
editor = {Hiroto Yasuura},
title = {An efficient IP-level power model for complex digital circuits},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {610--613},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119911},
doi = {10.1145/1119772.1119911},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HsuLJ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/JiangLJ02,
author = {Tai{-}Ying Jiang and
Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {Effective Error Diagnosis for {RTL} Designs in HDLs},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {362--367},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181738},
doi = {10.1109/ATS.2002.1181738},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/JiangLJ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuCJ01,
author = {Chien{-}Nan Jimmy Liu and
I{-}Ling Chen and
Jing{-}Yang Jou},
editor = {Satoshi Goto},
title = {An efficient design-for-verification technique for HDLs},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {103--108},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370291},
doi = {10.1145/370155.370291},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiuCJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiuYJ01,
author = {Chien{-}Nan Jimmy Liu and
Chia{-}Chih Yen and
Jing{-}Yang Jou},
title = {Automatic Functional Vector Generation Using the Interacting {FSM}
Model},
booktitle = {2nd International Symposium on Quality of Electronic Design {(ISQED}
2001), 26-28 March 2001, San Jose, CA, {USA}},
pages = {372--377},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ISQED.2001.915258},
doi = {10.1109/ISQED.2001.915258},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/LiuYJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/LiuJ00,
author = {Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {An Automatic Controller Extractor for {HDL} Descriptions at the {RTL}},
journal = {{IEEE} Des. Test Comput.},
volume = {17},
number = {3},
pages = {72--77},
year = {2000},
url = {https://doi.org/10.1109/54.867897},
doi = {10.1109/54.867897},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/LiuJ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiuCJLJ00,
author = {Chien{-}Nan Jimmy Liu and
Chen{-}Yi Chang and
Jing{-}Yang Jou and
Ming{-}Chih Lai and
Hsing{-}Ming Juan},
title = {A novel approach for functional coverage measurement in {HDL}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {217--220},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.858727},
doi = {10.1109/ISCAS.2000.858727},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiuCJLJ00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LiuJ99,
author = {Chien{-}Nan Jimmy Liu and
Jing{-}Yang Jou},
title = {An Efficient Functional Coverage Test for {HDL} Descriptions at {RTL}},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
{VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
October 10-13, 1999},
pages = {325--327},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCD.1999.808561},
doi = {10.1109/ICCD.1999.808561},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LiuJ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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