BibTeX records: Bosheng Liu

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@inproceedings{DBLP:conf/aspdac/LiWLHL19,
  author    = {Jiajun Li and
               Ying Wang and
               Bosheng Liu and
               Yinhe Han and
               Xiaowei Li},
  title     = {Simulate-the-hardware: training accurate binarized neural networks
               for low-precision neural accelerators},
  booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
               {ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
  pages     = {323--328},
  year      = {2019},
  crossref  = {DBLP:conf/aspdac/2019},
  url       = {https://doi.org/10.1145/3287624.3287628},
  doi       = {10.1145/3287624.3287628},
  timestamp = {Sun, 20 Jan 2019 16:08:16 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/LiWLHL19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuCWHLXL19,
  author    = {Bosheng Liu and
               Xiaoming Chen and
               Ying Wang and
               Yinhe Han and
               Jiajun Li and
               Haobo Xu and
               Xiaowei Li},
  title     = {Addressing the issue of processing element under-utilization in general-purpose
               systolic deep learning accelerators},
  booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
               {ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
  pages     = {733--738},
  year      = {2019},
  crossref  = {DBLP:conf/aspdac/2019},
  url       = {https://doi.org/10.1145/3287624.3287638},
  doi       = {10.1145/3287624.3287638},
  timestamp = {Sun, 20 Jan 2019 16:08:16 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/LiuCWHLXL19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SongWHZLL16,
  author    = {Lili Song and
               Ying Wang and
               Yinhe Han and
               Xin Zhao and
               Bosheng Liu and
               Xiaowei Li},
  title     = {C-brain: a deep learning accelerator that tames the diversity of CNNs
               through adaptive data-level parallelization},
  booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
               2016, Austin, TX, USA, June 5-9, 2016},
  pages     = {123:1--123:6},
  year      = {2016},
  crossref  = {DBLP:conf/dac/2016},
  url       = {https://doi.org/10.1145/2897937.2897995},
  doi       = {10.1145/2897937.2897995},
  timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/dac/SongWHZLL16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/LiuWYHL15,
  author    = {Bosheng Liu and
               Ying Wang and
               Zhiqiang You and
               Yinhe Han and
               Xiaowei Li},
  title     = {A signal degradation reduction method for memristor ratioed logic
               {(MRL)} gates},
  journal   = {{IEICE} Electronic Express},
  volume    = {12},
  number    = {8},
  pages     = {20150062},
  year      = {2015},
  url       = {https://doi.org/10.1587/elex.12.20150062},
  doi       = {10.1587/elex.12.20150062},
  timestamp = {Wed, 06 Sep 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieiceee/LiuWYHL15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/LiuYLKQ13,
  author    = {Bosheng Liu and
               Zhiqiang You and
               Xiangrao Li and
               Jishun Kuang and
               Zheng Qin},
  title     = {Comparator and half adder design using complementary resistive switches
               crossbar},
  journal   = {{IEICE} Electronic Express},
  volume    = {10},
  number    = {13},
  pages     = {20130369},
  year      = {2013},
  url       = {https://doi.org/10.1587/elex.10.20130369},
  doi       = {10.1587/elex.10.20130369},
  timestamp = {Sat, 27 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieiceee/LiuYLKQ13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tce/WangLZ09,
  author    = {Jianping Wang and
               Bosheng Liu and
               Xianwei Zhou},
  title     = {{PCE} algorithm for {PAPR} reduction in {OFDM-ROF} system},
  journal   = {{IEEE} Trans. Consumer Electronics},
  volume    = {55},
  number    = {3},
  pages     = {1078--1082},
  year      = {2009},
  url       = {https://doi.org/10.1109/TCE.2009.5277959},
  doi       = {10.1109/TCE.2009.5277959},
  timestamp = {Sun, 28 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tce/WangLZ09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2019,
  editor    = {Toshiyuki Shibuya},
  title     = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
               {ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3287624},
  doi       = {10.1145/3287624},
  isbn      = {978-1-4503-6007-4},
  timestamp = {Sun, 20 Jan 2019 16:08:16 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2019},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dac/2016,
  title     = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
               2016, Austin, TX, USA, June 5-9, 2016},
  publisher = {{ACM}},
  year      = {2016},
  url       = {https://doi.org/10.1145/2897937},
  doi       = {10.1145/2897937},
  isbn      = {978-1-4503-4236-0},
  timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/dac/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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