BibTeX records: Nan-Chun Lien

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@article{DBLP:journals/jssc/SiTHSLWLWLCCSLL21,
  author       = {Xin Si and
                  Yung{-}Ning Tu and
                  Wei{-}Hsing Huang and
                  Jian{-}Wei Su and
                  Pei{-}Jung Lu and
                  Jing{-}Hong Wang and
                  Ta{-}Wei Liu and
                  Ssu{-}Yen Wu and
                  Ruhui Liu and
                  Yen{-}Chi Chou and
                  Yen{-}Lin Chung and
                  William Shih and
                  Chung{-}Chuan Lo and
                  Ren{-}Shuo Liu and
                  Chih{-}Cheng Hsieh and
                  Kea{-}Tiong Tang and
                  Nan{-}Chun Lien and
                  Wei{-}Chiang Shih and
                  Yajuan He and
                  Qiang Li and
                  Meng{-}Fan Chang},
  title        = {A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro
                  With 8-b {MAC} Operation for Edge {AI} Chips},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {56},
  number       = {9},
  pages        = {2817--2831},
  year         = {2021},
  url          = {https://doi.org/10.1109/JSSC.2021.3073254},
  doi          = {10.1109/JSSC.2021.3073254},
  timestamp    = {Thu, 16 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/SiTHSLWLWLCCSLL21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/SiTHSLWLWLCZSWL20,
  author       = {Xin Si and
                  Yung{-}Ning Tu and
                  Wei{-}Hsing Huang and
                  Jian{-}Wei Su and
                  Pei{-}Jung Lu and
                  Jing{-}Hong Wang and
                  Ta{-}Wei Liu and
                  Ssu{-}Yen Wu and
                  Ruhui Liu and
                  Yen{-}Chi Chou and
                  Zhixiao Zhang and
                  Syuan{-}Hao Sie and
                  Wei{-}Chen Wei and
                  Yun{-}Chen Lo and
                  Tai{-}Hsing Wen and
                  Tzu{-}Hsiang Hsu and
                  Yen{-}Kai Chen and
                  William Shih and
                  Chung{-}Chuan Lo and
                  Ren{-}Shuo Liu and
                  Chih{-}Cheng Hsieh and
                  Kea{-}Tiong Tang and
                  Nan{-}Chun Lien and
                  Wei{-}Chiang Shih and
                  Yajuan He and
                  Qiang Li and
                  Meng{-}Fan Chang},
  title        = {15.5 {A} 28nm 64Kb 6T {SRAM} Computing-in-Memory Macro with 8b {MAC}
                  Operation for {AI} Edge Chips},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {246--248},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062995},
  doi          = {10.1109/ISSCC19947.2020.9062995},
  timestamp    = {Wed, 09 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/SiTHSLWLWLCZSWL20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcas/LienCCYTKHCJH14,
  author       = {Nan{-}Chun Lien and
                  Li{-}Wei Chu and
                  Chien{-}Hen Chen and
                  Hao{-}I Yang and
                  Ming{-}Hsien Tu and
                  Paul{-}Sen Kan and
                  Yong{-}Jyun Hu and
                  Ching{-}Te Chuang and
                  Shyh{-}Jye Jou and
                  Wei Hwang},
  title        = {A 40 nm 512 kb Cross-Point 8 {T} Pipeline {SRAM} With Binary Word-Line
                  Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {61-I},
  number       = {12},
  pages        = {3416--3425},
  year         = {2014},
  url          = {https://doi.org/10.1109/TCSI.2014.2336531},
  doi          = {10.1109/TCSI.2014.2336531},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/LienCCYTKHCJH14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/ChangYLLLCCHJTHHKCWWLCS13,
  author       = {Chi{-}Shin Chang and
                  Hao{-}I Yang and
                  Wei{-}Nan Liao and
                  Yi{-}Wei Lin and
                  Nan{-}Chun Lien and
                  Chien{-}Hen Chen and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Shyh{-}Jye Jou and
                  Ming{-}Hsien Tu and
                  Huan{-}Shun Huang and
                  Yong{-}Jyun Hu and
                  Paul{-}Sen Kan and
                  Cheng{-}Yo Cheng and
                  Wei{-}Chang Wang and
                  Jian{-}Hao Wang and
                  Kuen{-}Di Lee and
                  Chia{-}Cheng Chen and
                  Wei{-}Chiang Shih},
  title        = {A 40nm 1.0Mb pipeline 6T {SRAM} with variation-tolerant Step-Up Word-Line
                  and Adaptive Data-Aware Write-Assist},
  booktitle    = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
                  Beijing, China, May 19-23, 2013},
  pages        = {1468--1471},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISCAS.2013.6572134},
  doi          = {10.1109/ISCAS.2013.6572134},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ChangYLLLCCHJTHHKCWWLCS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/LienCW13,
  author       = {Nan{-}Chun Lien and
                  Ching{-}Te Chuang and
                  Wen{-}Rong Wu},
  editor       = {Norbert Schuhmann and
                  Kaijian Shi and
                  Nagi Naganathan},
  title        = {Method for resolving simultaneous same-row access in Dual-Port 8T
                  {SRAM} with asynchronous dual-clock operation},
  booktitle    = {2013 {IEEE} International {SOC} Conference, Erlangen, Germany, September
                  4-6, 2013},
  pages        = {105--109},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/SOCC.2013.6749669},
  doi          = {10.1109/SOCC.2013.6749669},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/LienCW13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/LiaoLCCYCJHTHWKH13,
  author       = {Wei{-}Nan Liao and
                  Nan{-}Chun Lien and
                  Chi{-}Shin Chang and
                  Li{-}Wei Chu and
                  Hao{-}I Yang and
                  Ching{-}Te Chuang and
                  Shyh{-}Jye Jou and
                  Wei Hwang and
                  Ming{-}Hsien Tu and
                  Huan{-}Shun Huang and
                  Jian{-}Hao Wang and
                  Paul{-}Sen Kan and
                  Yong{-}Jyun Hu},
  editor       = {Norbert Schuhmann and
                  Kaijian Shi and
                  Nagi Naganathan},
  title        = {A 40nm 1.0Mb 6T pipeline {SRAM} with digital-based Bit-Line Under-Drive,
                  Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with {VCS}
                  tracking and Adaptive Voltage Detector for boosting control},
  booktitle    = {2013 {IEEE} International {SOC} Conference, Erlangen, Germany, September
                  4-6, 2013},
  pages        = {110--115},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/SOCC.2013.6749670},
  doi          = {10.1109/SOCC.2013.6749670},
  timestamp    = {Tue, 23 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/LiaoLCCYCJHTHWKH13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/apccas/WangLLTCJCLSLC12,
  author       = {Shao{-}Cheng Wang and
                  Geng{-}Cing Lin and
                  Yi{-}Wei Lin and
                  Ming{-}Chien Tsai and
                  Yi{-}Wei Chiu and
                  Shyh{-}Jye Jou and
                  Ching{-}Te Chuang and
                  Nan{-}Chun Lien and
                  Wei{-}Chiang Shih and
                  Kuen{-}Di Lee and
                  Jyun{-}Kai Chu},
  title        = {Design and implementation of dynamic Word-Line pulse write margin
                  monitor for {SRAM}},
  booktitle    = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2012,
                  Kaohsiung, Taiwan, December 2-5, 2012},
  pages        = {116--119},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/APCCAS.2012.6418985},
  doi          = {10.1109/APCCAS.2012.6418985},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/apccas/WangLLTCJCLSLC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/YangLHLCCCHJLLLSWLH12,
  author       = {Hao{-}I Yang and
                  Yi{-}Wei Lin and
                  Mao{-}Chih Hsia and
                  Geng{-}Cing Lin and
                  Chi{-}Shin Chang and
                  Yin{-}Nien Chen and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Shyh{-}Jye Jou and
                  Nan{-}Chun Lien and
                  Hung{-}Yu Li and
                  Kuen{-}Di Lee and
                  Wei{-}Chiang Shih and
                  Ya{-}Ping Wu and
                  Wen{-}Ta Lee and
                  Chih{-}Chiang Hsu},
  title        = {High-performance 0.6V {VMIN} 55nm 1.0Mb 6T {SRAM} with adaptive {BL}
                  bleeder},
  booktitle    = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  2012, Seoul, Korea (South), May 20-23, 2012},
  pages        = {1831--1834},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISCAS.2012.6271624},
  doi          = {10.1109/ISCAS.2012.6271624},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/YangLHLCCCHJLLLSWLH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/LinWLTCJLSLC12,
  author       = {Geng{-}Cing Lin and
                  Shao{-}Cheng Wang and
                  Yi{-}Wei Lin and
                  Ming{-}Chien Tsai and
                  Ching{-}Te Chuang and
                  Shyh{-}Jye Jou and
                  Nan{-}Chun Lien and
                  Wei{-}Chiang Shih and
                  Kuen{-}Di Lee and
                  Jyun{-}Kai Chu},
  title        = {An all-digital bit transistor characterization scheme for {CMOS} 6T
                  {SRAM} array},
  booktitle    = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  2012, Seoul, Korea (South), May 20-23, 2012},
  pages        = {2485--2488},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISCAS.2012.6271804},
  doi          = {10.1109/ISCAS.2012.6271804},
  timestamp    = {Fri, 26 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/LinWLTCJLSLC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/LinYHLCCHLLSWLH12,
  author       = {Yung{-}Wei Lin and
                  Hao{-}I Yang and
                  Mao{-}Chih Hsia and
                  Yi{-}Wei Lin and
                  Chien{-}Hen Chen and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Nan{-}Chun Lien and
                  Kuen{-}Di Lee and
                  Wei{-}Chiang Shih and
                  Ya{-}Ping Wu and
                  Wen{-}Ta Lee and
                  Chih{-}Chiang Hsu},
  editor       = {Ramalingam Sridhar and
                  Norbert Schuhmann and
                  Kaijian Shi},
  title        = {A 55nm 0.5V 128Kb cross-point 8T {SRAM} with data-aware dynamic supply
                  Write-assist},
  booktitle    = {{IEEE} 25th International {SOC} Conference, {SOCC} 2012, Niagara Falls,
                  NY, USA, September 12-14, 2012},
  pages        = {218--223},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/SOCC.2012.6398351},
  doi          = {10.1109/SOCC.2012.6398351},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/LinYHLCCHLLSWLH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi-dat/LinTYLWCJHLLS12,
  author       = {Yi{-}Wei Lin and
                  Ming{-}Chien Tsai and
                  Hao{-}I Yang and
                  Geng{-}Cing Lin and
                  Shao{-}Cheng Wang and
                  Ching{-}Te Chuang and
                  Shyh{-}Jye Jou and
                  Wei Hwang and
                  Nan{-}Chun Lien and
                  Kuen{-}Di Lee and
                  Wei{-}Chiang Shih},
  title        = {An all-digital Read Stability and Write Margin characterization scheme
                  for {CMOS} 6T {SRAM} array},
  booktitle    = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation
                  and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSI-DAT.2012.6212589},
  doi          = {10.1109/VLSI-DAT.2012.6212589},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/LinTYLWCJHLLS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi-dat/TsaiLYTSLLJCH12,
  author       = {Ming{-}Chien Tsai and
                  Yi{-}Wei Lin and
                  Hao{-}I Yang and
                  Ming{-}Hsien Tu and
                  Wei{-}Chiang Shih and
                  Nan{-}Chun Lien and
                  Kuen{-}Di Lee and
                  Shyh{-}Jye Jou and
                  Ching{-}Te Chuang and
                  Wei Hwang},
  title        = {Embedded {SRAM} ring oscillator for in-situ measurement of {NBTI}
                  and {PBTI} degradation in {CMOS} 6T {SRAM} array},
  booktitle    = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation
                  and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSI-DAT.2012.6212587},
  doi          = {10.1109/VLSI-DAT.2012.6212587},
  timestamp    = {Fri, 26 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/TsaiLYTSLLJCH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/YangYHLLCCLCCHJLLLSWLH11,
  author       = {Hao{-}I Yang and
                  Shih{-}Chi Yang and
                  Mao{-}Chih Hsia and
                  Yung{-}Wei Lin and
                  Yi{-}Wei Lin and
                  Chien{-}Hen Chen and
                  Chi{-}Shin Chang and
                  Geng{-}Cing Lin and
                  Yin{-}Nien Chen and
                  Ching{-}Te Chuang and
                  Wei Hwang and
                  Shyh{-}Jye Jou and
                  Nan{-}Chun Lien and
                  Hung{-}Yu Li and
                  Kuen{-}Di Lee and
                  Wei{-}Chiang Shih and
                  Ya{-}Ping Wu and
                  Wen{-}Ta Lee and
                  Chih{-}Chiang Hsu},
  title        = {A high-performance low {VMIN} 55nm 512Kb disturb-free 8T {SRAM} with
                  adaptive {VVSS} control},
  booktitle    = {{IEEE} 24th International SoC Conference, {SOCC} 2011, Taipei, Taiwan,
                  September 26-28, 2011},
  pages        = {197--200},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/SOCC.2011.6085080},
  doi          = {10.1109/SOCC.2011.6085080},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/YangYHLLCCLCCHJLLLSWLH11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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