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@article{DBLP:journals/jssc/AoyagiNYTIONWHCLC24,
author = {Yumito Aoyagi and
Koji Nii and
Makoto Yabuuchi and
Tomotaka Tanaka and
Yuichiro Ishii and
Yoshiaki Osada and
Takaaki Nakazato and
Isabel Wang and
Yu{-}Hao Hsu and
Hong{-}Chen Cheng and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {A 3-nm FinFET 27.6-Mbit/mm\({}^{\mbox{2}}\) Single-Port 6T {SRAM}
Enabling 0.48-1.2 {V} Wide Operating Range With Far-End Pre-Charge
and Weak-Bit Tracking},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {4},
pages = {1225--1234},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2024.3355447},
doi = {10.1109/JSSC.2024.3355447},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AoyagiNYTIONWHCLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24,
author = {Hidehiro Fujiwara and
Haruki Mori and
Wei{-}Chang Zhao and
Kinshuk Khare and
Cheng{-}En Lee and
Xiaochen Peng and
Vineet Joshi and
Chao{-}Kai Chuang and
Shu{-}Huan Hsu and
Takeshi Hashizume and
Toshiaki Naganuma and
Chen{-}Hung Tien and
Yao{-}Yi Liu and
Yen{-}Chien Lai and
Chia{-}Fu Lee and
Tan{-}Li Chou and
Kerem Akarvardar and
Saman Adham and
Yih Wang and
Yu{-}Der Chih and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {34.4 {A} 3nm, 32.5TOPS/W, 55.0TOPS/mm\({}^{\mbox{2}}\) and 3.78Mb/mm\({}^{\mbox{2}}\)
Fully-Digital Compute-in-Memory Macro Supporting {INT12} {\texttimes}
{INT12} with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {572--574},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454556},
doi = {10.1109/ISSCC49657.2024.10454556},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraMZKLPJCHHNTLLLCAAWCCLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MoriZLLHCHTLWACFWCCLC23,
author = {Haruki Mori and
Wei{-}Chang Zhao and
Cheng{-}En Lee and
Chia{-}Fu Lee and
Yu{-}Hao Hsu and
Chao{-}Kai Chuang and
Takeshi Hashizume and
Hao{-}Chun Tung and
Yao{-}Yi Liu and
Shin{-}Rung Wu and
Kerem Akarvardar and
Tan{-}Li Chou and
Hidehiro Fujiwara and
Yih Wang and
Yu{-}Der Chih and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {A 4nm 6163-TOPS/W/b {\textdollar}{\textbackslash}mathbf\{4790-TOPS/mm{\^{}}\{2\}/b\}{\textdollar}
{SRAM} Based Digital-Computing-in-Memory Macro Supporting Bit-Width
Flexibility and Simultaneous {MAC} and Weight Update},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {132--133},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067555},
doi = {10.1109/ISSCC42615.2023.10067555},
timestamp = {Wed, 29 Mar 2023 15:53:39 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MoriZLLHCHTLWACFWCCLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/AoyagiYTIONNWHC23,
author = {Yumito Aoyagi and
Makoto Yabuuchi and
Tomotaka Tanaka and
Yuichiro Ishii and
Yoshiaki Osada and
Takaaki Nakazato and
Koji Nii and
Isabel Wang and
Yu{-}Hao Hsu and
Hong{-}Chen Cheng and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {A 3-nm 27.6-Mbit/mm2 Self-timed {SRAM} Enabling 0.48 - 1.2 {V} Wide
Operating Range with Far-end Pre-charge and Weak-Bit Tracking},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185429},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185429},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/AoyagiYTIONNWHC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/ChangCCLWLCLWLN23,
author = {Jonathan Chang and
Yen{-}Huei Chen and
Gary Chan and
Kuo{-}Cheng Lin and
Po{-}Sheng Wang and
Yangsyu Lin and
Sevic Chen and
Peijiun Lin and
Ching{-}Wei Wu and
Chih{-}Yu Lin and
Yi{-}Hsin Nien and
Hidehiro Fujiwara and
Atul Katoch and
Robin Lee and
Hung{-}Jen Liao and
Jhon{-}Jhy Liaw and
Shien{-}Yang Michael Wu and
Quincy Li},
title = {A 3nm 256Mb {SRAM} in FinFET Technology with New Array Banking Architecture
and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185287},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185287},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/ChangCCLWLCLWLN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/OsadaNNLWLFLC23,
author = {Yoshiaki Osada and
Takaaki Nakazato and
Koji Nii and
Jhon{-}Jhy Liaw and
Shien{-}Yang Michael Wu and
Quincy Li and
Hidehiro Fujiwara and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {3.7-GHz Multi-Bank High-Current Single-Port Cache {SRAM} with 0.5V-1.4V
Wide Voltage Range Operation in 3nm FinFET for {HPC} Applications},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185289},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185289},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/OsadaNNLWLFLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/ZhangKHKTLWYLC23,
author = {Nick Zhang and
Young Suk Kim and
Peter Hsu and
Samsoo Kim and
Derek Tao and
Hung{-}Jen Liao and
Ping{-}Wei Wang and
Geoffrey Yeap and
Quincy Li and
Tsung{-}Yung Jonathan Chang},
title = {A 4.24GHz 128X256 {SRAM} Operating Double Pump Read Write Same Cycle
in 5nm Technology},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185268},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185268},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/ZhangKHKTLWYLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraMZCNCHS22,
author = {Hidehiro Fujiwara and
Haruki Mori and
Wei{-}Chang Zhao and
Mei{-}Chen Chuang and
Rawan Naous and
Chao{-}Kai Chuang and
Takeshi Hashizume and
Dar Sun and
Chia{-}Fu Lee and
Kerem Akarvardar and
Saman Adham and
Tan{-}Li Chou and
Mahmut Ersin Sinangil and
Yih Wang and
Yu{-}Der Chih and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Tsung{-}Yung Jonathan Chang},
title = {A 5-nm 254-TOPS/W 221-TOPS/mm\({}^{\mbox{2}}\) Fully-Digital Computing-in-Memory
Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and
Simultaneous {MAC} and Write Operations},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731754},
doi = {10.1109/ISSCC42614.2022.9731754},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraMZCNCHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/AkkayaCLWC22,
author = {Nail Etkin Can Akkaya and
Gary Chan and
Hung{-}Jen Liao and
Yih Wang and
Jonathan Chang},
title = {A 135.6Tbps/W 2R2W {SRAM} with 12T Logic Bit-cell with Vmin Down to
335mV Targeted for Machine-Learning Applications in 6nm FinFET {CMOS}
Technology},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {110--111},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830214},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830214},
timestamp = {Thu, 04 Aug 2022 10:53:40 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/AkkayaCLWC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangCCCWLFLLWY21,
author = {Tsung{-}Yung Jonathan Chang and
Yen{-}Huei Chen and
Wei{-}Min Chan and
Hank Cheng and
Po{-}Sheng Wang and
Yangsyu Lin and
Hidehiro Fujiwara and
Robin Lee and
Hung{-}Jen Liao and
Ping{-}Wei Wang and
Geoffrey Yeap and
Quincy Li},
title = {A 5-nm 135-Mb {SRAM} in {EUV} and High-Mobility Channel FinFET Technology
With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes
for High-Density and Low-V\({}_{\mbox{MIN}}\) Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {1},
pages = {179--187},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3034241},
doi = {10.1109/JSSC.2020.3034241},
timestamp = {Sat, 09 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangCCCWLFLLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinangilENASKLW21,
author = {Mahmut E. Sinangil and
Burak Erbagci and
Rawan Naous and
Kerem Akarvardar and
Dar Sun and
Win{-}San Khwa and
Hung{-}Jen Liao and
Yih Wang and
Jonathan Chang},
title = {A 7-nm Compute-in-Memory {SRAM} Macro Supporting Multi-Bit Input,
Weight and Output and Achieving 351 {TOPS/W} and 372.4 {GOPS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {1},
pages = {188--198},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3031290},
doi = {10.1109/JSSC.2020.3031290},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinangilENASKLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChihLFSLNCLLMZS21,
author = {Yu{-}Der Chih and
Po{-}Hao Lee and
Hidehiro Fujiwara and
Yi{-}Chun Shih and
Chia{-}Fu Lee and
Rawan Naous and
Yu{-}Lin Chen and
Chieh{-}Pu Lo and
Cheng{-}Han Lu and
Haruki Mori and
Wei{-}Cheng Zhao and
Dar Sun and
Mahmut E. Sinangil and
Yen{-}Huei Chen and
Tan{-}Li Chou and
Kerem Akarvardar and
Hung{-}Jen Liao and
Yih Wang and
Meng{-}Fan Chang and
Tsung{-}Yung Jonathan Chang},
title = {An 89TOPS/W and 16.3TOPS/mm\({}^{\mbox{2}}\) All-Digital SRAM-Based
Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning
Edge Applications},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {252--254},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365766},
doi = {10.1109/ISSCC42613.2021.9365766},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChihLFSLNCLLMZS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraNLPHWLC21,
author = {Hidehiro Fujiwara and
Yi{-}Hsin Nien and
Chih{-}Yu Lin and
Hsien{-}Yu Pan and
Hao{-}Wen Hsu and
Shin{-}Rung Wu and
Yao{-}Yi Liu and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port
Register File with a 16T Bitcell with No Half-Selection Issue},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {340--342},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9366000},
doi = {10.1109/ISSCC42613.2021.9366000},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraNLPHWLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wocc/LiaoY21,
author = {Hung{-}Jen Liao and
Chin{-}Ping Yu},
title = {3D-printed mold-assisted U-shaped optical fiber sensor for displacement
sensing},
booktitle = {30th Wireless and Optical Communications Conference, {WOCC} 2021,
Taipei, Taiwan, October 7-8, 2021},
pages = {115--117},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/WOCC53213.2021.9603211},
doi = {10.1109/WOCC53213.2021.9603211},
timestamp = {Wed, 01 Dec 2021 17:46:16 +0100},
biburl = {https://dblp.org/rec/conf/wocc/LiaoY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCCWLFLLWY20,
author = {Jonathan Chang and
Yen{-}Huei Chen and
Gary Chan and
Hank Cheng and
Po{-}Sheng Wang and
Yangsyu Lin and
Hidehiro Fujiwara and
Robin Lee and
Hung{-}Jen Liao and
Ping{-}Wei Wang and
Geoffrey Yeap and
Quincy Li},
title = {15.1 {A} 5nm 135Mb {SRAM} in {EUV} and High-Mobility-Channel FinFET
Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry
Schemes for High-Density and Low-VMIN Applications},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {238--240},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062967},
doi = {10.1109/ISSCC19947.2020.9062967},
timestamp = {Sat, 18 Apr 2020 17:41:44 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangCCCWLFLLWY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/0001SESKLWC20,
author = {Qing Dong and
Mahmut E. Sinangil and
Burak Erbagci and
Dar Sun and
Win{-}San Khwa and
Hung{-}Jen Liao and
Yih Wang and
Jonathan Chang},
title = {15.3 {A} 351TOPS/W and 372.4GOPS Compute-in-Memory {SRAM} Macro in
7nm FinFET {CMOS} for Machine-Learning Applications},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {242--244},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062985},
doi = {10.1109/ISSCC19947.2020.9062985},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/0001SESKLWC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinangilLLC19,
author = {Mahmut E. Sinangil and
Yen{-}Ting Lin and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 290-mV, 7-nm Ultra-Low-Voltage One-Port {SRAM} Compiler Design Using
a 12T Write Contention and Read Upset Free Bit-Cell},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {4},
pages = {1152--1160},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2019.2895236},
doi = {10.1109/JSSC.2019.2895236},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinangilLLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraLPLHLLC19,
author = {Hidehiro Fujiwara and
Chih{-}Yu Lin and
Hsien{-}Yu Pan and
Cheng{-}Han Lin and
Po{-}Yi Huang and
Kao{-}Cheng Lin and
Jhon{-}Jhy Liaw and
Yen{-}Huei Chen and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 7nm 2.1GHz Dual-Port {SRAM} with {WL-RC} Optimization and Dummy-Read-Recovery
Circuitry to Mitigate Read- Disturb-Write Issue},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {390--392},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662415},
doi = {10.1109/ISSCC.2019.8662415},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraLPLHLLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SinangilLLC18,
author = {Mahmut E. Sinangil and
Yen{-}Ting Lin and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 290MV Ultra-Low Voltage One-Port {SRAM} Compiler Design Using a
12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {13--14},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502419},
doi = {10.1109/VLSIC.2018.8502419},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/SinangilLLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCSCFLLHLL17,
author = {Jonathan Chang and
Yen{-}Huei Chen and
Wei{-}Min Chan and
Sahil Preet Singh and
Hank Cheng and
Hidehiro Fujiwara and
Jih{-}Yu Lin and
Kao{-}Cheng Lin and
John Hung and
Robin Lee and
Hung{-}Jen Liao and
Jhon{-}Jhy Liaw and
Quincy Li and
Chih{-}Yung Lin and
Mu{-}Chi Chiang and
Shien{-}Yang Wu},
title = {12.1 {A} 7nm 256Mb {SRAM} in high-k metal-gate FinFET technology with
write-assist circuitry for low-VMIN applications},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {206--207},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870333},
doi = {10.1109/ISSCC.2017.7870333},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangCCSCFLLHLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ClintonCLLWYHWY17,
author = {Michael Clinton and
Hank Cheng and
Hung{-}Jen Liao and
Robin Lee and
Ching{-}Wei Wu and
Johnny Yang and
Hau{-}Tai Hsieh and
Frank Wu and
Jung{-}Ping Yang and
Atul Katoch and
Arun Achyuthan and
Donald Mikan and
Bryan Sheffield and
Jonathan Chang},
title = {12.3 {A} low-power and high-performance 10nm {SRAM} architecture for
mobile applications},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {210--211},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870335},
doi = {10.1109/ISSCC.2017.7870335},
timestamp = {Wed, 10 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ClintonCLLWYHWY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/wicomm/LinLLLH16,
author = {Chun{-}Hung Richard Lin and
Hung{-}Jen Liao and
Ying{-}Chih Lin and
Jain{-}Shing Liu and
Yu{-}Hsiu Huang},
title = {An efficient tabu search for cell planning problem in mobile communication},
journal = {Wirel. Commun. Mob. Comput.},
volume = {16},
number = {4},
pages = {486--496},
year = {2016},
url = {https://doi.org/10.1002/wcm.2549},
doi = {10.1002/WCM.2549},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/wicomm/LinLLLH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/FujiwaraCLWSWLC16,
author = {Hidehiro Fujiwara and
Yen{-}Huei Chen and
Chih{-}Yu Lin and
Wei{-}Cheng Wu and
Dar Sun and
Shin{-}Rung Wu and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted {WL}
scheme for IoT applications},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {185--188},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844166},
doi = {10.1109/ASSCC.2016.7844166},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/FujiwaraCLWSWLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenLWCLLC16,
author = {Yen{-}Huei Chen and
Kao{-}Cheng Lin and
Ching{-}Wei Wu and
Wei{-}Min Chan and
Jhon{-}Jhy Liaw and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 16nm dual-port {SRAM} with partial suppressed word-line, dummy read
recovery and negative bit-line circuitries for low {VMIN} applications},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573459},
doi = {10.1109/VLSIC.2016.7573459},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenLWCLLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCWLPLCLLCWC15,
author = {Yen{-}Huei Chen and
Wei{-}Min Chan and
Wei{-}Cheng Wu and
Hung{-}Jen Liao and
Kuo{-}Hua Pan and
Jhon{-}Jhy Liaw and
Tang{-}Hsuan Chung and
Quincy Li and
Chih{-}Yung Lin and
Mu{-}Chi Chiang and
Shien{-}Yang Wu and
Jonathan Chang},
title = {A 16 nm 128 Mb {SRAM} in High-{\(\kappa\)} Metal-Gate FinFET Technology
With Write-Assist Circuitry for Low-VMIN Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {170--177},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2349977},
doi = {10.1109/JSSC.2014.2349977},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChenCWLPLCLLCWC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraWCLSWLL15,
author = {Hidehiro Fujiwara and
Li{-}Wen Wang and
Yen{-}Huei Chen and
Kao{-}Cheng Lin and
Dar Sun and
Shin{-}Rung Wu and
Jhon{-}Jhy Liaw and
Chih{-}Yung Lin and
Mu{-}Chi Chiang and
Hung{-}Jen Liao and
Shien{-}Yang Wu and
Jonathan Chang},
title = {17.2 {A} 64kb 16nm asynchronous disturb current free 2-port {SRAM}
with {PMOS} pass-gates for FinFET technologies},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7063051},
doi = {10.1109/ISSCC.2015.7063051},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FujiwaraWCLSWLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WuCCLLC14,
author = {Ching{-}Wei Wu and
Ming{-}Hung Chang and
Chia{-}Cheng Chen and
Robin Lee and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A configurable 2-in-1 {SRAM} compiler with constant-negative-level
write driver for low Vmin in 16nm Fin-FET {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {145--148},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008881},
doi = {10.1109/ASSCC.2014.7008881},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/WuCCLLC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChenCWLPLCLCLCW14,
author = {Yen{-}Huei Chen and
Wei{-}Min Chan and
Wei{-}Cheng Wu and
Hung{-}Jen Liao and
Kuo{-}Hua Pan and
Jhon{-}Jhy Liaw and
Tang{-}Hsuan Chung and
Quincy Li and
George H. Chang and
Chih{-}Yung Lin and
Mu{-}Chi Chiang and
Shien{-}Yang Wu and
Sreedhar Natarajan and
Jonathan Chang},
title = {13.5 {A} 16nm 128Mb {SRAM} in high-{\(\kappa\)} metal-gate FinFET
technology with write-assist circuitry for low-VMIN applications},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {238--239},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757416},
doi = {10.1109/ISSCC.2014.6757416},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChenCWLPLCLCLCW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/AdhamCLHH14,
author = {Saman Adham and
Jonathan Chang and
Hung{-}Jen Liao and
John Hung and
Ting{-}Hua Hsieh},
title = {The importance of DFX, a foundry perspective},
booktitle = {2014 International Test Conference, {ITC} 2014, Seattle, WA, USA,
October 20-23, 2014},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/TEST.2014.7035311},
doi = {10.1109/TEST.2014.7035311},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/AdhamCLHH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jnca/LiaoLLT13,
author = {Hung{-}Jen Liao and
Chun{-}Hung Richard Lin and
Ying{-}Chih Lin and
Kuang{-}Yuan Tung},
title = {Intrusion detection system: {A} comprehensive review},
journal = {J. Netw. Comput. Appl.},
volume = {36},
number = {1},
pages = {16--24},
year = {2013},
url = {https://doi.org/10.1016/j.jnca.2012.09.004},
doi = {10.1016/J.JNCA.2012.09.004},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jnca/LiaoLLT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangSLWLKLLCY13,
author = {Meng{-}Fan Chang and
Shin{-}Jang Shen and
Chia{-}Chi Liu and
Che{-}Wei Wu and
Yu{-}Fan Lin and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Hung{-}Jen Liao and
Yu{-}Der Chih and
Hiroyuki Yamauchi},
title = {An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier
for Small-Cell-Current Nonvolatile Memory},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {3},
pages = {864--877},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2235013},
doi = {10.1109/JSSC.2012.2235013},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangSLWLKLLCY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCCLLCNLWLWCCC13,
author = {Jonathan Chang and
Yen{-}Huei Chen and
Hank Cheng and
Wei{-}Min Chan and
Hung{-}Jen Liao and
Quincy Li and
Stanley Chang and
Sreedhar Natarajan and
Robin Lee and
Ping{-}Wei Wang and
Shyue{-}Shyh Lin and
Chung{-}Cheng Wu and
Kuan{-}Lun Cheng and
Min Cao and
George H. Chang},
title = {A 20nm 112Mb {SRAM} in High-{\cyrchar\cyrk} metal-gate with assist
circuitry for low-leakage and low-VMIN applications},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {316--317},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487750},
doi = {10.1109/ISSCC.2013.6487750},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangCCCLLCNLWLWCCC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCLCSLWCY12,
author = {Yen{-}Huei Chen and
Shao{-}Yu Chou and
Quincy Li and
Wei{-}Min Chan and
Dar Sun and
Hung{-}Jen Liao and
Ping Wang and
Meng{-}Fan Chang and
Hiroyuki Yamauchi},
title = {Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset
Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance
Margin in a 40 nm Fully Functional Embedded {SRAM}},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {4},
pages = {969--980},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2185180},
doi = {10.1109/JSSC.2012.2185180},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChenCLCSLWCY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WuCCCCLCCWY11,
author = {Jui{-}Jen Wu and
Yen{-}Hui Chen and
Meng{-}Fan Chang and
Po{-}Wei Chou and
Chien{-}Yuan Chen and
Hung{-}Jen Liao and
Ming{-}Bin Chen and
Yuan{-}Hua Chu and
Wen{-}Chin Wu and
Hiroyuki Yamauchi},
title = {A Large Sigma {V} \({}_{\mbox{TH}}\) /VDD Tolerant Zigzag 8T {SRAM}
With Area-Efficient Decoupled Differential Sensing and Fast Write-Back
Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {4},
pages = {815--827},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2109440},
doi = {10.1109/JSSC.2011.2109440},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/WuCCCCLCCWY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangSLWLWHLKLLCY11,
author = {Meng{-}Fan Chang and
Shin{-}Jang Shen and
Chia{-}Chi Liu and
Che{-}Wei Wu and
Yu{-}Fan Lin and
Shang{-}Chi Wu and
Chia{-}En Huang and
Han{-}Chao Lai and
Ya{-}Chin King and
Chorng{-}Jung Lin and
Hung{-}Jen Liao and
Yu{-}Der Chih and
Hiroyuki Yamauchi},
title = {An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current
nonvolatile memory},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {206--208},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746284},
doi = {10.1109/ISSCC.2011.5746284},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangSLWLWHLKLLCY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChangWCCCLLY10,
author = {Meng{-}Fan Chang and
Jui{-}Jen Wu and
Kuang{-}Ting Chen and
Yung{-}Chi Chen and
Yen{-}Hui Chen and
Robin Lee and
Hung{-}Jen Liao and
Hiroyuki Yamauchi},
title = {A Differential Data-Aware Power-Supplied {(D} \({}^{\mbox{2}}\) {AP)}
8T {SRAM} Cell With Expanded Write/Read Stabilities for Lower VDDmin
Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {6},
pages = {1234--1245},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2048496},
doi = {10.1109/JSSC.2010.2048496},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChangWCCCLLY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCCPWLLY09,
author = {Yen{-}Huei Chen and
Gary Chan and
Shao{-}Yu Chou and
Hsien{-}Yu Pan and
Jui{-}Jen Wu and
Robin Lee and
Hung{-}Jen Liao and
Hiroyuki Yamauchi},
title = {A 0.6 {V} Dual-Rail Compiler {SRAM} Design on 45 nm {CMOS} Technology
With Adaptive {SRAM} Power for Lower VDD{\_}min VLSIs},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {4},
pages = {1209--1215},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2014208},
doi = {10.1109/JSSC.2009.2014208},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChenCCPWLLY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/WangLYCLLLCH07,
author = {D. P. Wang and
Hung{-}Jen Liao and
Hiroyuki Yamauchi and
Y. H. Chen and
Y. L. Lin and
S. H. Lin and
D. C. Liu and
Huan{-}Cheng Chang and
W. Hwang},
title = {A 45nm dual-port {SRAM} with write and read capability enhancement
at low voltage},
booktitle = {2007 {IEEE} International {SOC} Conference, Tampere, Finland, November
19-21, 2007},
pages = {211--214},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/SOCC.2007.4545460},
doi = {10.1109/SOCC.2007.4545460},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/socc/WangLYCLLLCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/KwaiCLCC00,
author = {Ding{-}Ming Kwai and
Hung{-}Wen Chang and
Hung{-}Jen Liao and
Ching{-}Hua Chiao and
Yung{-}Fa Chou},
title = {etection of {SRAM} cell stability by lowering array supply voltage},
booktitle = {9th Asian Test Symposium {(ATS} 2000), 4-6 December 2000, Taipei,
Taiwan},
pages = {268--273},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ATS.2000.893636},
doi = {10.1109/ATS.2000.893636},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/KwaiCLCC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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