BibTeX records: Po-Hao Lee

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@inproceedings{DBLP:conf/isscc/LeeLSLCLCLCKCWWWCWCC23,
  author       = {Po{-}Hao Lee and
                  Chia{-}Fu Lee and
                  Yi{-}Chun Shih and
                  Hon{-}Jarn Lin and
                  Yen{-}An Chang and
                  Cheng{-}Han Lu and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Chung{-}Chieh Chen and
                  Cheng{-}Hsiung Kuo and
                  Tan{-}Li Chou and
                  Chia{-}Yu Wang and
                  J. J. Wu and
                  Roger Wang and
                  Harry Chuang and
                  Yih Wang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {A 16nm 32Mb Embedded {STT-MRAM} with a 6ns Read-Access Time, a 1M-Cycle
                  Write Endurance, 20-Year Retention at 150{\textdegree}C and {MTJ-OTP}
                  Solutions for Magnetic Immunity},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
                  San Francisco, CA, USA, February 19-23, 2023},
  pages        = {494--495},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/ISSCC42615.2023.10067837},
  doi          = {10.1109/ISSCC42615.2023.10067837},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeLSLCLCLCKCWWWCWCC23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChihLFSLNCLLMZS21,
  author       = {Yu{-}Der Chih and
                  Po{-}Hao Lee and
                  Hidehiro Fujiwara and
                  Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Rawan Naous and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Cheng{-}Han Lu and
                  Haruki Mori and
                  Wei{-}Cheng Zhao and
                  Dar Sun and
                  Mahmut E. Sinangil and
                  Yen{-}Huei Chen and
                  Tan{-}Li Chou and
                  Kerem Akarvardar and
                  Hung{-}Jen Liao and
                  Yih Wang and
                  Meng{-}Fan Chang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {An 89TOPS/W and 16.3TOPS/mm\({}^{\mbox{2}}\) All-Digital SRAM-Based
                  Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning
                  Edge Applications},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {252--254},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9365766},
  doi          = {10.1109/ISSCC42613.2021.9365766},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChihLFSLNCLLMZS21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChihSLCLLCLSSCC20,
  author       = {Yu{-}Der Chih and
                  Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Meng{-}Chun Shih and
                  Kuei{-}Hung Shen and
                  Harry Chuang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {13.3 {A} 22nm 32Mb Embedded {STT-MRAM} with 10ns Read Speed, 1M Cycle
                  Write Endurance, 10 Years Retention at 150{\textdegree}C and High
                  Immunity to Magnetic Field Interference},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {222--224},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062955},
  doi          = {10.1109/ISSCC19947.2020.9062955},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChihSLCLLCLSSCC20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShihLCLLCLYYCCC19,
  author       = {Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Ku{-}Feng Lin and
                  Ta{-}Ching Yeh and
                  Hung{-}Chang Yu and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM
                  With Hybrid-Resistance Reference, Sub- {\textdollar}{\textbackslash}mu{\textdollar}
                  {A} Sensing Resolution, and 17.5-nS Read Access Time},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {4},
  pages        = {1029--1038},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2018.2889106},
  doi          = {10.1109/JSSC.2018.2889106},
  timestamp    = {Wed, 07 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShihLCLLCLYYCCC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/ShihLCLLCLYYCCC18,
  author       = {Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Ku{-}Feng Lin and
                  Ta{-}Ching Yeh and
                  Hung{-}Chang Yu and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with
                  Hybrid-Resistance Reference, Sub-{\(\mu\)}A Sensing Resolution, and
                  17.5NS Read Access Time},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {79--80},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502260},
  doi          = {10.1109/VLSIC.2018.8502260},
  timestamp    = {Wed, 07 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}