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ORCIDBibTeX records: Chang-Kyo Lee
@article{DBLP:journals/itiis/LeeLKLR23,
author = {Chang{-}Kyo Lee and
Dong Hyun Lee and
Junseok Kim and
Xiaoying Lei and
Seung Hyong Rhee},
title = {Q-Learning based Collision Avoidance for 802.11 Stations with Maximum
Requirements},
journal = {{KSII} Trans. Internet Inf. Syst.},
volume = {17},
number = {3},
pages = {1035--1048},
year = {2023},
url = {https://doi.org/10.3837/tiis.2023.03.019},
doi = {10.3837/TIIS.2023.03.019},
timestamp = {Tue, 25 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/itiis/LeeLKLR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LeeCHPJLJLKKKPL21,
author = {Chang{-}Kyo Lee and
Hyung{-}Joon Chi and
Jin{-}Seok Heo and
Junghwan Park and
Jin{-}Hun Jang and
Dongkeon Lee and
Jaehoon Jung and
Dong{-}Hun Lee and
Dae{-}Hyun Kim and
Kihan Kim and
Sang{-}Yun Kim and
Dukha Park and
Youngil Lim and
Geuntae Park and
Seungjun Lee and
Seungki Hong and
Dae{-}Hyun Kwon and
Isak Hwang and
Byongwook Na and
Kyungryun Kim and
Seouk{-}Kyu Choi and
Hye{-}In Choi and
Hangi{-}Jung and
Wonil Bae and
Jeong{-}Don Ihm and
Seung{-}Jun Bae and
Nam Sung Kim and
Jung{-}Bae Lee},
title = {An 8.5-Gb/s/Pin 12-Gb {LPDDR5} {SDRAM} With a Hybrid-Bank Architecture,
Low Power, and Speed-Boosting Techniques},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {1},
pages = {212--224},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3017775},
doi = {10.1109/JSSC.2020.3017775},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/LeeCHPJLJLKKKPL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HaLPKOSBPLLLMHP20,
author = {Kyung{-}Soo Ha and
Seungseob Lee and
Youn{-}Sik Park and
Hyuck{-}Joon Kwon and
Tae{-}Young Oh and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Kwang{-}Il Park and
Jung{-}Bae Lee and
Chang{-}Kyo Lee and
Dongkeon Lee and
Daesik Moon and
Hyong{-}Ryol Hwang and
Dukha Park and
Young{-}Hwa Kim and
Young Hoon Son and
Byongwook Na},
title = {A 7.5 Gb/s/pin 8-Gb {LPDDR5} {SDRAM} With Various High-Speed and Low-Power
Techniques},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {1},
pages = {157--166},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2938396},
doi = {10.1109/JSSC.2019.2938396},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HaLPKOSBPLLLMHP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/LeeKKCL20,
author = {Chang{-}Kyo Lee and
Seong{-}Hoon Kee and
Jun Won Kang and
Byong{-}Jeong Choi and
Jin Woo Lee},
title = {Interpretation of Impact-Echo Testing Data from a Fire-Damaged Reinforced
Concrete Slab Using a Discrete Layered Concrete Damage Model},
journal = {Sensors},
volume = {20},
number = {20},
pages = {5838},
year = {2020},
url = {https://doi.org/10.3390/s20205838},
doi = {10.3390/S20205838},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/LeeKKCL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChiLPHJLKPKKPCL20,
author = {Hyung{-}Joon Chi and
Chang{-}Kyo Lee and
Junghwan Park and
Jin{-}Seok Heo and
Jaehoon Jung and
Dongkeon Lee and
Dae{-}Hyun Kim and
Dukha Park and
Kihan Kim and
Sang{-}Yun Kim and
Jinsol Park and
Hyunyoon Cho and
Sukhyun Lim and
YeonKyu Choi and
Youngil Lim and
Daesik Moon and
Geuntae Park and
Jin{-}Hun Jang and
Kyungho Lee and
Isak Hwang and
Cheol Kim and
Younghoon Son and
Gil{-}Young Kang and
Kiwon Park and
Seungjun Lee and
Su{-}Yeon Doo and
Chang{-}Ho Shin and
Byongwook Na and
Ji{-}Suk Kwon and
Kyung Ryun Kim and
Hye{-}In Choi and
Seouk{-}Kyu Choi and
Soobong Chang and
Wonil Bae and
Hyuck{-}Joon Kwon and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Kwang{-}Il Park and
Jung{-}Bae Lee},
title = {22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 {SDRAM} with a Hybrid-Bank Architecture
using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a
2nd generation 10nm {DRAM} Process},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {382--384},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062914},
doi = {10.1109/ISSCC19947.2020.9062914},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChiLPHJLKPKKPCL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/LeeR19,
author = {Chang{-}Kyo Lee and
Seung{-}Tak Ryu},
title = {Noise analysis of replica driving technique and its verification to
12-bit 200 MS/s pipelined {ADC}},
journal = {{IET} Circuits Devices Syst.},
volume = {13},
number = {8},
pages = {1277--1283},
year = {2019},
url = {https://doi.org/10.1049/iet-cds.2018.5308},
doi = {10.1049/IET-CDS.2018.5308},
timestamp = {Thu, 31 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/LeeR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HaLLMJHCPSPKLPC19,
author = {Kyung{-}Soo Ha and
Chang{-}Kyo Lee and
Dongkeon Lee and
Daesik Moon and
Jin{-}Hun Jang and
Hyong{-}Ryol Hwang and
Hyung{-}Joon Chi and
Junghwan Park and
Seungjun Shin and
Dukha Park and
Sang{-}Yun Kim and
Sukhyun Lim and
Kiwon Park and
YeonKyu Choi and
Young{-}Hwa Kim and
Younghoon Son and
Hyunyoon Cho and
Byongwook Na and
Hyo{-}Joo Ahn and
Seungseob Lee and
Seouk{-}Kyu Choi and
Youn{-}Sik Park and
Seok{-}Hun Hyun and
Soobong Chang and
Hyuck{-}Joon Kwon and
Jung{-}Hwan Choi and
Tae{-}Young Oh and
Young{-}Soo Sohn and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {A 7.5Gb/s/pin {LPDDR5} {SDRAM} With {WCK} Clocking and Non-Target
{ODT} for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep
Mode for Low Power},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {378--380},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662509},
doi = {10.1109/ISSCC.2019.8662509},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HaLLMJHCPSPKLPC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HeoKLLMKBYYKKPP19,
author = {Jin{-}Seok Heo and
Kihan Kim and
Dong{-}Hoon Lee and
Chang{-}Kyo Lee and
Daesik Moon and
Kiho Kim and
Jin{-}Hyeok Baek and
Sung{-}Woo Yoon and
Hui{-}Kap Yang and
Kyungryun Kim and
Youngjae Kim and
Bokgue Park and
Su{-}Jin Park and
Joung{-}Wook Moon and
Jae{-}Hyung Lee and
Yun{-}Sik Park and
Soobong Jang and
Seok{-}Hun Hyun and
Hyuck{-}Joon Kwon and
Jung{-}Hwan Choi and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Kwang{-}Il Park and
Jung{-}Bae Lee},
title = {A 5Gb/s/pin 16Gb {LPDDR4/4X} Reconfigurable {SDRAM} with Voltage-High
Keeper and a Prediction-based Fast-tracking {ZQ} Calibration},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {114},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778102},
doi = {10.23919/VLSIC.2019.8778102},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HeoKLLMKBYYKKPP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LeeLKHBCMLPLCCH18,
author = {Chang{-}Kyo Lee and
Junha Lee and
Kiho Kim and
Jin{-}Seok Heo and
Jin{-}Hyeok Baek and
Gil{-}Hoon Cha and
Daesik Moon and
Dong{-}Hun Lee and
Jong{-}Wook Park and
Seunseob Lee and
Si{-}Hyeong Cho and
Young{-}Ryeol Choi and
Kyung{-}Soo Ha and
Eunsung Seo and
Youn{-}Sik Park and
Seung{-}Jun Bae and
Indal Song and
Seok{-}Hun Hyun and
Hyuck{-}Joon Kwon and
Young{-}Soo Sohn and
Jung{-}Hwan Choi and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {Dual-Loop Two-Step {ZQ} Calibration for Dynamic Voltage-Frequency
Scaling in {LPDDR4} {SDRAM}},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {10},
pages = {2906--2916},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2018.2850937},
doi = {10.1109/JSSC.2018.2850937},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LeeLKHBCMLPLCCH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icufn/YoonLLCK18,
author = {Mahn{-}Suk Yoon and
Sung{-}Hun Lee and
Chang{-}Kyo Lee and
Soo{-}Hyun Cho and
Wan{-}Jin Ko},
title = {Performance Test of {LTE-R} Railway Wireless Communication at High-Speed
{(350} km/h) Environments},
booktitle = {Tenth International Conference on Ubiquitous and Future Networks,
{ICUFN} 2018, Prague, Czech Republic, July 3-6, 2018},
pages = {637--640},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICUFN.2018.8437021},
doi = {10.1109/ICUFN.2018.8437021},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/icufn/YoonLLCK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChunCHKKYKLKYSC18,
author = {Ki Chul Chun and
Yong{-}Gyu Chu and
Jin{-}Seok Heo and
Tae{-}Sung Kim and
Soohwan Kim and
Hui{-}Kap Yang and
Mi{-}Jo Kim and
Chang{-}Kyo Lee and
Ju{-}Hwan Kim and
Hyunchul Yoon and
Chang{-}Ho Shin and
Sang{-}uhn Cha and
Hyung{-}Jin Kim and
Young{-}Sik Kim and
Kyungryun Kim and
Young{-}Ju Kim and
Won{-}Jun Choi and
Dae{-}Sik Yim and
Inkyu Moon and
Young{-}Ju Kim and
Junha Lee and
Young Choi and
Yongmin Kwon and
Sung{-}Won Choi and
Jung{-}Wook Kim and
Yoon{-}Suk Park and
Woongdae Kang and
Jinil Chung and
Seunghyun Kim and
Yesin Ryu and
Seong{-}Jin Cho and
Hoon Shin and
Hangyun Jung and
Sanghyuk Kwon and
Kyuchang Kang and
Jongmyung Lee and
Yujung Song and
Youngjae Kim and
Eun{-}Ah Kim and
Kyung{-}Soo Ha and
Kyoung{-}Ho Kim and
Seok{-}Hun Hyun and
Seung{-}Bum Ko and
Jung{-}Hwan Choi and
Young{-}Soo Sohn and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {A 16Gb {LPDDR4X} {SDRAM} with an NBTI-tolerant circuit solution, an
{SWD} {PMOS} {GIDL} reduction technique, an adaptive gear-down scheme
and a metastable-free {DQS} aligner in a 10nm class {DRAM} process},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {206--208},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310256},
doi = {10.1109/ISSCC.2018.8310256},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChunCHKKYKLKYSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BaekLKMCHAKSKKK18,
author = {Jin{-}Hyeok Baek and
Chang{-}Kyo Lee and
Kiho Kim and
Daesik Moon and
Gil{-}Hoon Cha and
Jin{-}Seok Heo and
Min{-}Su Ahn and
Dong{-}Ju Kim and
Jae{-}Joon Song and
Seokhong Kwon and
Jongmin Kim and
Kyung{-}Soo Kim and
Jinoh Ahn and
Jeong{-}Sik Nam and
Byung{-}Cheol Kim and
Jeong{-}Hyeon Cho and
Jeonghoon Oh and
Seung{-}Jun Bae and
Indal Song and
Seok{-}Hun Hyun and
Ilgweon Kim and
Hyuck{-}Joon Kwon and
Young{-}Soo Sohn and
Jung{-}Hwan Choi and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up
Time Using 2-Step Charging Control and VOHCalibration in 20NM {DRAM}
Process},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {147--148},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502299},
doi = {10.1109/VLSIC.2018.8502299},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/BaekLKMCHAKSKKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LeeLKHCBMEKCSKP17,
author = {Chang{-}Kyo Lee and
Junha Lee and
Kiho Kim and
Jin{-}Seok Heo and
Gil{-}Hoon Cha and
Jin{-}Hyeok Baek and
Daesik Moon and
Yoon{-}Joo Eom and
Tae{-}Sung Kim and
Hyunyoon Cho and
Young Hoon Son and
Seonghwan Kim and
Jong{-}Wook Park and
Sewon Eom and
Si{-}Hyeong Cho and
Young{-}Ryeol Choi and
Seungseob Lee and
Kyoung{-}Soo Ha and
Youngseok Kim and
Bo{-}Tak Lim and
Dae{-}Hee Jung and
Eungsung Seo and
Kyoung{-}Ho Kim and
Yoon{-}Gyu Song and
Youn{-}Sik Park and
Tae{-}Young Oh and
Seung{-}Jun Bae and
Indal Song and
Seok{-}Hun Hyun and
Joon{-}Young Park and
Hyuck{-}Joon Kwon and
Young{-}Soo Sohn and
Jung{-}Hwan Choi and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {Dual-loop 2-step {ZQ} calibration for dedicated power supply voltage
in {LPDDR4} {SDRAM}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
Korea (South), November 6-8, 2017},
pages = {153--156},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASSCC.2017.8240239},
doi = {10.1109/ASSCC.2017.8240239},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/LeeLKHCBMEKCSKP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LeeEPLKKCCKBSPP17,
author = {Chang{-}Kyo Lee and
Yoon{-}Joo Eom and
Jin{-}Hee Park and
Junha Lee and
Hye{-}Ran Kim and
Kihan Kim and
Young Choi and
Ho{-}Jun Chang and
Jonghyuk Kim and
Jong{-}Min Bang and
Seungjun Shin and
Hanna Park and
Su{-}Jin Park and
Young{-}Ryeol Choi and
Hoon Lee and
Kyong{-}Ho Jeon and
Jae{-}Young Lee and
Hyo{-}Joo Ahn and
Kyoung{-}Ho Kim and
Jung{-}Sik Kim and
Soobong Chang and
Hyong{-}Ryol Hwang and
Duyeul Kim and
Yoon{-}Hwan Yoon and
Seok{-}Hun Hyun and
Joon{-}Young Park and
Yoon{-}Gyu Song and
Youn{-}Sik Park and
Hyuck{-}Joon Kwon and
Seung{-}Jun Bae and
Tae{-}Young Oh and
Indal Song and
Yong{-}Cheol Bae and
Jung{-}Hwan Choi and
Kwang{-}Il Park and
Seong{-}Jin Jang and
Gyo{-}Young Jin},
title = {23.2 {A} 5Gb/s/pin 8Gb {LPDDR4X} {SDRAM} with power-isolated {LVSTL}
and split-die architecture with 2-die {ZQ} calibration scheme},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {390--391},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870425},
doi = {10.1109/ISSCC.2017.7870425},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LeeEPLKKCCKBSPP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeAMKELKYCKPBB15,
author = {Chang{-}Kyo Lee and
Min{-}Su Ahn and
Daesik Moon and
Kiho Kim and
Yoon{-}Joo Eom and
Won{-}Young Lee and
Jongmin Kim and
Sanghyuk Yoon and
Baekkyu Choi and
Seokhong Kwon and
Joon{-}Young Park and
Seung{-}Jun Bae and
Yong{-}Cheol Bae and
Jung{-}Hwan Choi and
Seong{-}Jin Jang and
Gyo{-}Young Jin},
title = {A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for
mobile {DRAM} interface},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
2015},
pages = {182},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSIC.2015.7231254},
doi = {10.1109/VLSIC.2015.7231254},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeAMKELKYCKPBB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/OhLR14,
author = {Ghil{-}Geun Oh and
Chang{-}Kyo Lee and
Seung{-}Tak Ryu},
title = {A 10-Bit 40-MS/s Pipelined {ADC} With a Wide Range Operating Temperature
for {WAVE} Applications},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {61-II},
number = {1},
pages = {6--10},
year = {2014},
url = {https://doi.org/10.1109/TCSII.2013.2290910},
doi = {10.1109/TCSII.2013.2290910},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/OhLR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/3dica/YooCHLKSPK14,
author = {ByungIn Yoo and
Changkyu Choi and
Jae{-}Joon Han and
Chang{-}Kyo Lee and
Wonjun Kim and
Sungjoo Suh and
Dusik Park and
Junmo Kim},
editor = {Atilla Baskurt and
Robert Sitnik},
title = {Real-time 3D human pose recognition from reconstructed volume via
voxel classifiers},
booktitle = {Three-Dimensional Image Processing, Measurement (3DIPM), and Applications
2014, San Francisco, California, USA, February 5, 2014},
series = {{SPIE} Proceedings},
volume = {9013},
pages = {901306},
publisher = {{SPIE}},
year = {2014},
url = {https://doi.org/10.1117/12.2037152},
doi = {10.1117/12.2037152},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/3dica/YooCHLKSPK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LeeKKR13,
author = {Chang{-}Kyo Lee and
Wan Kim and
Hyun{-}Wook Kang and
Seung{-}Tak Ryu},
title = {A Replica-Driving Technique for High Performance {SC} Circuits and
Pipelined {ADC} Design},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {60-II},
number = {9},
pages = {557--561},
year = {2013},
url = {https://doi.org/10.1109/TCSII.2013.2268432},
doi = {10.1109/TCSII.2013.2268432},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LeeKKR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoLLR12,
author = {Sang{-}Hyun Cho and
Chang{-}Kyo Lee and
Sang{-}Gug Lee and
Seung{-}Tak Ryu},
title = {A Two-Channel Asynchronous {SAR} {ADC} With Metastable-Then-Set Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {4},
pages = {765--769},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2109743},
doi = {10.1109/TVLSI.2011.2109743},
timestamp = {Wed, 02 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoLLR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChoLKR11,
author = {Sang{-}Hyun Cho and
Chang{-}Kyo Lee and
Jong{-}Kee Kwon and
Seung{-}Tak Ryu},
title = {A 550-{\(\mu\)}W 10-b 40-MS/s {SAR} {ADC} With Multistep Addition-Only
Digital Error Correction},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {8},
pages = {1881--1892},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2151450},
doi = {10.1109/JSSC.2011.2151450},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChoLKR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ChoLKR10,
author = {Sang{-}Hyun Cho and
Chang{-}Kyo Lee and
Jong{-}Kee Kwon and
Seung{-}Tak Ryu},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {A 550{\(\mathrm{\mu}\)}W 10b 40MS/s {SAR} {ADC} with multistep addition-only
digital error correction},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617408},
doi = {10.1109/CICC.2010.5617408},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ChoLKR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SungCLKR09,
author = {Ba Sung and
Sang{-}Hyun Cho and
Chang{-}Kyo Lee and
Jong{-}In Kim and
Seung{-}Tak Ryu},
title = {A Time-interleaved Flash-SAR Architecture for High Speed {A/D} Conversion},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17
May 2009, Taipei, Taiwan},
pages = {984--987},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISCAS.2009.5117923},
doi = {10.1109/ISCAS.2009.5117923},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SungCLKR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChoLS07,
author = {Sang{-}Hyun Cho and
Chang{-}Kyo Lee and
Jong{-}In Song},
title = {Design of a 1-Volt and {\(\mathrm{\mu}\)}-power {SARADC} for Sensor
Network Application},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3852--3855},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.377879},
doi = {10.1109/ISCAS.2007.377879},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChoLS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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