BibTeX records: Jan Lappas

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@inproceedings{DBLP:conf/aspdac/LappasRWWN24,
  author       = {Jan Lappas and
                  Mohamed Amine Riahi and
                  Christian Weis and
                  Norbert Wehn and
                  Sani R. Nassif},
  title        = {Timing Analysis beyond Complementary {CMOS} Logic Styles},
  booktitle    = {Proceedings of the 29th Asia and South Pacific Design Automation Conference,
                  {ASPDAC} 2024, Incheon, Korea, January 22-25, 2024},
  pages        = {189--194},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASP-DAC58780.2024.10473842},
  doi          = {10.1109/ASP-DAC58780.2024.10473842},
  timestamp    = {Thu, 22 Aug 2024 15:31:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/LappasRWWN24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/esticas/SudarshanSLWSJG22,
  author       = {Chirag Sudarshan and
                  Taha Soliman and
                  Jan Lappas and
                  Christian Weis and
                  Mohammad Hassani Sadi and
                  Matthias Jung and
                  Andre Guntoro and
                  Norbert Wehn},
  title        = {A Weighted Current Summation Based Mixed Signal {DRAM-PIM} Architecture
                  for Deep Neural Network Inference},
  journal      = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
  volume       = {12},
  number       = {2},
  pages        = {367--380},
  year         = {2022},
  url          = {https://doi.org/10.1109/JETCAS.2022.3170235},
  doi          = {10.1109/JETCAS.2022.3170235},
  timestamp    = {Tue, 28 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/esticas/SudarshanSLWSJG22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/date/LappasCWXWNW22,
  author       = {Jan Lappas and
                  Andr{\'{e}} Lucas Chinazzo and
                  Christian Weis and
                  Chenyang Xia and
                  Zhihang Wu and
                  Leibin Ni and
                  Norbert Wehn},
  editor       = {Cristiana Bolchini and
                  Ingrid Verbauwhede and
                  Ioana Vatajelu},
  title        = {Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology
                  Node},
  booktitle    = {2022 Design, Automation {\&} Test in Europe Conference {\&}
                  Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
  pages        = {1083--1084},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.23919/DATE54114.2022.9774561},
  doi          = {10.23919/DATE54114.2022.9774561},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/date/LappasCWXWNW22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ets/ZhangLCWWNWT22,
  author       = {Zhe Zhang and
                  Jan Lappas and
                  Andr{\'{e}} Lucas Chinazzo and
                  Christian Weis and
                  Zhihang Wu and
                  Leibin Ni and
                  Norbert Wehn and
                  Mehdi B. Tahoori},
  title        = {Machine learning based soft error rate estimation of pass transistor
                  logic in high-speed communication},
  booktitle    = {{IEEE} European Test Symposium, {ETS} 2022, Barcelona, Spain, May
                  23-27, 2022},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ETS54262.2022.9810410},
  doi          = {10.1109/ETS54262.2022.9810410},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/ets/ZhangLCWWNWT22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icecsys/ChinazzoLWHWNW22,
  author       = {Andr{\'{e}} Lucas Chinazzo and
                  Jan Lappas and
                  Christian Weis and
                  Qinhui Huang and
                  Zhihang Wu and
                  Leibin Ni and
                  Norbert Wehn},
  title        = {Investigation of Pass Transistor Logic in a 12nm FinFET {CMOS} Technology},
  booktitle    = {29th {IEEE} International Conference on Electronics, Circuits and
                  Systems, {ICECS} 2022, Glasgow, United Kingdom, October 24-26, 2022},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ICECS202256217.2022.9970947},
  doi          = {10.1109/ICECS202256217.2022.9970947},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/icecsys/ChinazzoLWHWNW22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tcasII/SudarshanSJLWW21,
  author       = {Chirag Sudarshan and
                  Lukas Steiner and
                  Matthias Jung and
                  Jan Lappas and
                  Christian Weis and
                  Norbert Wehn},
  title        = {A Novel {DRAM} Architecture for Improved Bandwidth Utilization and
                  Latency Reduction Using Dual-Page Operation},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {68},
  number       = {5},
  pages        = {1615--1619},
  year         = {2021},
  url          = {https://doi.org/10.1109/TCSII.2021.3068007},
  doi          = {10.1109/TCSII.2021.3068007},
  timestamp    = {Sun, 16 May 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcasII/SudarshanSJLWW21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/RybalkinSWLWC21,
  author       = {Vladimir Rybalkin and
                  Chirag Sudarshan and
                  Christian Weis and
                  Jan Lappas and
                  Norbert Wehn and
                  Li Cheng},
  title        = {Correction to: Efficient Hardware Architectures for 1D- and {MD-LSTM}
                  Networks},
  journal      = {J. Signal Process. Syst.},
  volume       = {93},
  number       = {12},
  pages        = {1467},
  year         = {2021},
  url          = {https://doi.org/10.1007/s11265-021-01684-w},
  doi          = {10.1007/S11265-021-01684-W},
  timestamp    = {Sat, 25 Dec 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/RybalkinSWLWC21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/RybalkinSWLWC20,
  author       = {Vladimir Rybalkin and
                  Chirag Sudarshan and
                  Christian Weis and
                  Jan Lappas and
                  Norbert Wehn and
                  Li Cheng},
  title        = {Efficient Hardware Architectures for 1D- and {MD-LSTM} Networks},
  journal      = {J. Signal Process. Syst.},
  volume       = {92},
  number       = {11},
  pages        = {1219--1245},
  year         = {2020},
  url          = {https://doi.org/10.1007/s11265-020-01554-x},
  doi          = {10.1007/S11265-020-01554-X},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/RybalkinSWLWC20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/SudarshanLGRW0W19,
  author       = {Chirag Sudarshan and
                  Jan Lappas and
                  Muhammad Mohsin Ghaffar and
                  Vladimir Rybalkin and
                  Christian Weis and
                  Matthias Jung and
                  Norbert Wehn},
  title        = {An In-DRAM Neural Network Processing Engine},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
                  Sapporo, Japan, May 26-29, 2019},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISCAS.2019.8702458},
  doi          = {10.1109/ISCAS.2019.8702458},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/SudarshanLGRW0W19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/samos/SudarshanLWM0W19,
  author       = {Chirag Sudarshan and
                  Jan Lappas and
                  Christian Weis and
                  Deepak M. Mathew and
                  Matthias Jung and
                  Norbert Wehn},
  editor       = {Dionisios N. Pnevmatikatos and
                  Maxime Pelcat and
                  Matthias Jung},
  title        = {A Lean, Low Power, Low Latency {DRAM} Memory Controller for Transprecision
                  Computing},
  booktitle    = {Embedded Computer Systems: Architectures, Modeling, and Simulation
                  - 19th International Conference, {SAMOS} 2019, Samos, Greece, July
                  7-11, 2019, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {11733},
  pages        = {429--441},
  publisher    = {Springer},
  year         = {2019},
  url          = {https://doi.org/10.1007/978-3-030-27562-4\_31},
  doi          = {10.1007/978-3-030-27562-4\_31},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/samos/SudarshanLWM0W19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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