BibTeX records: Fang-Shi Lai

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@article{DBLP:journals/jssc/LaiL07,
  author       = {Fang{-}Shi Lai and
                  Chia{-}Fu Lee},
  title        = {On-Chip Voltage Down Converter to Improve {SRAM} Read/Write Margin
                  and Static Power for Sub-Nano {CMOS} Technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {42},
  number       = {9},
  pages        = {2061--2070},
  year         = {2007},
  url          = {https://doi.org/10.1109/JSSC.2007.903072},
  doi          = {10.1109/JSSC.2007.903072},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LaiL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/DiazFLWCCLLLCS05,
  author       = {Carlos H. Diaz and
                  K. H. Fung and
                  Ying{-}Keung Leung and
                  Chung{-}Cheng Wu and
                  Chih{-}Ping Chao and
                  G. J. Chern and
                  Wesley L. Lin and
                  Chien{-}Ming Lee and
                  Fang{-}Shi Lai and
                  Mi{-}Chang Chang and
                  Yuan{-}Chen Sun},
  title        = {Device trends and implications on circuit design in advanced {CMOS}
                  technologies},
  booktitle    = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
                  {CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
                  18-21, 2005},
  pages        = {675--679},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/CICC.2005.1568759},
  doi          = {10.1109/CICC.2005.1568759},
  timestamp    = {Fri, 06 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/DiazFLWCCLLLCS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LaiH97,
  author       = {Fang{-}Shi Lai and
                  Wei Hwang},
  title        = {Design and implementation of differential cascode voltage switch with
                  pass-gate {(DCVSPG)} logic for high-performance digital systems},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {32},
  number       = {4},
  pages        = {563--573},
  year         = {1997},
  url          = {https://doi.org/10.1109/4.563678},
  doi          = {10.1109/4.563678},
  timestamp    = {Thu, 07 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LaiH97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}