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ORCIDBibTeX records: Muhammad M. Khellah
@inproceedings{DBLP:conf/vlsit/AugustineMLVBMT23,
author = {Charles Augustine and
Pascal Meinerzhagen and
Wootaek Lim and
A. Veerabathini and
M. Bright and
K. Mojjada and
Jim Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop
Monitor Using Coupled Ring Oscillators in Intel 4 {CMOS}},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185254},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185254},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/AugustineMLVBMT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/IyerDIKCHKHK21,
author = {Ravi R. Iyer and
Vivek De and
Ramesh Illikkal and
David A. Koufaty and
Bhushan Chitlur and
Andrew Herdrich and
Muhammad M. Khellah and
Fatih Hamzaoglu and
Eric Karl},
title = {Advances in Microprocessor Cache Architectures Over the Last 25 Years},
journal = {{IEEE} Micro},
volume = {41},
number = {6},
pages = {78--88},
year = {2021},
url = {https://doi.org/10.1109/MM.2021.3114903},
doi = {10.1109/MM.2021.3114903},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/IyerDIKCHKHK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarCEMLTKTDK21,
author = {Saurabh Kumar and
Minki Cho and
Luke R. Everson and
Andres Malavasi and
Dan Lake and
Carlos Tokunaga and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De and
Chris H. Kim},
title = {A Back-Sampling Chain Technique for Accelerated Detection, Characterization,
and Reconstruction of Radiation-Induced Transient Pulses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2086--2097},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3119462},
doi = {10.1109/TVLSI.2021.3119462},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarCEMLTKTDK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AugustineAMORSM21,
author = {Charles Augustine and
A. Afzal and
U. Misgar and
Abdullah A. Owahid and
A. Raman and
K. Subramanian and
Feroze Merchant and
James W. Tschanz and
Muhammad M. Khellah},
title = {All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm
4-Core x86 {IP}},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492376},
doi = {10.23919/VLSICIRCUITS52068.2021.9492376},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AugustineAMORSM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BangCMMKTD20,
author = {Suyoung Bang and
Minki Cho and
Pascal Andreas Meinerzhagen and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An All-Digital, {\textdollar}V{\_}\{{\textbackslash}mathrm\{MAX\}\}{\textdollar}
-Compliant, Stable, and Scalable Distributed Charge Injection Scheme
in 10-nm {CMOS} for Fast and Local Mitigation of Voltage Droop},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {7},
pages = {1898--1908},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2020.2992892},
doi = {10.1109/JSSC.2020.2992892},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BangCMMKTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BangLAMKTD20,
author = {Suyoung Bang and
Wootaek Lim and
Charles Augustine and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {25.1 {A} Fully Synthesizable Distributed and Scalable All-Digital
{LDO} in 10nm {CMOS}},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {380--382},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063040},
doi = {10.1109/ISSCC19947.2020.9063040},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BangLAMKTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AugustinePMTKD20,
author = {Charles Augustine and
Somnath Paul and
Turbo Majumder and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162815},
doi = {10.1109/VLSICIRCUITS18222.2020.9162815},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AugustinePMTKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KulkarniMATTKD20,
author = {Jaydeep P. Kulkarni and
Andres Malavasi and
Charles Augustine and
Carlos Tokunaga and
Jim Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin,
Noise-Tolerant, High-Density, 1R1W 8T-Bitcell {SRAM} in 10nm FinFET
{CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162822},
doi = {10.1109/VLSICIRCUITS18222.2020.9162822},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KulkarniMATTKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PaulMAMUKKCYBOL20,
author = {Somnath Paul and
Turbo Majumder and
Charles Augustine and
Andres F. Malavasi and
S. Usirikayala and
Raghavan Kumar and
Jisna Kollikunnel and
S. Chhabra and
Satish Yada and
M. L. Barajas and
C. Ornelas and
Dan Lake and
Muhammad M. Khellah and
Jim Tschanz and
Vivek De},
title = {A 0.05pJ/Pixel 70fps {FHD} 1Meps Event-Driven Visual Data Processing
Unit},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162948},
doi = {10.1109/VLSICIRCUITS18222.2020.9162948},
timestamp = {Mon, 03 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/PaulMAMUKKCYBOL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MeinerzhagenTMV19,
author = {Pascal Andreas Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Xiang Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An Energy-Efficient Graphics Processor in 14-nm Tri-Gate {CMOS} Featuring
Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep,
and {\textdollar}\{V\}{\_}\{{\textbackslash}text\{MIN\}\}{\textdollar}
Optimization},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {1},
pages = {144--157},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2875097},
doi = {10.1109/JSSC.2018.2875097},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MeinerzhagenTMV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/BangCMMKTD19,
author = {Suyoung Bang and
Minki Cho and
Pascal Meinerzhagen and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection
Scheme for Fast Mitigation of Voltage Droop},
booktitle = {45th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2019,
Cracow, Poland, September 23-26, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ESSCIRC.2019.8902534},
doi = {10.1109/ESSCIRC.2019.8902534},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/BangCMMKTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/MeinerzhagenKMN19,
author = {Pascal Andreas Meinerzhagen and
Sandip Kundu and
Andres Malavasi and
Trang Nguyen and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Min-Delay Margin/Error Detection and Correction for Flip-Flops and
Pulsed Latches in 10-nm {CMOS}},
booktitle = {45th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2019,
Cracow, Poland, September 23-26, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ESSCIRC.2019.8902924},
doi = {10.1109/ESSCIRC.2019.8902924},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/MeinerzhagenKMN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BowmanKKSM18,
author = {Keith A. Bowman and
Muhammad M. Khellah and
Takashi Kono and
Joseph Shor and
Pui{-}In Mak},
title = {Introduction to the January Special Issue on the 2017 {IEEE} International
Solid-State Circuits Conference},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {3--7},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2780639},
doi = {10.1109/JSSC.2017.2780639},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BowmanKKSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BurdKN18,
author = {Thomas Burd and
Muhammad M. Khellah and
Byeong{-}Gyu Nam},
title = {Session 2 overview: Processors: Digital architectures and systems
subcommittee},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {32--33},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310169},
doi = {10.1109/ISSCC.2018.8310169},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BurdKN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MeinerzhagenTMV18,
author = {Pascal Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Chris Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An energy-efficient graphics processor featuring fine-grain {DVFS}
with integrated voltage regulators, execution-unit turbo, and retentive
sleep in 14nm tri-gate {CMOS}},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {38--40},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310172},
doi = {10.1109/ISSCC.2018.8310172},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MeinerzhagenTMV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChoKTAKRTKD17,
author = {Minki Cho and
Stephen T. Kim and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution
Core Using Adaptive Voltage Scaling and Dynamic Power Gating},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {50--63},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2601319},
doi = {10.1109/JSSC.2016.2601319},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChoKTAKRTKD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KhellahJ17,
author = {Muhammad M. Khellah and
Rajiv V. Joshi},
title = {Session 5 - Memory for emerging applications},
booktitle = {2017 {IEEE} Custom Integrated Circuits Conference, {CICC} 2017, Austin,
TX, USA, April 30 - May 3, 2017},
pages = {1},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/CICC.2017.7993690},
doi = {10.1109/CICC.2017.7993690},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KhellahJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/RaghunathanK16,
author = {Vijay Raghunathan and
Muhammad M. Khellah},
title = {Recap of the 2016 {IEEE/ACM} International Symposium on Low Power
Electronics and Design {(ISLPED} 2016)},
journal = {{IEEE} Des. Test},
volume = {33},
number = {6},
pages = {93--94},
year = {2016},
url = {https://doi.org/10.1109/MDAT.2016.2611493},
doi = {10.1109/MDAT.2016.2611493},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/RaghunathanK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimSMJ0TAKRTKD16,
author = {Stephen T. Kim and
Yi{-}Chun Shih and
Kaushik Mazumdar and
Rinkle Jain and
Joseph F. Ryan and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Enabling Wide Autonomous {DVFS} in a 22 nm Graphics Execution Core
Using a Digitally Controlled Fully Integrated Voltage Regulator},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {18--30},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2457920},
doi = {10.1109/JSSC.2015.2457920},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimSMJ0TAKRTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SheikPAKKCN16,
author = {Sadique Sheik and
Somnath Paul and
Charles Augustine and
Chinnikrishna Kothapalli and
Muhammad M. Khellah and
Gert Cauwenberghs and
Emre Neftci},
title = {Synaptic sampling in hardware spiking neural networks},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {2090--2093},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7538991},
doi = {10.1109/ISCAS.2016.7538991},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SheikPAKKCN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChoKTAKRTKD16,
author = {Minki Cho and
Stephen T. Kim and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution
core using adaptive voltage scaling and dynamic power gating},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {152--153},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417952},
doi = {10.1109/ISSCC.2016.7417952},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChoKTAKRTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChoTKTKD16,
author = {Minki Cho and
Carlos Tokunaga and
Stephen T. Kim and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Adaptive clocking with dynamic power gating for mitigating energy
efficiency {\&} performance impacts of fast voltage droop in a
22nm graphics execution core},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573529},
doi = {10.1109/VLSIC.2016.7573529},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChoTKTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ChoTKTD15,
author = {Minki Cho and
Carlos Tokunaga and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate
{CMOS}},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338419},
doi = {10.1109/CICC.2015.7338419},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ChoTKTD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/YahyaMTK15,
author = {Farah B. Yahya and
Mohammad M. Mansour and
James W. Tschanz and
Muhammad M. Khellah},
title = {Designing low-VTh {STT-RAM} for write energy reduction in scaled technologies},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {5--9},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085370},
doi = {10.1109/ISQED.2015.7085370},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/YahyaMTK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimSMJRTAKRTKD15,
author = {Stephen T. Kim and
Yi{-}Chun Shih and
Kaushik Mazumdar and
Rinkle Jain and
Joseph F. Ryan and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {8.6 Enabling wide autonomous {DVFS} in a 22nm graphics execution core
using a digitally controlled hybrid LDO/switched-capacitor {VR} with
fast droop mitigation},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062972},
doi = {10.1109/ISSCC.2015.7062972},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimSMJRTAKRTKD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/AmmarGSTTK15,
author = {Ahmed M. Ammar and
Rafik Guindi and
Ethan Shih and
Carlos Tokunaga and
Jim Tschanz and
Muhammad M. Khellah},
title = {A fully integrated charge sharing active decap scheme for power supply
noise suppression},
booktitle = {28th {IEEE} International System-on-Chip Conference, {SOCC} 2015,
Beijing, China, September 8-11, 2015},
pages = {374--379},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/SOCC.2015.7406986},
doi = {10.1109/SOCC.2015.7406986},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/AmmarGSTTK15.bib},
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author = {Rinkle Jain and
Bibiche M. Geuskens and
Stephen T. Kim and
Muhammad M. Khellah and
Jaydeep Kulkarni and
James W. Tschanz and
Vivek De},
title = {A 0.45-1 {V} Fully-Integrated Distributed Switched Capacitor {DC-DC}
Converter With High Density {MIM} Capacitor in 22 nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {4},
pages = {917--927},
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doi = {10.1109/JSSC.2013.2297402},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JainGKKKTD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Carlos Tokunaga and
Joseph F. Ryan and
Charles Augustine and
Jaydeep P. Kulkarni and
Yi{-}Chun Shih and
Stephen T. Kim and
Rinkle Jain and
Keith A. Bowman and
Arijit Raychowdhury and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {5.7 {A} graphics execution core in 22nm {CMOS} featuring adaptive
clocking, selective boosting and state-retentive sleep},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {108--109},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757359},
doi = {10.1109/ISSCC.2014.6757359},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TokunagaRAKSKJB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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editor = {Yuan Xie and
Tanay Karnik and
Muhammad M. Khellah and
Renu Mehra},
title = {International Symposium on Low Power Electronics and Design, ISLPED'14,
La Jolla, CA, {USA} - August 11 - 13, 2014},
publisher = {{ACM}},
year = {2014},
url = {http://dl.acm.org/citation.cfm?id=2627369},
isbn = {978-1-4503-2975-0},
timestamp = {Tue, 05 Aug 2014 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/2014.bib},
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author = {Minki Cho and
Muhammad M. Khellah and
Kwanyeob Chae and
Khondker Zakir Ahmed and
James W. Tschanz and
Saibal Mukhopadhyay},
title = {Characterization of Inverse Temperature Dependence in logic circuits},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330659},
doi = {10.1109/CICC.2012.6330659},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ChoKCATM12.bib},
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author = {Michael Nicolaidis and
Lorena Anghel and
Nacer{-}Eddine Zergainoh and
Yervant Zorian and
Tanay Karnik and
Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Carlos Tokunaga and
Arijit Raychowdhury and
Muhammad M. Khellah and
Jaydeep Kulkarni and
Vivek De and
Dimiter Avresky},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Design for test and reliability in ultimate {CMOS}},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {677--682},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176556},
doi = {10.1109/DATE.2012.6176556},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/NicolaidisAZZKBTLTRKKDA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Jaydeep Kulkarni and
Bibiche M. Geuskens and
Tanay Karnik and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Capacitive-coupling wordline boosting with self-induced {VCC} collapse
for write {VMIN} reduction in 22-nm 8T {SRAM}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {234--236},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176990},
doi = {10.1109/ISSCC.2012.6176990},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KulkarniGKKTD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Arijit Raychowdhury and
Jim Tschanz and
Keith A. Bowman and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek De},
title = {Error Detection and Correction in Microprocessor Core and Memory Due
to Fast Dynamic Voltage Droops},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {1},
number = {3},
pages = {208--217},
year = {2011},
url = {https://doi.org/10.1109/JETCAS.2011.2167070},
doi = {10.1109/JETCAS.2011.2167070},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/RaychowdhuryTBLAKGTWKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Arijit Raychowdhury and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek K. De},
title = {A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {194--208},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2089657},
doi = {10.1109/JSSC.2010.2089657},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BowmanTLAKRGTWKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Arijit Raychowdhury and
Bibiche M. Geuskens and
Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Tanay Karnik and
Muhammad M. Khellah and
Vivek K. De},
title = {Tunable Replica Bits for Dynamic Variation Tolerance in 8T {SRAM}
Arrays},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {4},
pages = {797--805},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2108141},
doi = {10.1109/JSSC.2011.2108141},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/RaychowdhuryGBTLKKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/BowmanTTRKGLAKD11,
author = {Keith A. Bowman and
Carlos Tokunaga and
James W. Tschanz and
Arijit Raychowdhury and
Muhammad M. Khellah and
Bibiche M. Geuskens and
Shih{-}Lien Lu and
Paolo A. Aseron and
Tanay Karnik and
Vivek K. De},
title = {All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug
and Adaptive Clock Control},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {58-I},
number = {9},
pages = {2017--2025},
year = {2011},
url = {https://doi.org/10.1109/TCSI.2011.2163893},
doi = {10.1109/TCSI.2011.2163893},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/BowmanTTRKGLAKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Dinesh Somasekhar and
Balaji Srinivasan and
Gunjan Pandya and
Fatih Hamzaoglu and
Muhammad M. Khellah and
Tanay Karnik and
Kevin Zhang},
title = {Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {4},
pages = {751--758},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2042253},
doi = {10.1109/JSSC.2010.2042253},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SomasekharSPHKKZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TschanzBKWGSRKTLKD10,
author = {James W. Tschanz and
Keith A. Bowman and
Muhammad M. Khellah and
Chris Wilkerson and
Bibiche M. Geuskens and
Dinesh Somasekhar and
Arijit Raychowdhury and
Jaydeep Kulkarni and
Carlos Tokunaga and
Shih{-}Lien Lu and
Tanay Karnik and
Vivek De},
title = {Resilient design in scaled {CMOS} for energy efficiency},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {625},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419812},
doi = {10.1109/ASPDAC.2010.5419812},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/TschanzBKWGSRKTLKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/BowmanTTRKGLAKD10,
author = {Keith A. Bowman and
Carlos Tokunaga and
James W. Tschanz and
Arijit Raychowdhury and
Muhammad M. Khellah and
Bibiche M. Geuskens and
Shih{-}Lien Lu and
Paolo A. Aseron and
Tanay Karnik and
Vivek De},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Dynamic variation monitor for measuring the impact of voltage droops
on microprocessor clock frequency},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617415},
doi = {10.1109/CICC.2010.5617415},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/BowmanTTRKGLAKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/GeuskensKKKD10,
author = {Bibiche M. Geuskens and
Muhammad M. Khellah and
Jaydeep Kulkarni and
Tanay Karnik and
Vivek De},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Opportunities for {PMOS} read and write ports in low voltage dual-port
8T bit cell arrays},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617441},
doi = {10.1109/CICC.2010.5617441},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/GeuskensKKKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/BowmanTLAKRGTWKD10,
author = {Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Arijit Raychowdhury and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek De},
editor = {Vojin G. Oklobdzija and
Barry Pangle and
Naehyuck Chang and
Naresh R. Shanbhag and
Chris H. Kim},
title = {Resilient microprocessor design for high performance {\&} energy
efficiency},
booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics
and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
pages = {355--356},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1840845.1840919},
doi = {10.1145/1840845.1840919},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/BowmanTLAKRGTWKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TschanzBLAKRGTWKD10,
author = {James W. Tschanz and
Keith A. Bowman and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Arijit Raychowdhury and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek De},
title = {A 45nm resilient and adaptive microprocessor core for dynamic variation
tolerance},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {282--283},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433922},
doi = {10.1109/ISSCC.2010.5433922},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TschanzBLAKRGTWKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RaychowdhuryGKTBKLDK10,
author = {Arijit Raychowdhury and
Bibiche M. Geuskens and
Jaydeep Kulkarni and
James W. Tschanz and
Keith A. Bowman and
Tanay Karnik and
Shih{-}Lien Lu and
Vivek De and
Muhammad M. Khellah},
title = {PVT-and-aging adaptive wordline boosting for 8T {SRAM} power reduction},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {352--353},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433815},
doi = {10.1109/ISSCC.2010.5433815},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/RaychowdhuryGKTBKLDK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Dinesh Somasekhar and
Yibin Ye and
Paolo A. Aseron and
Shih{-}Lien Lu and
Muhammad M. Khellah and
Jason Howard and
Gregory Ruhl and
Tanay Karnik and
Shekhar Borkar and
Vivek K. De and
Ali Keshavarzi},
title = {2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth
in a 65 nm Logic Process Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {174--185},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2007155},
doi = {10.1109/JSSC.2008.2007155},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SomasekharYALKH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KhellahKYSKBPHC09,
author = {Muhammad M. Khellah and
Nam{-}Sung Kim and
Yibin Ye and
Dinesh Somasekhar and
Tanay Karnik and
Nitin Borkar and
Gunjan Pandya and
Fatih Hamzaoglu and
Tom Coan and
Yih Wang and
Kevin Zhang and
Clair Webb and
Vivek De},
title = {Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays
With Diffusion-Notch-Free {(DNF)} 6T {SRAM} Cells and Dynamic Multi-Vcc
Circuits},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {4},
pages = {1199--1208},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2014015},
doi = {10.1109/JSSC.2009.2014015},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KhellahKYSKBPHC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/WilkersonGACKL09,
author = {Chris Wilkerson and
Hongliang Gao and
Alaa R. Alameldeen and
Zeshan Chishti and
Muhammad M. Khellah and
Shih{-}Lien Lu},
title = {Trading Off Cache Capacity for Low-Voltage Operation},
journal = {{IEEE} Micro},
volume = {29},
number = {1},
pages = {96--103},
year = {2009},
url = {https://doi.org/10.1109/MM.2009.20},
doi = {10.1109/MM.2009.20},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/WilkersonGACKL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {DiaaEldin Khalil and
Muhammad M. Khellah and
Nam{-}Sung Kim and
Yehea I. Ismail and
Tanay Karnik and
Vivek De},
title = {{SRAM} dynamic stability estimation using {MPFP} and its applications},
journal = {Microelectron. J.},
volume = {40},
number = {11},
pages = {1523--1530},
year = {2009},
url = {https://doi.org/10.1016/j.mejo.2009.01.015},
doi = {10.1016/J.MEJO.2009.01.015},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/KhalilKKIKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {{SSMCB:} Low-Power Variation-Tolerant Source-Synchronous Multicycle
Bus},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {2},
pages = {384--394},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2001805},
doi = {10.1109/TCSI.2008.2001805},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaIKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaIKTD09,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Serial-Link Bus: {A} Low-Power On-Chip Bus Architecture},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {9},
pages = {2020--2032},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2010155},
doi = {10.1109/TCSI.2008.2010155},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaIKTD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaKTYKBNID08,
author = {Maged Ghoneima and
Muhammad M. Khellah and
James W. Tschanz and
Yibin Ye and
Nasser A. Kurd and
Javed Barkatullah and
Srikanth Nimmagadda and
Yehea I. Ismail and
Vivek K. De},
title = {Skewed Repeater Bus: {A} Low-Power Scheme for On-Chip Buses},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {55-I},
number = {7},
pages = {1904--1910},
year = {2008},
url = {https://doi.org/10.1109/TCSI.2008.928527},
doi = {10.1109/TCSI.2008.928527},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaKTYKBNID08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {D. E. Khalil and
Muhammad M. Khellah and
Nam{-}Sung Kim and
Yehea I. Ismail and
Tanay Karnik and
Vivek K. De},
title = {Accurate Estimation of {SRAM} Dynamic Stability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {12},
pages = {1639--1647},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2001941},
doi = {10.1109/TVLSI.2008.2001941},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhalilKKIKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/WilkersonGACKL08,
author = {Chris Wilkerson and
Hongliang Gao and
Alaa R. Alameldeen and
Zeshan Chishti and
Muhammad M. Khellah and
Shih{-}Lien Lu},
title = {Trading off Cache Capacity for Reliability to Enable Low Voltage Operation},
booktitle = {35th International Symposium on Computer Architecture {(ISCA} 2008),
June 21-25, 2008, Beijing, China},
pages = {203--214},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISCA.2008.22},
doi = {10.1109/ISCA.2008.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/WilkersonGACKL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KhalilIKKD08,
author = {DiaaEldin Khalil and
Yehea I. Ismail and
Muhammad M. Khellah and
Tanay Karnik and
Vivek De},
title = {Analytical Model for the Propagation Delay of Through Silicon Vias},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {553--556},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479795},
doi = {10.1109/ISQED.2008.4479795},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KhalilIKKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SomasekharYALKHRKBDK08,
author = {Dinesh Somasekhar and
Yibin Ye and
Paolo A. Aseron and
Shih{-}Lien Lu and
Muhammad M. Khellah and
Jason Howard and
Gregory Ruhl and
Tanay Karnik and
Shekhar Y. Borkar and
Vivek De and
Ali Keshavarzi},
title = {2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm
Logic Process},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {274--275},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523163},
doi = {10.1109/ISSCC.2008.4523163},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SomasekharYALKHRKBDK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KhellahSYKHRSTB07,
author = {Muhammad M. Khellah and
Dinesh Somasekhar and
Yibin Ye and
Nam{-}Sung Kim and
Jason Howard and
Gregory Ruhl and
Murad Sunna and
James W. Tschanz and
Nitin Borkar and
Fatih Hamzaoglu and
Gunjan Pandya and
Ali Farhang and
Kevin Zhang and
Vivek De},
title = {A 256-Kb Dual-V\({}_{\mbox{CC}}\) {SRAM} Building Block in 65-nm {CMOS}
Process With Actively Clamped Sleep Transistor},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {1},
pages = {233--242},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2006.888357},
doi = {10.1109/JSSC.2006.888357},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KhellahSYKHRSTB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AziziKDN07,
author = {Navid Azizi and
Muhammad M. Khellah and
Vivek De and
Farid N. Najm},
title = {Variations-Aware Low-Power Design and Block Clustering With Voltage
Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {15},
number = {7},
pages = {746--757},
year = {2007},
url = {https://doi.org/10.1109/TVLSI.2007.899226},
doi = {10.1109/TVLSI.2007.899226},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AziziKDN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GhoneimaIKD07,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip
Interconnect Scheme},
journal = {{VLSI} Design},
volume = {2007},
pages = {95402:1--95402:12},
year = {2007},
url = {https://doi.org/10.1155/2007/95402},
doi = {10.1155/2007/95402},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GhoneimaIKD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoneimaIKTD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Formal derivation of optimal active shielding for low-power on-chip
buses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {821--836},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855974},
doi = {10.1109/TCAD.2005.855974},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoneimaIKTD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaIKTD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Reducing the Effective Coupling Capacitance in Buses Using Threshold
Voltage Adjustment Techniques},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {53-I},
number = {9},
pages = {1928--1933},
year = {2006},
url = {https://doi.org/10.1109/TCSI.2006.879054},
doi = {10.1109/TCSI.2006.879054},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaIKTD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GhoneimaIKD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {Reducing the data switching activity of serialized datastreams},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692760},
doi = {10.1109/ISCAS.2006.1692760},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GhoneimaIKD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YeKSD06,
author = {Yibin Ye and
Muhammad M. Khellah and
Dinesh Somasekhar and
Vivek De},
title = {Evaluation of differential vs. single-ended sensing and asymmetric
cells in 90 nm logic technology for on-chip caches},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692747},
doi = {10.1109/ISCAS.2006.1692747},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/YeKSD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/BowmanTKGID06,
author = {Keith A. Bowman and
James W. Tschanz and
Muhammad M. Khellah and
Maged Ghoneima and
Yehea I. Ismail and
Vivek De},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {Time-borrowing multi-cycle on-chip interconnects for delay variation
tolerance},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {79--84},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165592},
doi = {10.1145/1165573.1165592},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/BowmanTKGID06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GhoneimaIKD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {Reducing the Data Switching Activity on Serial Link Buses},
booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED}
2006), 27-29 March 2006, San Jose, CA, {USA}},
pages = {425--432},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISQED.2006.111},
doi = {10.1109/ISQED.2006.111},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/GhoneimaIKD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhellahKHRYTSBH06,
author = {Muhammad M. Khellah and
Nam{-}Sung Kim and
Jason Howard and
Gregory Ruhl and
Yibin Ye and
James W. Tschanz and
Dinesh Somasekhar and
Nitin Borkar and
Fatih Hamzaoglu and
Gunjan Pandya and
Ali Farhang and
Kevin Zhang and
Vivek De},
title = {A 4.2GHz 0.3mm2 256kb Dual-V\({}_{\mbox{cc}}\) {SRAM} Building Block
in 65nm {CMOS}},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {2572--2581},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696323},
doi = {10.1109/ISSCC.2006.1696323},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhellahKHRYTSBH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AziziKDN05,
author = {Navid Azizi and
Muhammad M. Khellah and
Vivek De and
Farid N. Najm},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Variations-aware low-power design with voltage scaling},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {529--534},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065717},
doi = {10.1145/1065579.1065717},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AziziKDN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GhoneimaIKTD05,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Serial-link bus: a low-power on-chip bus architecture},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {541--546},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560126},
doi = {10.1109/ICCAD.2005.1560126},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/GhoneimaIKTD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KhellahGTYKBNI05,
author = {Muhammad M. Khellah and
Maged Ghoneima and
James W. Tschanz and
Yibin Ye and
Nasser A. Kurd and
Javed Barkatullah and
Srikanth Nimmagadda and
Yehea I. Ismail},
title = {A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in
Microprocessors},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {253--257},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.14},
doi = {10.1109/ICCD.2005.14},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KhellahGTYKBNI05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/IsmailKGTYD05,
author = {Yehea I. Ismail and
Muhammad M. Khellah and
Maged Ghoneima and
James W. Tschanz and
Yibin Ye and
Vivek De},
title = {Skewing adjacent line repeaters to reduce the delay and energy dissipation
of on-chip buses},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {592--595},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464657},
doi = {10.1109/ISCAS.2005.1464657},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/IsmailKGTYD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YeKSFD03,
author = {Yibin Ye and
Muhammad M. Khellah and
Dinesh Somasekhar and
Ali Farhang and
Vivek De},
title = {A 6-GHz 16-kB {L1} cache in a 100-nm dual-V\({}_{\mbox{T}}\) technology
using a bitline leakage reduction {(BLR)} technique},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {5},
pages = {839--842},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.810057},
doi = {10.1109/JSSC.2003.810057},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YeKSFD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhellahE01,
author = {Muhammad M. Khellah and
Mohamed I. Elmasry},
title = {A low-power high-performance current-mode multiport {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {5},
pages = {590--598},
year = {2001},
url = {https://doi.org/10.1109/92.953493},
doi = {10.1109/92.953493},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhellahE01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FahimKE98,
author = {Amr M. Fahim and
Muhammad M. Khellah and
Mohamed I. Elmasry},
title = {A Low-Power High-Performance Embedded {SRAM} Macrocell},
booktitle = {8th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '98), 19-21 February
1998, Lafayette, LA, {USA}},
pages = {13--17},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/GLSV.1998.665192},
doi = {10.1109/GLSV.1998.665192},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FahimKE98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KhellahE98,
author = {Muhammad M. Khellah and
Mohamed I. Elmasry},
title = {Effective Capacitance Macro-Modelling for Architectural-Level Power
Estimation},
booktitle = {8th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '98), 19-21 February
1998, Lafayette, LA, {USA}},
pages = {414--419},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/GLSV.1998.665336},
doi = {10.1109/GLSV.1998.665336},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/KhellahE98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BrownKV96,
author = {Stephen Dean Brown and
Muhammad M. Khellah and
Zvonko G. Vranesic},
title = {Minimizing {FPGA} Interconnect Delays},
journal = {{IEEE} Des. Test Comput.},
volume = {13},
number = {4},
pages = {16--23},
year = {1996},
url = {https://doi.org/10.1109/54.544532},
doi = {10.1109/54.544532},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BrownKV96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BrownKL96,
author = {Stephen Dean Brown and
Muhammad M. Khellah and
Guy Lemieux},
title = {Segmented Routing for Speed-Performance and Routability in Field-Programmable
Gate Arrays},
journal = {{VLSI} Design},
volume = {4},
number = {4},
pages = {275--291},
year = {1996},
url = {https://doi.org/10.1155/1996/45983},
doi = {10.1155/1996/45983},
timestamp = {Tue, 06 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/BrownKL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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