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ORCIDBibTeX records: S. Kala
@article{DBLP:journals/ijes/MuneebSK23,
author = {M. A. Muneeb and
Nalesh S and
S. Kala},
title = {A physically unclonable function architecture with multiple responses
on {FPGA}},
journal = {Int. J. Embed. Syst.},
volume = {16},
number = {1},
pages = {67--74},
year = {2023},
url = {https://doi.org/10.1504/IJES.2023.134117},
doi = {10.1504/IJES.2023.134117},
timestamp = {Fri, 03 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijes/MuneebSK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/KalvacherlaGSK23,
author = {Abhinav Kalvacherla and
Rachana George and
Nalesh S and
S. Kala},
title = {Approximate {CNN} on {FPGA} Using Toom-Cook Multiplier},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2023,
Ahmedabad, India, December 18-20, 2023},
pages = {271--276},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/iSES58672.2023.00062},
doi = {10.1109/ISES58672.2023.00062},
timestamp = {Tue, 02 Apr 2024 12:53:25 +0200},
biburl = {https://dblp.org/rec/conf/ises/KalvacherlaGSK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GSK23,
author = {Noble G and
Nalesh S and
S. Kala},
title = {{MOSCON:} Modified Outer Product based Sparse Matrix-Matrix Multiplication
Accelerator with Configurable Tiles},
booktitle = {36th International Conference on {VLSI} Design and 2023 22nd International
Conference on Embedded Systems, {VLSID} 2023, Hyderabad, India, January
8-12, 2023},
pages = {264--269},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSID57277.2023.00061},
doi = {10.1109/VLSID57277.2023.00061},
timestamp = {Wed, 08 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GSK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/BajjuriSRS22,
author = {Vishnu Bajjuri and
Nalesh S and
Sree Ranjani Rajendran and
S. Kala},
title = {Adiabatic Physical Unclonable Function Using Cross-Coupled Pair},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2022,
Warangal, India, December 18-22, 2022},
pages = {278--282},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/iSES54909.2022.00063},
doi = {10.1109/ISES54909.2022.00063},
timestamp = {Wed, 08 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/BajjuriSRS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/MSS21,
author = {Mahesh M and
Nalesh S and
S. Kala},
editor = {Gang Qu and
Jinjun Xiong and
Danella Zhao and
Venki Muthukumar and
Md Farhadur Reza and
Ramalingam Sridhar},
title = {Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep
Neural Networks on {FPGA}},
booktitle = {34th {IEEE} International System-on-Chip Conference, {SOCC} 2021,
Las Vegas, NV, USA, September 14-17, 2021},
pages = {7--12},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SOCC52499.2021.9739346},
doi = {10.1109/SOCC52499.2021.9739346},
timestamp = {Wed, 08 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/socc/MSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/MahadurkarSK21,
author = {Mahesh Mahadurkar and
Nalesh Sivanandan and
S. Kala},
title = {Hardware Acceleration of SpMV Multiplier for Deep Learning},
booktitle = {25th International Symposium on {VLSI} Design and Test, {VDAT} 2021,
Surat, India, September 16-18, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VDAT53777.2021.9600988},
doi = {10.1109/VDAT53777.2021.9600988},
timestamp = {Fri, 19 Nov 2021 11:34:23 +0100},
biburl = {https://dblp.org/rec/conf/vdat/MahadurkarSK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/KalaMJS19,
author = {S. Kala and
Jimson Mathew and
Babita R. Jose and
Nalesh Sivanandan},
title = {Radix-4\({}^{\mbox{3}}\) based two-dimensional {FFT} architecture
with efficient data reordering scheme},
journal = {{IET} Comput. Digit. Tech.},
volume = {13},
number = {2},
pages = {78--86},
year = {2019},
url = {https://doi.org/10.1049/iet-cdt.2018.5075},
doi = {10.1049/IET-CDT.2018.5075},
timestamp = {Thu, 31 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cdt/KalaMJS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KalaJMS19,
author = {S. Kala and
Babita R. Jose and
Jimson Mathew and
Nalesh Sivanandan},
title = {High-Performance {CNN} Accelerator on {FPGA} Using Unified Winograd-GEMM
Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2816--2828},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2941250},
doi = {10.1109/TVLSI.2019.2941250},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KalaJMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/KalaJMS19,
author = {S. Kala and
Babita R. Jose and
Jimson Mathew and
Nalesh Sivanandan},
title = {Efficient Hardware Acceleration of Convolutional Neural Networks},
booktitle = {32nd {IEEE} International System-on-Chip Conference, {SOCC} 2019,
Singapore, September 3-6, 2019},
pages = {191--192},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SOCC46988.2019.1570573948},
doi = {10.1109/SOCC46988.2019.1570573948},
timestamp = {Tue, 19 May 2020 13:56:11 +0200},
biburl = {https://dblp.org/rec/conf/socc/KalaJMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KalaMJS19,
author = {S. Kala and
Jimson Mathew and
Babita R. Jose and
Nalesh Sivanandan},
title = {UniWiG: Unified Winograd-GEMM Architecture for Accelerating {CNN}
on FPGAs},
booktitle = {32nd International Conference on {VLSI} Design and 18th International
Conference on Embedded Systems, {VLSID} 2019, Delhi, India, January
5-9, 2019},
pages = {209--214},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSID.2019.00055},
doi = {10.1109/VLSID.2019.00055},
timestamp = {Mon, 14 Nov 2022 15:28:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KalaMJS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dtis/KalaSJMO18,
author = {S. Kala and
Nalesh Sivanandan and
Babita R. Jose and
Jimson Mathew and
Marco Ottavi},
title = {Two dimensional {FFT} architecture based on radix-4\({}^{\mbox{3}}\)
algorithm with efficient output reordering},
booktitle = {13th International Conference on Design {\&} Technology of Integrated
Systems In Nanoscale Era, {DTIS} 2018, Taormina, Italy, April 9-12,
2018},
pages = {1--2},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/DTIS.2018.8368562},
doi = {10.1109/DTIS.2018.8368562},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/dtis/KalaSJMO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/KalaPJS18,
author = {S. Kala and
Debdeep Paul and
Babita R. Jose and
Nalesh Sivanandan},
editor = {Bijoy Antony Jose and
Jimson Mathew},
title = {Design Space Exploration of Convolution Algorithms to Accelerate CNNs
on {FPGA}},
booktitle = {8th International Symposium on Embedded Computing and System Design,
{ISED} 2018, Cochin, India, December 13-15, 2018},
pages = {21--25},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISED.2018.8704043},
doi = {10.1109/ISED.2018.8704043},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ised/KalaPJS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/KalaJPM18,
author = {S. Kala and
Babita R. Jose and
Debdeep Paul and
Jimson Mathew},
editor = {S. Rajaram and
N. B. Balamurugan and
D. Gracia Nirmala Rani and
Virendra Singh},
title = {A Hardware Accelerator for Convolutional Neural Network Using Fast
Fourier Transform},
booktitle = {{VLSI} Design and Test - 22nd International Symposium, {VDAT} 2018,
Madurai, India, June 28-30, 2018, Revised Selected Papers},
series = {Communications in Computer and Information Science},
volume = {892},
pages = {28--36},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-981-13-5950-7\_3},
doi = {10.1007/978-981-13-5950-7\_3},
timestamp = {Wed, 04 May 2022 16:21:48 +0200},
biburl = {https://dblp.org/rec/conf/vdat/KalaJPM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/KalaNNN15,
author = {S. Kala and
Nalesh Sivanandan and
S. K. Nandy and
Ranjani Narayan},
title = {Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier
Transform Architecture},
journal = {J. Low Power Electron.},
volume = {11},
number = {3},
pages = {426--435},
year = {2015},
url = {https://doi.org/10.1166/jolpe.2015.1390},
doi = {10.1166/JOLPE.2015.1390},
timestamp = {Tue, 27 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/KalaNNN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/KalaSNN14,
author = {S. Kala and
Nalesh Sivanandan and
S. K. Nandy and
Ranjani Narayan},
title = {Energy Efficient, Scalable, and Dynamically Reconfigurable {FFT} Architecture
for {OFDM} Systems},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal,
Mangalore, India, December 15-17, 2014},
pages = {20--24},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISED.2014.12},
doi = {10.1109/ISED.2014.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/KalaSNN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KalaNMNN13,
author = {S. Kala and
Nalesh Sivanandan and
Arka Maity and
S. K. Nandy and
Ranjani Narayan},
title = {High throughput, low latency, memory optimized 64K point {FFT} architecture
using novel radix-4 butterfly unit},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {3034--3037},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572518},
doi = {10.1109/ISCAS.2013.6572518},
timestamp = {Tue, 27 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KalaNMNN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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