BibTeX records: Richen Jiang

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@inproceedings{DBLP:conf/ats/OzawaIJSTTSK17,
  author       = {Yuki Ozawa and
                  Takashi Ida and
                  Richen Jiang and
                  Shotaro Sakurai and
                  Seiya Takigami and
                  Nobukazu Tsukiji and
                  Ryoji Shiota and
                  Haruo Kobayashi},
  title        = {{SAR} {TDC} Architecture with Self-Calibration Employing Trigger Circuit},
  booktitle    = {26th {IEEE} Asian Test Symposium, {ATS} 2017, Taipei City, Taiwan,
                  November 27-30, 2017},
  pages        = {94--99},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/ATS.2017.29},
  doi          = {10.1109/ATS.2017.29},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ats/OzawaIJSTTSK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ispacs/OzawaISJTKS17,
  author       = {Yuki Ozawa and
                  Takashi Ida and
                  Shotaro Sakurai and
                  Richen Jiang and
                  Rino Takahashi and
                  Haruo Kobayashi and
                  Ryoji Shiota},
  title        = {{SAR} {TDC} architecture for one-shot timing measurement with full
                  digital implementation},
  booktitle    = {2017 International Symposium on Intelligent Signal Processing and
                  Communication Systems, {ISPACS} 2017, Xiamen, China, November 6-9,
                  2017},
  pages        = {462--467},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISPACS.2017.8266523},
  doi          = {10.1109/ISPACS.2017.8266523},
  timestamp    = {Thu, 06 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispacs/OzawaISJTKS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ispacs/JiangASYTOTKS17,
  author       = {Richen Jiang and
                  Gopal Adhikari and
                  Yifei Sun and
                  Dan Yao and
                  Rino Takahashi and
                  Yuki Ozawa and
                  Nobukazu Tsukiji and
                  Haruo Kobayashi and
                  Ryoji Shiota},
  title        = {Gray-code input {DAC} architecture for clean signal generation},
  booktitle    = {2017 International Symposium on Intelligent Signal Processing and
                  Communication Systems, {ISPACS} 2017, Xiamen, China, November 6-9,
                  2017},
  pages        = {669--674},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISPACS.2017.8266561},
  doi          = {10.1109/ISPACS.2017.8266561},
  timestamp    = {Thu, 28 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispacs/JiangASYTOTKS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}