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BibTeX records: Seyed Borna Ehsani
@inproceedings{DBLP:conf/aips/BakhshalipourQG23, author = {Mohammad Bakhshalipour and Mohamad Qadri and Dominic Guri and Seyed Borna Ehsani and Maxim Likhachev and Phillip B. Gibbons}, editor = {Sven Koenig and Roni Stern and Mauro Vallati}, title = {Runahead A*: Speculative Parallelism for A* with Slow Expansions}, booktitle = {Proceedings of the Thirty-Third International Conference on Automated Planning and Scheduling, July 8-13, 2023, Prague, Czech Republic}, pages = {31--41}, publisher = {{AAAI} Press}, year = {2023}, url = {https://doi.org/10.1609/icaps.v33i1.27176}, doi = {10.1609/ICAPS.V33I1.27176}, timestamp = {Wed, 20 Sep 2023 11:58:30 +0200}, biburl = {https://dblp.org/rec/conf/aips/BakhshalipourQG23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChengPZRWVERJIR22, author = {Lin Cheng and Peitian Pan and Zhongyuan Zhao and Krithik Ranjan and Jack Weber and Bandhav Veluri and Seyed Borna Ehsani and Max Ruttenberg and Dai Cheol Jung and Preslav Ivanov and Dustin Richmond and Michael B. Taylor and Zhiru Zhang and Christopher Batten}, title = {A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {41}, number = {6}, pages = {1620--1635}, year = {2022}, url = {https://doi.org/10.1109/TCAD.2021.3103825}, doi = {10.1109/TCAD.2021.3103825}, timestamp = {Mon, 28 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChengPZRWVERJIR22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/BakhshalipourEQ22, author = {Mohammad Bakhshalipour and Seyed Borna Ehsani and Mohamad Qadri and Dominic Guri and Maxim Likhachev and Phillip B. Gibbons}, editor = {Valentina Salapura and Mohamed Zahran and Fred Chong and Lingjia Tang}, title = {{RACOD:} algorithm/hardware co-design for mobile robot path planning}, booktitle = {{ISCA} '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18 - 22, 2022}, pages = {597--609}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3470496.3527383}, doi = {10.1145/3470496.3527383}, timestamp = {Wed, 01 Jun 2022 14:28:13 +0200}, biburl = {https://dblp.org/rec/conf/isca/BakhshalipourEQ22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2010-09330, author = {Mohammad Sadrosadati and Amirhossein Mirhosseini and Ali Hajiabadi and Seyed Borna Ehsani and Hajar Falahati and Hamid Sarbazi{-}Azad and Mario Drumond and Babak Falsafi and Rachata Ausavarungnirun and Onur Mutlu}, title = {Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent {GPU} Register Files via Software/Hardware Cooperation}, journal = {CoRR}, volume = {abs/2010.09330}, year = {2020}, url = {https://arxiv.org/abs/2010.09330}, eprinttype = {arXiv}, eprint = {2010.09330}, timestamp = {Wed, 21 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2010-09330.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/taco/SadrosadatiEFAT19, author = {Mohammad Sadrosadati and Seyed Borna Ehsani and Hajar Falahati and Rachata Ausavarungnirun and Arash Tavakkol and Mojtaba Abaee and Lois Orosa and Yaohua Wang and Hamid Sarbazi{-}Azad and Onur Mutlu}, title = {{ITAP:} Idle-Time-Aware Power Management for {GPU} Execution Units}, journal = {{ACM} Trans. Archit. Code Optim.}, volume = {16}, number = {1}, pages = {3:1--3:26}, year = {2019}, url = {https://doi.org/10.1145/3291606}, doi = {10.1145/3291606}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/taco/SadrosadatiEFAT19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/AmrouchEGH19, author = {Hussam Amrouch and Seyed Borna Ehsani and Andreas Gerstlauer and J{\"{o}}rg Henkel}, title = {On the Efficiency of Voltage Overscaling under Temperature and Aging Effects}, journal = {{IEEE} Trans. Computers}, volume = {68}, number = {11}, pages = {1647--1662}, year = {2019}, url = {https://doi.org/10.1109/TC.2019.2916869}, doi = {10.1109/TC.2019.2916869}, timestamp = {Thu, 07 Nov 2019 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tc/AmrouchEGH19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tocs/SadrosadatiMHEF21, author = {Mohammad Sadrosadati and Amirhossein Mirhosseini and Ali Hajiabadi and Seyed Borna Ehsani and Hajar Falahati and Hamid Sarbazi{-}Azad and Mario Drumond and Babak Falsafi and Rachata Ausavarungnirun and Onur Mutlu}, title = {Highly Concurrent Latency-tolerant Register Files for GPUs}, journal = {{ACM} Trans. Comput. Syst.}, volume = {37}, number = {1-4}, pages = {1:1--1:36}, year = {2019}, url = {https://doi.org/10.1145/3419973}, doi = {10.1145/3419973}, timestamp = {Fri, 18 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tocs/SadrosadatiMHEF21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asplos/SadrosadatiMESD18, author = {Mohammad Sadrosadati and Amirhossein Mirhosseini and Seyed Borna Ehsani and Hamid Sarbazi{-}Azad and Mario Drumond and Babak Falsafi and Rachata Ausavarungnirun and Onur Mutlu}, editor = {Xipeng Shen and James Tuck and Ricardo Bianchini and Vivek Sarkar}, title = {{LTRF:} Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching}, booktitle = {Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, {ASPLOS} 2018, Williamsburg, VA, USA, March 24-28, 2018}, pages = {489--502}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3173162.3173211}, doi = {10.1145/3173162.3173211}, timestamp = {Tue, 23 Jan 2024 20:31:22 +0100}, biburl = {https://dblp.org/rec/conf/asplos/SadrosadatiMESD18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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