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ORCIDBibTeX records: Daniel M. Dreps
@inproceedings{DBLP:conf/isscc/RaoGFMBD0LSWSK22,
author = {Rahul M. Rao and
Christopher J. Gonzalez and
Eric Fluhr and
Abraham Mathews and
Andrew Bianchi and
Daniel Dreps and
David Wolpert and
Eric Lai and
Gerald Strevig and
Glen A. Wiedemeier and
Philipp Salz and
Ryan Kruse},
title = {POWER10{\texttrademark}: {A} 16-Core {SMT8} Server Processor With
2TB/s Off-Chip Bandwidth in 7nm Technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {48--50},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731594},
doi = {10.1109/ISSCC42614.2022.9731594},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/RaoGFMBD0LSWSK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YouWMSEYPNOBSZF20,
author = {Yang You and
Glen A. Wiedemeier and
Chad Marquart and
Chris Steffen and
Erik English and
Dereje Yilma and
Thomas Pham and
Venkat Nammi and
Jeffrey Okyere and
Nathan Blanchard and
Akil Sutton and
Ze Zhang and
David Friend and
Diego Barba and
Tyler Bohlke and
Michael Spear and
Vikram Raj and
James Crugnale and
Daniel Dreps and
Pier Andrea Francese and
Marcel A. Kossel and
Thomas Morf},
title = {A 25{\texttimes}50Gb/s 2.22pJ/b {NRZ} {RX} with Dual-Bank and 3-Tap
Speculative {DFE} for Microprocessor Application in 7nm FinFET {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162821},
doi = {10.1109/VLSICIRCUITS18222.2020.9162821},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/YouWMSEYPNOBSZF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KahleMD19,
author = {James A. Kahle and
Jaime Moreno and
Daniel Dreps},
title = {Summit and Sierra: Designing {AI/HPC} Supercomputers},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {42--43},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662426},
doi = {10.1109/ISSCC.2019.8662426},
timestamp = {Mon, 16 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KahleMD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/StuecheliSIADBW18,
author = {Jeffrey Stuecheli and
William J. Starke and
John D. Irish and
L. Baba Arimilli and
Daniel M. Dreps and
Bart Blaner and
Curt Wollbrink and
Brian Allison},
title = {{IBM} {POWER9} opens up a new era of acceleration enablement: OpenCAPI},
journal = {{IBM} J. Res. Dev.},
volume = {62},
number = {4/5},
pages = {8:1--8:8},
year = {2018},
url = {https://doi.org/10.1147/JRD.2018.2856978},
doi = {10.1147/JRD.2018.2856978},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ibmrd/StuecheliSIADBW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/ChunBCODHNBE18,
author = {Sungjun Chun and
Wiren Dale Becker and
Jon Casey and
Steve Ostrander and
Daniel Dreps and
Jose Ale Hejase and
Ryan Nett and
Brian Beaman and
Jason R. Eagle},
title = {{IBM} {POWER9} package technology and design},
journal = {{IBM} J. Res. Dev.},
volume = {62},
number = {4/5},
pages = {12:1--12:10},
year = {2018},
url = {https://doi.org/10.1147/JRD.2018.2847178},
doi = {10.1147/JRD.2018.2847178},
timestamp = {Thu, 23 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ibmrd/ChunBCODHNBE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/GonzalezFFRDSRH18,
author = {Christopher J. Gonzalez and
Michael S. Floyd and
Eric Fluhr and
Phillip J. Restle and
Daniel Dreps and
Michael A. Sperling and
Rahul M. Rao and
David Hogenmiller and
Christos Vezyrtzis and
Pierce Chuang and
Daniel Lewis and
Ricardo Escobar and
Vinod Ramadurai and
Ryan Kruse and
Juergen Pille and
Ryan Nett and
Pawel Owczarczyk and
Joshua Friedrich and
Jose Paredes and
Timothy Diemoz and
Md. Saiful Islam and
Donald W. Plass and
Paul Muench},
title = {The 24-Core {POWER9} Processor With Adaptive Clocking, 25-Gb/s Accelerator
Links, and 16-Gb/s PCIe Gen4},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {91--101},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2748623},
doi = {10.1109/JSSC.2017.2748623},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/GonzalezFFRDSRH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GonzalezFDHRPFS17,
author = {Christopher J. Gonzalez and
Eric Fluhr and
Daniel Dreps and
David Hogenmiller and
Rahul M. Rao and
Jose Paredes and
Michael S. Floyd and
Michael A. Sperling and
Ryan Kruse and
Vinod Ramadurai and
Ryan Nett and
Md. Saiful Islam and
Juergen Pille and
Donald W. Plass},
title = {3.1 POWER9{\texttrademark}: {A} processor family optimized for cognitive
computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {50--51},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870255},
doi = {10.1109/ISSCC.2017.7870255},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/GonzalezFDHRPFS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/SukhwaniRHKMDSL17,
author = {Bharat Sukhwani and
Thomas Roewer and
Charles L. Haymes and
Kyu{-}Hyoun Kim and
Adam J. McPadden and
Daniel M. Dreps and
Dean Sanner and
Jan van Lunteren and
Sameh W. Asaad},
editor = {Hillery C. Hunter and
Jaime Moreno and
Joel S. Emer and
Daniel S{\'{a}}nchez},
title = {Contutto: a novel FPGA-based prototyping platform enabling innovation
in the memory subsystem of a server class processor},
booktitle = {Proceedings of the 50th Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 2017, Cambridge, MA, USA, October 14-18,
2017},
pages = {15--26},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3123939.3124535},
doi = {10.1145/3123939.3124535},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/SukhwaniRHKMDSL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/ZyubanFDPPRDZCI15,
author = {Victor V. Zyuban and
Joshua Friedrich and
Daniel M. Dreps and
J{\"{u}}rgen Pille and
Donald W. Plass and
Phillip J. Restle and
Zeynep Toprak Deniz and
Matthew M. Ziegler and
Sam G. Chu and
Md. Saiful Islam and
James D. Warnock and
Bob Philhower and
Rahul M. Rao and
Gregory S. Still and
David Shan and
Eric Fluhr and
Jose Paredes and
Dieter F. Wendel and
Christopher J. Gonzalez and
D. Hogenmiller and
Ruchir Puri and
Scott A. Taylor and
Stephen D. Posluszny},
title = {{IBM} {POWER8} circuit design and energy optimization},
journal = {{IBM} J. Res. Dev.},
volume = {59},
number = {1},
year = {2015},
url = {https://doi.org/10.1147/JRD.2014.2380200},
doi = {10.1147/JRD.2014.2380200},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/ZyubanFDPPRDZCI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15,
author = {Eric J. Fluhr and
Steve Baumgartner and
David W. Boerstler and
John F. Bulzacchelli and
Timothy Diemoz and
Daniel Dreps and
George English and
Joshua Friedrich and
Anne Gattiker and
Tilman Gloekler and
Christopher J. Gonzalez and
Jason Hibbeler and
Keith A. Jenkins and
Yong Kim and
Paul Muench and
Ryan Nett and
Jose Paredes and
Juergen Pille and
Donald W. Plass and
Phillip J. Restle and
Raphael Robertazzi and
David Shan and
David W. Siljenberg and
Michael A. Sperling and
Kevin Stawiasz and
Gregory S. Still and
Zeynep Toprak Deniz and
James D. Warnock and
Glen A. Wiedemeier and
Victor V. Zyuban},
title = {The 12-Core POWER8{\texttrademark} Processor With 7.6 Tb/s {IO} Bandwidth,
Integrated Voltage Regulation, and Resonant Clocking},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {10--23},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2358553},
doi = {10.1109/JSSC.2014.2358553},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockCBFPCCSS15,
author = {James D. Warnock and
Brian W. Curran and
John Badar and
Gregory Fredeman and
Donald W. Plass and
Yuen H. Chan and
Sean M. Carey and
Gerard Salem and
Friedrich Schroeder and
Frank Malgioglio and
Guenter Mayer and
Christopher J. Berry and
Michael H. Wood and
Yiu{-}Hing Chan and
Mark D. Mayo and
John Isakson and
Charudhattan Nagarajan and
Tobias Werner and
Leon J. Sigal and
Ricardo Nigaglioni and
Mark Cichanowski and
Jeffrey A. Zitz and
Matthew M. Ziegler and
Tim Bronson and
Gerald Strevig and
Daniel Dreps and
Ruchir Puri and
Douglas Malone and
Dieter F. Wendel and
Pak{-}kin Mak and
Michael A. Blake},
title = {4.1 22nm Next-generation {IBM} System z microprocessor},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062930},
doi = {10.1109/ISSCC.2015.7062930},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WarnockCBFPCCSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ofc/Dreps15,
author = {Daniel Dreps},
title = {How server designs will change as interface bandwidth demands continue
to increase},
booktitle = {Optical Fiber Communications Conference and Exhibition, {OFC} 2015,
Los Angeles, CA, USA, March 22-26, 2015},
pages = {1},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1364/OFC.2015.M3H.2},
doi = {10.1364/OFC.2015.M3H.2},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/ofc/Dreps15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/FriedrichLSSSFD14,
author = {Joshua Friedrich and
Hung Q. Le and
William J. Starke and
Jeff Stuecheli and
Balaram Sinharoy and
Eric J. Fluhr and
Daniel M. Dreps and
Victor V. Zyuban and
Gregory S. Still and
Christopher J. Gonzalez and
David Hogenmiller and
Frank Malgioglio and
Ryan Nett and
Ruchir Puri and
Phillip J. Restle and
David Shan and
Zeynep Toprak Deniz and
Dieter F. Wendel and
Matthew M. Ziegler and
Dave W. Victor},
title = {The POWER8\({}^{\mbox{TM}}\) processor: Designed for big data, analytics,
and cloud environments},
booktitle = {2014 {IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2014, Austin, TX, USA, May 28-30, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICICDT.2014.6838618},
doi = {10.1109/ICICDT.2014.6838618},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icicdt/FriedrichLSSSFD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FluhrFDZSGHHMNP14,
author = {Eric J. Fluhr and
Joshua Friedrich and
Daniel M. Dreps and
Victor V. Zyuban and
Gregory S. Still and
Christopher J. Gonzalez and
Allen Hall and
David Hogenmiller and
Frank Malgioglio and
Ryan Nett and
Jose Paredes and
Juergen Pille and
Donald W. Plass and
Ruchir Puri and
Phillip J. Restle and
David Shan and
Kevin Stawiasz and
Zeynep Toprak Deniz and
Dieter F. Wendel and
Matthew M. Ziegler},
title = {5.1 POWER8\({}^{\mbox{TM}}\): {A} 12-core server-class processor in
22nm {SOI} with 7.6Tb/s off-chip bandwidth},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {96--97},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757353},
doi = {10.1109/ISSCC.2014.6757353},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FluhrFDZSGHHMNP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ToiflMRRDBPGKBBFM12,
author = {Thomas Toifl and
Christian Menolfi and
Michael Ruegg and
Robert Reutemann and
Daniel Dreps and
Troy J. Beukema and
Andrea Prati and
Daniele Gardellini and
Marcel A. Kossel and
Peter Buchmann and
Matthias Braendli and
Pier Andrea Francese and
Thomas Morf},
title = {A 2.6 mW/Gbps 12.5 Gbps {RX} With 8-Tap Switched-Capacitor {DFE} in
32 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {4},
pages = {897--910},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2185342},
doi = {10.1109/JSSC.2012.2185342},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ToiflMRRDBPGKBBFM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WendelKWCCCDHFIKLMPPRSSSTNWWZ11,
author = {Dieter F. Wendel and
Ronald N. Kalla and
James D. Warnock and
Robert Cargnoni and
Sam G. Chu and
Joachim G. Clabes and
Daniel Dreps and
David Hrusecky and
Joshua Friedrich and
Md. Saiful Islam and
James A. Kahle and
Jens Leenstra and
Gaurav Mittal and
Jose Paredes and
Juergen Pille and
Phillip J. Restle and
Balaram Sinharoy and
George Smith and
William J. Starke and
Scott A. Taylor and
James Van Norstrand and
Stephen Weitzel and
Phillip G. Williams and
Victor V. Zyuban},
title = {POWER7{\texttrademark}, a Highly Parallel, Scalable Multi-Core High
End Server Processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {145--161},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2080611},
doi = {10.1109/JSSC.2010.2080611},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WendelKWCCCDHFIKLMPPRSSSTNWWZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ReutemannRKBDTS10,
author = {Robert Reutemann and
Michael Ruegg and
Fran Keyser and
John Bergkvist and
Daniel Dreps and
Thomas Toifl and
Martin L. Schmatz},
title = {A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core
With Optional Cleanup {PLL} in 65 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {12},
pages = {2850--2860},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2077350},
doi = {10.1109/JSSC.2010.2077350},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ReutemannRKBDTS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/ArimilliBCDSM10,
author = {L. Baba Arimilli and
Steve Baumgartner and
Scott Clark and
Daniel Dreps and
David W. Siljenberg and
Andrew Maki},
title = {The {IBM} {POWER7} {HUB} module: {A} terabyte interconnect switch
for high-performance computer systems},
booktitle = {2010 {IEEE} Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24,
2010},
pages = {1--33},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2010.7480080},
doi = {10.1109/HOTCHIPS.2010.7480080},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/ArimilliBCDSM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ReutemannRKBDTS10,
author = {Robert Reutemann and
Michael Ruegg and
Fran Keyser and
John Bergkvist and
Daniel Dreps and
Thomas Toifl and
Martin L. Schmatz},
title = {A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with
optional cleanup {PLL} in 65nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {160--161},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5434008},
doi = {10.1109/ISSCC.2010.5434008},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ReutemannRKBDTS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MandrekarZCHCNDWH10,
author = {Rohan Mandrekar and
Yaping Zhou and
Sungjun Chun and
Anand Haridass and
Jinwoo Choi and
Nanju Na and
Daniel M. Dreps and
Roger D. Weekly and
Paul Harvey},
title = {Channel Optimization for the Design of High Speed {I/O} links},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {87--92},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.87},
doi = {10.1109/VLSI.DESIGN.2010.87},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/MandrekarZCHCNDWH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/WinkelHKSDCCZSLE09,
author = {Thomas{-}Michael Winkel and
Hubert Harrer and
Dierk Kaller and
Jochen Supper and
Daniel M. Dreps and
Kenneth L. Christian and
D. Cosmadelis and
Tingdong Zhou and
Thomas Strach and
J. Ludwig and
David L. Edwards},
title = {Packaging design challenges of the {IBM} System z10 Enterprise Class
server},
journal = {{IBM} J. Res. Dev.},
volume = {53},
number = {1},
pages = {10},
year = {2009},
url = {https://doi.org/10.1147/JRD.2009.5388589},
doi = {10.1147/JRD.2009.5388589},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/WinkelHKSDCCZSLE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ZhangZDKDBKC09,
author = {Yulei Zhang and
Ling Zhang and
Alina Deutsch and
George A. Katopis and
Daniel M. Dreps and
James F. Buckwalter and
Ernest S. Kuh and
Chung{-}Kuan Cheng},
title = {Design methodology of high performance on-chip global interconnect
using terminated transmission-line},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {451--458},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810337},
doi = {10.1109/ISQED.2009.4810337},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ZhangZDKDBKC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimDFCKRF09,
author = {Kyu{-}Hyoun Kim and
Daniel M. Dreps and
Frank D. Ferraiolo and
Paul W. Coteus and
Seongwon Kim and
Sergey V. Rylov and
Daniel J. Friedman},
title = {A 5.4mW 0.0035mm\({}^{\mbox{2}}\) 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL
all-digital phase generator/rotator in 45nm {SOI} {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {98--99},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977326},
doi = {10.1109/ISSCC.2009.4977326},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimDFCKRF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhangYZDKDKC08,
author = {Ling Zhang and
Wenjian Yu and
Haikun Zhu and
Alina Deutsch and
George A. Katopis and
Daniel M. Dreps and
Ernest S. Kuh and
Chung{-}Kuan Cheng},
editor = {Limor Fix},
title = {Low power passive equalizer optimization using tritonic step response},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {570--573},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391613},
doi = {10.1145/1391469.1391613},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhangYZDKDKC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hoti/ZhangYZWDKDBKC08,
author = {Ling Zhang and
Wenjian Yu and
Yulei Zhang and
Renshen Wang and
Alina Deutsch and
George A. Katopis and
Daniel M. Dreps and
James F. Buckwalter and
Ernest S. Kuh and
Chung{-}Kuan Cheng},
title = {Low Power Passive Equalizer Design for Computer Memory Links},
booktitle = {16th Annual {IEEE} Symposium on High Performance Interconnects {(HOTI}
2008), 26-28 August 2008, Stanford, CA, {USA}},
pages = {51--56},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/HOTI.2008.23},
doi = {10.1109/HOTI.2008.23},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hoti/ZhangYZWDKDBKC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimCDKRF08,
author = {Kyu{-}Hyoun Kim and
Paul W. Coteus and
Daniel M. Dreps and
Seongwon Kim and
Sergey V. Rylov and
Daniel J. Friedman},
title = {A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {458--459},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523255},
doi = {10.1109/ISSCC.2008.4523255},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimCDKRF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/HarrerDWSTHZCG07,
author = {Hubert Harrer and
Daniel M. Dreps and
Thomas{-}Michael Winkel and
Wolfgang Scholz and
Bao G. Truong and
Andreas Huber and
Tingdong Zhou and
Kenneth L. Christian and
Gary F. Goth},
title = {High-speed interconnect and packaging design of the {IBM} System z9
processor cage},
journal = {{IBM} J. Res. Dev.},
volume = {51},
number = {1/2},
pages = {37--52},
year = {2007},
url = {https://doi.org/10.1147/rd.511.0037},
doi = {10.1147/RD.511.0037},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/HarrerDWSTHZCG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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