BibTeX records: Zhixiong Di

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@article{DBLP:journals/tcas/TianHLSDC19,
  author    = {Yinghui Tian and
               Yong Hei and
               Zhizhe Liu and
               Qi Shen and
               Zhixiong Di and
               Tao Chen},
  title     = {A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy
               for Memory-Based {FFT} Processor Design},
  journal   = {{IEEE} Trans. on Circuits and Systems},
  volume    = {66-II},
  number    = {1},
  pages     = {106--110},
  year      = {2019},
  url       = {https://doi.org/10.1109/TCSII.2018.2828648},
  doi       = {10.1109/TCSII.2018.2828648},
  timestamp = {Tue, 25 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/tcas/TianHLSDC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiSD19,
  author    = {Lintao Li and
               Jiangyi Shi and
               Zhixiong Di},
  title     = {High Parallel {VLSI} Architecture Design of {BPC} in {JPEG2000}},
  booktitle = {13th {IEEE} International Conference on ASIC, {ASICON} 2019, Chongqing,
               China, October 29 - November 1, 2019},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/ASICON47005.2019.8983455},
  doi       = {10.1109/ASICON47005.2019.8983455},
  timestamp = {Wed, 12 Feb 2020 16:13:42 +0100},
  biburl    = {https://dblp.org/rec/conf/asicon/LiSD19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/TianHLDSY17,
  author    = {Yinghui Tian and
               Yong Hei and
               Zhizhe Liu and
               Zhixiong Di and
               Qi Shen and
               Zenghui Yu},
  title     = {A memory-based {FFT} processor using modified signal flow graph with
               novel conflict-free address schemes},
  journal   = {{IEICE} Electronic Express},
  volume    = {14},
  number    = {15},
  pages     = {20170660},
  year      = {2017},
  url       = {https://doi.org/10.1587/elex.14.20170660},
  doi       = {10.1587/elex.14.20170660},
  timestamp = {Wed, 13 Sep 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/ieiceee/TianHLDSY17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/TianHLDSY17a,
  author    = {Yinghui Tian and
               Yong Hei and
               Zhizhe Liu and
               Zhixiong Di and
               Qi Shen and
               Zenghui Yu},
  title     = {Erratum: {A} memory-based {FFT} processor using modified signal flow
               graph with novel conflict-free address schemes {[IEICE} Electronics
               Express Vol. 14 {(2017)} No. 15 pp. 20170660]},
  journal   = {{IEICE} Electronic Express},
  volume    = {14},
  number    = {22},
  pages     = {20178005},
  year      = {2017},
  url       = {https://doi.org/10.1587/elex.14.20178005},
  doi       = {10.1587/elex.14.20178005},
  timestamp = {Wed, 28 Mar 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/ieiceee/TianHLDSY17a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/DiHSM15,
  author    = {Zhixiong Di and
               Yue Hao and
               Jiangyi Shi and
               Peijun Ma},
  title     = {A High-Throughput {VLSI} Architecture Design of Arithmetic Encoder
               in {JPEG2000}},
  journal   = {Signal Processing Systems},
  volume    = {81},
  number    = {2},
  pages     = {227--247},
  year      = {2015},
  url       = {https://doi.org/10.1007/s11265-014-0945-5},
  doi       = {10.1007/s11265-014-0945-5},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/vlsisp/DiHSM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/DiWQXF15,
  author    = {Zhixiong Di and
               Yanlong Wang and
               Shuang Qiao and
               Qianyin Xiang and
               Quanyuan Feng},
  title     = {{LC-KO:} {A} congestion-aware and area{\&}timing-oriented placement
               method},
  booktitle = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015,
               Chengdu, China, November 3-6, 2015},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://doi.org/10.1109/ASICON.2015.7516959},
  doi       = {10.1109/ASICON.2015.7516959},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/conf/asicon/DiWQXF15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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